i965: Make a common backend_reg class.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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@ -63,7 +63,7 @@ namespace brw {
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class fs_live_variables;
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}
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class fs_reg {
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class fs_reg : public backend_reg {
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public:
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DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
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@ -90,36 +90,14 @@ public:
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/** Smear a channel of the reg to all channels. */
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fs_reg &set_smear(unsigned subreg);
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/** Register file: GRF, MRF, IMM. */
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enum register_file file;
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/** Register type. BRW_REGISTER_TYPE_* */
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uint8_t type;
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/**
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* Register number. For MRF, it's the hardware register. For
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* GRF, it's a virtual register number until register allocation
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*/
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uint16_t reg;
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/**
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* Offset from the start of the contiguous register block.
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*
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* For pre-register-allocation GRFs, this is in units of a float per pixel
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* (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
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* For uniforms, this is in units of 1 float.
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*/
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int reg_offset;
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/**
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* Offset in bytes from the start of the register. Values up to a
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* backend_reg::reg_offset unit are valid.
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*/
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int subreg_offset;
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struct brw_reg fixed_hw_reg;
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fs_reg *reladdr;
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bool negate;
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bool abs;
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/** Register region horizontal stride */
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uint8_t stride;
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};
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@ -22,6 +22,7 @@
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*/
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#include <stdint.h>
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#include "brw_reg.h"
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#include "brw_defines.h"
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#include "main/compiler.h"
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#include "glsl/ir.h"
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@ -39,6 +40,37 @@ enum PACKED register_file {
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UNIFORM, /* prog_data->params[reg] */
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};
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struct backend_reg
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{
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enum register_file file; /**< Register file: GRF, MRF, IMM. */
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uint8_t type; /**< Register type: BRW_REGISTER_TYPE_* */
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/**
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* Register number.
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*
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* For GRF, it's a virtual register number until register allocation.
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*
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* For MRF, it's the hardware register.
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*/
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uint16_t reg;
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/**
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* Offset within the virtual register.
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*
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* In the scalar backend, this is in units of a float per pixel for pre-
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* register allocation registers (i.e., one register in SIMD8 mode and two
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* registers in SIMD16 mode).
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*
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* For uniforms, this is in units of 1 float.
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*/
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int reg_offset;
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struct brw_reg fixed_hw_reg;
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bool negate;
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bool abs;
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};
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#ifdef __cplusplus
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class cfg_t;
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@ -91,21 +91,7 @@ class dst_reg;
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unsigned
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swizzle_for_size(int size);
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class reg
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{
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public:
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/** Register file: GRF, MRF, IMM. */
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enum register_file file;
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/** virtual register number. 0 = fixed hw reg */
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int reg;
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/** Offset within the virtual register. */
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int reg_offset;
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/** Register type. BRW_REGISTER_TYPE_* */
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int type;
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struct brw_reg fixed_hw_reg;
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};
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class src_reg : public reg
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class src_reg : public backend_reg
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{
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public:
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DECLARE_RALLOC_CXX_OPERATORS(src_reg)
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@ -129,8 +115,6 @@ public:
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explicit src_reg(dst_reg reg);
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GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
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bool negate;
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bool abs;
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src_reg *reladdr;
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};
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@ -174,7 +158,7 @@ negate(src_reg reg)
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return reg;
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}
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class dst_reg : public reg
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class dst_reg : public backend_reg
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{
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public:
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DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
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@ -34,7 +34,7 @@ using namespace brw;
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namespace brw {
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static void
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assign(unsigned int *reg_hw_locations, reg *reg)
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assign(unsigned int *reg_hw_locations, backend_reg *reg)
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{
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if (reg->file == GRF) {
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reg->reg = reg_hw_locations[reg->reg];
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