freedreno/ir3: move disasm and optmsgs debug flags
Move them to IR3_SHADER_DEBUG so we can remove ir3's dependency on fd_mesa_debug. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
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424d75656f
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bfd8d26372
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@ -64,7 +64,7 @@
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static const struct debug_named_value debug_options[] = {
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{"msgs", FD_DBG_MSGS, "Print debug messages"},
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{"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
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{"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
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{"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
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{"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
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{"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
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@ -72,7 +72,6 @@ static const struct debug_named_value debug_options[] = {
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{"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"},
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{"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
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{"nobin", FD_DBG_NOBIN, "Disable hw binning"},
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{"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
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{"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
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{"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
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{"flush", FD_DBG_FLUSH, "Force flush after every draw"},
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@ -70,7 +70,7 @@ enum adreno_stencil_op fd_stencil_op(unsigned op);
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#define FD_DBG_NOBYPASS 0x0040
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#define FD_DBG_FRAGHALF 0x0080
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#define FD_DBG_NOBIN 0x0100
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#define FD_DBG_OPTMSGS 0x0200
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/* unused 0x0200 */
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#define FD_DBG_GLSL120 0x0400
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#define FD_DBG_SHADERDB 0x0800
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#define FD_DBG_FLUSH 0x1000
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@ -297,7 +297,7 @@ int main(int argc, char **argv)
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while (n < argc) {
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if (!strcmp(argv[n], "--verbose")) {
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fd_mesa_debug |= FD_DBG_MSGS | FD_DBG_OPTMSGS | FD_DBG_DISASM;
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ir3_shader_debug |= IR3_DBG_OPTMSGS | IR3_DBG_DISASM;
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n++;
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continue;
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}
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@ -452,13 +452,13 @@ int main(int argc, char **argv)
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return ret;
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}
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if (fd_mesa_debug & FD_DBG_OPTMSGS)
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if (ir3_shader_debug & IR3_DBG_OPTMSGS)
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debug_printf("%s\n", (char *)ptr);
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if (!tgsi_text_translate(ptr, toks, ARRAY_SIZE(toks)))
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errx(1, "could not parse `%s'", filenames[0]);
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if (fd_mesa_debug & FD_DBG_OPTMSGS)
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if (ir3_shader_debug & IR3_DBG_OPTMSGS)
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tgsi_dump(toks, 0);
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nir = ir3_tgsi_to_nir(toks);
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@ -32,6 +32,8 @@ static const struct debug_named_value shader_debug_options[] = {
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{"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
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{"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
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{"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
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{"disasm", IR3_DBG_DISASM, "Dump NIR and adreno shader disassembly"},
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{"optmsgs", IR3_DBG_OPTMSGS,"Enable optimizer debug messages"},
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DEBUG_NAMED_VALUE_END
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};
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@ -74,6 +74,8 @@ enum ir3_shader_debug {
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IR3_DBG_SHADER_VS = 0x01,
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IR3_DBG_SHADER_FS = 0x02,
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IR3_DBG_SHADER_CS = 0x04,
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IR3_DBG_DISASM = 0x08,
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IR3_DBG_OPTMSGS = 0x10,
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};
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extern enum ir3_shader_debug ir3_shader_debug;
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@ -181,7 +181,7 @@ compile_init(struct ir3_compiler *compiler,
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NIR_PASS_V(ctx->s, nir_lower_locals_to_regs);
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NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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DBG("dump nir%dv%d: type=%d, k={cts=%u,hp=%u}",
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so->shader->id, so->id, so->type,
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so->key.color_two_side, so->key.half_precision);
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@ -3680,7 +3680,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
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}
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}
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if (fd_mesa_debug & FD_DBG_OPTMSGS) {
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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printf("BEFORE CP:\n");
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ir3_print(ir);
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}
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@ -3709,7 +3709,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
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}
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}
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if (fd_mesa_debug & FD_DBG_OPTMSGS) {
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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printf("BEFORE GROUPING:\n");
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ir3_print(ir);
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}
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@ -3721,14 +3721,14 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
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*/
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ir3_group(ir);
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if (fd_mesa_debug & FD_DBG_OPTMSGS) {
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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printf("AFTER GROUPING:\n");
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ir3_print(ir);
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}
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ir3_depth(ir);
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if (fd_mesa_debug & FD_DBG_OPTMSGS) {
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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printf("AFTER DEPTH:\n");
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ir3_print(ir);
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}
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@ -3739,7 +3739,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
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goto out;
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}
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if (fd_mesa_debug & FD_DBG_OPTMSGS) {
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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printf("AFTER SCHED:\n");
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ir3_print(ir);
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}
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@ -3750,7 +3750,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
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goto out;
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}
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if (fd_mesa_debug & FD_DBG_OPTMSGS) {
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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printf("AFTER RA:\n");
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ir3_print(ir);
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}
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@ -3800,7 +3800,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
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*/
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ir3_legalize(ir, &so->num_samp, &so->has_ssbo, &max_bary);
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if (fd_mesa_debug & FD_DBG_OPTMSGS) {
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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printf("AFTER LEGALIZE:\n");
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ir3_print(ir);
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}
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@ -161,7 +161,7 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
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tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
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}
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if (fd_mesa_debug & FD_DBG_DISASM) {
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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debug_printf("----------------------\n");
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nir_print_shader(s, stdout);
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debug_printf("----------------------\n");
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@ -207,7 +207,7 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
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OPT_V(s, nir_move_load_const);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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debug_printf("----------------------\n");
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nir_print_shader(s, stdout);
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debug_printf("----------------------\n");
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@ -867,7 +867,7 @@ ra_add_interference(struct ir3_ra_ctx *ctx)
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/* update per-block livein/liveout: */
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while (ra_compute_livein_liveout(ctx)) {}
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if (fd_mesa_debug & FD_DBG_OPTMSGS) {
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if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
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debug_printf("AFTER LIVEIN/OUT:\n");
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ir3_print(ir);
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list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
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@ -143,7 +143,7 @@ assemble_variant(struct ir3_shader_variant *v)
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memcpy(fd_bo_map(v->bo), bin, sz);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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struct ir3_shader_key key = v->key;
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printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
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v->binning_pass, key.color_two_side, key.half_precision);
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@ -327,7 +327,7 @@ ir3_shader_create(struct ir3_compiler *compiler,
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nir = cso->ir.nir;
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} else {
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debug_assert(cso->type == PIPE_SHADER_IR_TGSI);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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DBG("dump tgsi: type=%d", shader->type);
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tgsi_dump(cso->tokens, 0);
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}
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@ -337,7 +337,7 @@ ir3_shader_create(struct ir3_compiler *compiler,
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(nir_lower_io_options)0);
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/* do first pass optimization, ignoring the key: */
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shader->nir = ir3_optimize_nir(shader, nir, NULL);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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DBG("dump nir%d: type=%d", shader->id, shader->type);
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nir_print_shader(shader->nir, stdout);
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}
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@ -378,7 +378,7 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
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(nir_lower_io_options)0);
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} else {
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debug_assert(cso->ir_type == PIPE_SHADER_IR_TGSI);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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DBG("dump tgsi: type=%d", shader->type);
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tgsi_dump(cso->prog, 0);
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}
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@ -387,7 +387,7 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
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/* do first pass optimization, ignoring the key: */
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shader->nir = ir3_optimize_nir(shader, nir, NULL);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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printf("dump nir%d: type=%d\n", shader->id, shader->type);
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nir_print_shader(shader->nir, stdout);
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}
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