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radeonsi: Disable clear_state with radeon kernel driver 

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Sonny Jiang 2018-10-19 16:16:41 -04:00 committed by Marek Olšák
parent f91f9bab83
commit bfb2b90246
2 changed files with 7 additions and 4 deletions
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6
src/gallium/drivers/radeonsi/si_pipe.c
View File

@ -993,8 +993,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
}
/* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
* on SI. */
sscreen->has_clear_state = sscreen->info.chip_class >= CIK;
* on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
* SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
sscreen->has_clear_state = sscreen->info.chip_class >= CIK &&
sscreen->info.drm_major == 3;
sscreen->has_distributed_tess =
sscreen->info.chip_class >= VI &&

5
src/gallium/drivers/radeonsi/si_state.c
View File

@ -4899,8 +4899,9 @@ static void si_init_config(struct si_context *sctx)
bool has_clear_state = sscreen->has_clear_state;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
/* Only SI can disable CLEAR_STATE for now. */
assert(has_clear_state || sscreen->info.chip_class == SI);
/* SI, radeon kernel disabled CLEAR_STATE. */
assert(has_clear_state || sscreen->info.chip_class == SI ||
sscreen->info.drm_major != 3);
if (!pm4)
return;