vc4: Add support for the TGSI TRUNC opcode.
v2: Rebase on helpers.
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399285403a
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@ -292,6 +292,16 @@ tgsi_to_qir_pow(struct tgsi_to_qir *trans,
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qir_LOG2(c, src[0 * 4 + 0])));
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}
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static struct qreg
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tgsi_to_qir_trunc(struct tgsi_to_qir *trans,
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struct tgsi_full_instruction *tgsi_inst,
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enum qop op, struct qreg *src, int i)
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{
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struct qcompile *c = trans->c;
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return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
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}
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static struct qreg
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tgsi_to_qir_dp(struct tgsi_to_qir *trans,
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struct tgsi_full_instruction *tgsi_inst,
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@ -413,6 +423,7 @@ emit_tgsi_instruction(struct tgsi_to_qir *trans,
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[TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
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[TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
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[TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
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[TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
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};
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static int asdf = 0;
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uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
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@ -52,6 +52,7 @@ static const struct qir_op_info qir_op_info[] = {
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[QOP_CMP] = { "cmp", 1, 3 },
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[QOP_FTOI] = { "ftoi", 1, 1 },
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[QOP_ITOF] = { "itof", 1, 1 },
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[QOP_RCP] = { "rcp", 1, 1 },
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[QOP_RSQ] = { "rsq", 1, 1 },
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[QOP_EXP2] = { "exp2", 1, 2 },
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@ -59,6 +59,7 @@ enum qop {
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QOP_CMP,
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QOP_FTOI,
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QOP_ITOF,
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QOP_RCP,
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QOP_RSQ,
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QOP_EXP2,
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@ -186,6 +187,7 @@ QIR_ALU2(FMAX)
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QIR_ALU2(FMINABS)
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QIR_ALU2(FMAXABS)
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QIR_ALU1(FTOI)
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QIR_ALU1(ITOF)
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QIR_ALU1(RCP)
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QIR_ALU1(RSQ)
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QIR_ALU1(EXP2)
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@ -249,6 +249,7 @@ vc4_generate_code(struct qcompile *c)
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A(FMINABS),
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A(FMAXABS),
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A(FTOI),
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A(ITOF),
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M(FMUL),
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};
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