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radv: only mask 1 CU for GS/VS waves on GFX10.3 

Ported from Radeonsi and PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7769>
This commit is contained in:
Samuel Pitoiset 2020-11-25 08:16:14 +01:00 committed by Marge Bot
parent 7729ea3d67
commit bf36cfced1
1 changed files with 11 additions and 5 deletions
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16
src/amd/vulkan/si_cmd_buffer.c
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@ -347,12 +347,18 @@ si_emit_graphics(struct radv_device *device,
} else {
late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
/* CU2 & CU3 disabled because of the dual CU design */
cu_mask_vs = 0xfff3;
/* Gfx10: CU2 & CU3 must be disabled to
* prevent a hw deadlock. Others: CU1 must be
* disabled to prevent a hw deadlock.
*
* The deadlock is caused by late alloc, which
* usually increases performance.
*/
cu_mask_vs &= physical_device->rad_info.chip_class == GFX10 ?
~BITFIELD_RANGE(2, 2) : ~BITFIELD_RANGE(1, 1);
if (physical_device->use_ngg) {
cu_mask_gs = 0xfff3;
} else {
cu_mask_gs = 0xffff;
cu_mask_gs = cu_mask_vs;
}
}