radv/gfx10: add gfx10_make_texture_descriptor
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
Bas Nieuwenhuizen
parent
3dc5ec5d16
commit
bf11f1c3a4
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@ -572,7 +572,134 @@ static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
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}
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/**
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* Build the sampler view descriptor for a texture.
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* Build the sampler view descriptor for a texture (GFX10).
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*/
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static void
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gfx10_make_texture_descriptor(struct radv_device *device,
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struct radv_image *image,
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bool is_storage_image,
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VkImageViewType view_type,
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VkFormat vk_format,
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const VkComponentMapping *mapping,
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unsigned first_level, unsigned last_level,
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unsigned first_layer, unsigned last_layer,
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unsigned width, unsigned height, unsigned depth,
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uint32_t *state,
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uint32_t *fmask_state)
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{
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const struct vk_format_description *desc;
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enum vk_swizzle swizzle[4];
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unsigned img_format;
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unsigned type;
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desc = vk_format_description(vk_format);
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img_format = gfx10_format_table[vk_format].img_format;
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if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
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const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
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vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
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} else {
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vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
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}
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type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
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is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
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if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
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height = 1;
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depth = image->info.array_size;
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} else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
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type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
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if (view_type != VK_IMAGE_VIEW_TYPE_3D)
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depth = image->info.array_size;
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} else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
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depth = image->info.array_size / 6;
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state[0] = 0;
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state[1] = S_00A004_FORMAT(img_format) |
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S_00A004_WIDTH_LO(width - 1);
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state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
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S_00A008_HEIGHT(height - 1) |
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S_00A008_RESOURCE_LEVEL(1);
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state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
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S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
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S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
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S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
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S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
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0 : first_level) |
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S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
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util_logbase2(image->info.samples) :
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last_level) |
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S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
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S_00A00C_TYPE(type);
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/* Depth is the the last accessible layer on gfx9+. The hw doesn't need
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* to know the total number of layers.
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*/
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state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
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S_00A010_BASE_ARRAY(first_layer);
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state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
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S_00A014_MAX_MIP(image->info.samples > 1 ?
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util_logbase2(image->info.samples) :
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image->info.levels - 1) |
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S_00A014_PERF_MOD(4);
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state[6] = 0;
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state[7] = 0;
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if (radv_dcc_enabled(image, first_level)) {
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unsigned swap = radv_translate_colorswap(vk_format, FALSE);
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state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
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S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
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S_00A018_ALPHA_IS_ON_MSB(swap <= 1);
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}
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/* Initialize the sampler view for FMASK. */
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if (radv_image_has_fmask(image)) {
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uint64_t gpu_address = radv_buffer_get_va(image->bo);
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uint32_t format;
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uint64_t va;
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assert(image->plane_count == 1);
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va = gpu_address + image->offset + image->fmask.offset;
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switch (image->info.samples) {
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case 2:
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format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
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break;
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case 4:
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format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
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break;
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case 8:
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format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
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break;
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default:
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unreachable("invalid nr_samples");
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}
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fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
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fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
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S_00A004_FORMAT(format) |
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S_00A004_WIDTH_LO(width - 1);
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fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
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S_00A008_HEIGHT(height - 1) |
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S_00A008_RESOURCE_LEVEL(1);
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fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
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S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
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S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
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S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
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fmask_state[4] = S_00A010_DEPTH(last_layer) |
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S_00A010_BASE_ARRAY(first_layer);
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fmask_state[5] = 0;
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fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
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fmask_state[7] = 0;
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} else if (fmask_state)
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memset(fmask_state, 0, 8 * 4);
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}
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/**
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* Build the sampler view descriptor for a texture (SI-GFX9)
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*/
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static void
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si_make_texture_descriptor(struct radv_device *device,
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@ -782,6 +909,36 @@ si_make_texture_descriptor(struct radv_device *device,
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memset(fmask_state, 0, 8 * 4);
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}
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static void
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radv_make_texture_descriptor(struct radv_device *device,
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struct radv_image *image,
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bool is_storage_image,
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VkImageViewType view_type,
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VkFormat vk_format,
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const VkComponentMapping *mapping,
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unsigned first_level, unsigned last_level,
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unsigned first_layer, unsigned last_layer,
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unsigned width, unsigned height, unsigned depth,
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uint32_t *state,
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uint32_t *fmask_state)
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{
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if (device->physical_device->rad_info.chip_class >= GFX10) {
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gfx10_make_texture_descriptor(device, image, is_storage_image,
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view_type, vk_format, mapping,
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first_level, last_level,
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first_layer, last_layer,
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width, height, depth,
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state, fmask_state);
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} else {
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si_make_texture_descriptor(device, image, is_storage_image,
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view_type, vk_format, mapping,
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first_level, last_level,
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first_layer, last_layer,
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width, height, depth,
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state, fmask_state);
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}
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}
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static void
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radv_query_opaque_metadata(struct radv_device *device,
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struct radv_image *image,
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@ -807,13 +964,13 @@ radv_query_opaque_metadata(struct radv_device *device,
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md->metadata[1] = si_get_bo_metadata_word1(device);
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si_make_texture_descriptor(device, image, false,
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(VkImageViewType)image->type, image->vk_format,
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&fixedmapping, 0, image->info.levels - 1, 0,
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image->info.array_size - 1,
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image->info.width, image->info.height,
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image->info.depth,
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desc, NULL);
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radv_make_texture_descriptor(device, image, false,
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(VkImageViewType)image->type, image->vk_format,
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&fixedmapping, 0, image->info.levels - 1, 0,
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image->info.array_size - 1,
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image->info.width, image->info.height,
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image->info.depth,
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desc, NULL);
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si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
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image->planes[0].surface.blk_w, false, false, desc);
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@ -1250,18 +1407,18 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
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if (device->physical_device->rad_info.chip_class >= GFX9)
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hw_level = iview->base_mip;
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si_make_texture_descriptor(device, image, is_storage_image,
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iview->type,
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vk_format,
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components,
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hw_level, hw_level + iview->level_count - 1,
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iview->base_layer,
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iview->base_layer + iview->layer_count - 1,
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iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
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iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
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iview->extent.depth,
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descriptor->plane_descriptors[descriptor_plane_id],
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descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
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radv_make_texture_descriptor(device, image, is_storage_image,
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iview->type,
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vk_format,
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components,
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hw_level, hw_level + iview->level_count - 1,
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iview->base_layer,
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iview->base_layer + iview->layer_count - 1,
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iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
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iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
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iview->extent.depth,
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descriptor->plane_descriptors[descriptor_plane_id],
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descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
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const struct legacy_surf_level *base_level_info = NULL;
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if (device->physical_device->rad_info.chip_class <= GFX9) {
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