freedreno/a6xx: Track location of gl_Position out as we link it
When using xfb and rasterizing, the fragment shader may have fewer inputs than the vertex shader outputs. We can't rely on gl_Position to be placed at fs->total_in, but have to instead remember where we add it in the link map and use that location. Fixes 100+ tesselation dEQPs under dEQP-GLES31.functional.tessellation.primitive_discard.* dEQP-GLES31.functional.tessellation.user_defined_io.* Reviewed-by: Eric Anholt <eric@anholt.net>
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@ -2423,7 +2423,7 @@ to upconvert to 32b float internally?
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hw streamout (rather than stg instructions in shader)
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</doc>
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<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
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<bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/>
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<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
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<!--
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This seems to be the OUTLOC for the psize output. It could possibly
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be the max-OUTLOC position, but it is only set when VS writes psize
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@ -2434,14 +2434,10 @@ to upconvert to 32b float internally?
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<reg32 offset="0x9303" name="VPC_PACK_3">
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<doc>
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domain shader version
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num of varyings plus four for gl_Position (plus one if gl_PointSize)
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plus # of transform-feedback (streamout) varyings if using the
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hw streamout (rather than stg instructions in shader)
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domain shader version of VPC_PACK
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</doc>
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<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
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<bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/>
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<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
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<!--
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This seems to be the OUTLOC for the psize output. It could possibly
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be the max-OUTLOC position, but it is only set when VS writes psize
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@ -523,9 +523,11 @@ tu6_emit_vpc(struct tu_cs *cs,
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ir3_find_output_regid(vs, VARYING_SLOT_POS);
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const uint32_t pointsize_regid =
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ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
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uint32_t pointsize_loc = 0xff;
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if (position_regid != regid(63, 0))
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uint32_t pointsize_loc = 0xff, position_loc = 0xff;
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if (position_regid != regid(63, 0)) {
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position_loc = linkage.max_loc;
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ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
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}
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if (pointsize_regid != regid(63, 0)) {
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pointsize_loc = linkage.max_loc;
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ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
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@ -559,7 +561,7 @@ tu6_emit_vpc(struct tu_cs *cs,
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0xff00ff00);
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
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tu_cs_emit(cs, A6XX_VPC_PACK_NUMNONPOSVAR(fs->total_in) |
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tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
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A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
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A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
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@ -275,7 +275,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
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uint32_t vertex_regid, instance_regid;
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uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
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enum a3xx_threadsize fssz;
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uint8_t psize_loc = ~0;
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uint8_t psize_loc = ~0, pos_loc = ~0;
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int i, j;
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static const struct ir3_shader_variant dummy_fs = {0};
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@ -393,8 +393,10 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
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OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
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/* a6xx appends pos/psize to end of the linkage map: */
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if (VALIDREG(pos_regid))
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if (VALIDREG(pos_regid)) {
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pos_loc = l.max_loc;
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ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
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}
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if (VALIDREG(psize_regid)) {
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psize_loc = l.max_loc;
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@ -551,7 +553,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
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}
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OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
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OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(fs->total_in) |
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OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
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A6XX_VPC_PACK_PSIZELOC(psize_loc) |
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A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
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