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dzn: Fix indentation 

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Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17140>
This commit is contained in:
Boris Brezillon 2022-06-20 13:52:14 +02:00 committed by Marge Bot
parent aab5d176b8
commit be019e69e2
4 changed files with 10 additions and 10 deletions
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2
src/microsoft/vulkan/dzn_descriptor_set.c
View File

@ -1973,7 +1973,7 @@ dzn_descriptor_update_template_create(struct dzn_device *device,
entry->type = type;
entry->desc_count = MIN2(desc_count - d, ndescs);
entry->user_data.stride = user_data_stride;
entry->user_data.stride = user_data_stride;
entry->user_data.offset = user_data_offset;
memset(&entry->heap_offsets, ~0, sizeof(entry->heap_offsets));

2
src/microsoft/vulkan/dzn_device.c
View File

@ -2175,7 +2175,7 @@ dzn_device_memory_create(struct dzn_device *device,
buffer = dzn_buffer_from_handle(dedicated->buffer);
image = dzn_image_from_handle(dedicated->image);
assert(!buffer || !image);
break;
break;
}
default:
dzn_debug_ignored_stype(ext->sType);

6
src/microsoft/vulkan/dzn_nir.c
View File

@ -233,9 +233,9 @@ dzn_nir_indirect_draw_shader(enum dzn_indirect_draw_type type)
if (prim_restart) {
triangle_fan_exec_vals[triangle_fan_exec_param_count++] = nir_channel(&b, draw_info1, 2);
triangle_fan_exec_vals[triangle_fan_exec_param_count++] = nir_channel(&b, draw_info1, 0);
uint32_t index_count_offset =
uint32_t index_count_offset =
offsetof(struct dzn_indirect_triangle_fan_draw_exec_params, indexed_draw.index_count);
nir_ssa_def *exec_buf_start =
nir_ssa_def *exec_buf_start =
nir_load_ubo(&b, 2, 32,
params_desc, nir_imm_int(&b, 16),
.align_mul = 4, .align_offset = 0, .range_base = 0, .range = ~0);
@ -243,7 +243,7 @@ dzn_nir_indirect_draw_shader(enum dzn_indirect_draw_type type)
nir_iadd(&b, nir_imm_int(&b, index_count_offset),
nir_iadd(&b, nir_channel(&b, exec_buf_start, 0),
nir_imul(&b, exec_stride, index)));
addr_lo_overflow = nir_ult(&b, exec_buf_start_lo, nir_channel(&b, exec_buf_start, 0));
addr_lo_overflow = nir_ult(&b, exec_buf_start_lo, nir_channel(&b, exec_buf_start, 0));
nir_ssa_def *exec_buf_start_hi =
nir_iadd(&b, nir_channel(&b, exec_buf_start, 0),
nir_bcsel(&b, addr_lo_overflow, nir_imm_int(&b, 1), nir_imm_int(&b, 0)));

10
src/microsoft/vulkan/dzn_pipeline.c
View File

@ -426,9 +426,9 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
gl_shader_stage prev_stage =
util_last_bit(active_stage_mask & BITFIELD_MASK(MESA_SHADER_FRAGMENT)) - 1;
/* Disable rasterization if the last geometry stage doesn't
* write the position.
*/
if (prev_stage == MESA_SHADER_NONE ||
* write the position.
*/
if (prev_stage == MESA_SHADER_NONE ||
!(stages[prev_stage].nir->info.outputs_written & VARYING_BIT_POS))
continue;
}
@ -1226,7 +1226,7 @@ dzn_graphics_pipeline_create(struct dzn_device *device,
const struct vk_render_pass_attachment *attachment =
&pass->attachments[subpass->depth_stencil_attachment->attachment];
zs_fmt = attachment->format;
zs_fmt = attachment->format;
}
} else if (ri) {
color_count = ri->colorAttachmentCount;
@ -1374,7 +1374,7 @@ dzn_graphics_pipeline_get_state(struct dzn_graphics_pipeline *pipeline,
ds->BackFace.StencilFunc != D3D12_COMPARISON_FUNC_NEVER &&
ds->BackFace.StencilFunc != D3D12_COMPARISON_FUNC_ALWAYS)
assert(masked_key.stencil_test.front.compare_mask == masked_key.stencil_test.back.compare_mask);
}
}
if (pipeline->zsa.stencil_test.dynamic_write_mask) {
assert(!masked_key.stencil_test.front.write_mask ||