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intel/fs: Replace fs_visitor::bank_conflict_cycles() with stand-alone function. 

This will be re-usable by the IR performance analysis pass.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2020-04-02 16:20:34 -07:00
parent d2ed740795
commit bda1d72dd9
4 changed files with 17 additions and 17 deletions
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1
src/intel/compiler/brw_fs.h
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@ -167,7 +167,6 @@ public:
bool opt_drop_redundant_mov_to_flags(); bool opt_drop_redundant_mov_to_flags();
bool opt_register_renaming(); bool opt_register_renaming();
bool opt_bank_conflicts(); bool opt_bank_conflicts();
unsigned bank_conflict_cycles(const fs_inst *inst) const;
bool register_coalesce(); bool register_coalesce();
bool compute_to_mrf(); bool compute_to_mrf();
bool eliminate_find_live_channel(); bool eliminate_find_live_channel();

22
src/intel/compiler/brw_fs_bank_conflicts.cpp
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@ -935,20 +935,16 @@ fs_visitor::opt_bank_conflicts()
} }
/** /**
* Estimate the number of GRF bank conflict cycles incurred by an instruction. * Return whether the instruction incurs GRF bank conflict cycles.
* *
* Note that this neglects conflict cycles prior to register allocation * Note that this is only accurate after register allocation because otherwise
* because we don't know which bank each VGRF is going to end up aligned to. * we don't know which bank each VGRF is going to end up aligned to.
*/ */
unsigned bool
fs_visitor::bank_conflict_cycles(const fs_inst *inst) const has_bank_conflict(const gen_device_info *devinfo, const fs_inst *inst)
{ {
if (grf_used && inst->is_3src(devinfo) && return inst->is_3src(devinfo) &&
is_grf(inst->src[1]) && is_grf(inst->src[2]) && is_grf(inst->src[1]) && is_grf(inst->src[2]) &&
bank_of(reg_of(inst->src[1])) == bank_of(reg_of(inst->src[2])) && bank_of(reg_of(inst->src[1])) == bank_of(reg_of(inst->src[2])) &&
!is_conflict_optimized_out(devinfo, inst)) { !is_conflict_optimized_out(devinfo, inst);
return DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE);
} else {
return 0;
}
} }

3
src/intel/compiler/brw_ir_fs.h
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@ -667,4 +667,7 @@ is_coalescing_payload(const brw::simple_allocator &alloc, const fs_inst *inst)
alloc.sizes[inst->src[0].nr] * REG_SIZE == inst->size_written; alloc.sizes[inst->src[0].nr] * REG_SIZE == inst->size_written;
} }
bool
has_bank_conflict(const gen_device_info *devinfo, const fs_inst *inst);
#endif #endif

8
src/intel/compiler/brw_schedule_instructions.cpp
View File

@ -1649,10 +1649,12 @@ vec4_instruction_scheduler::choose_instruction_to_schedule()
} }
int int
fs_instruction_scheduler::issue_time(backend_instruction *inst) fs_instruction_scheduler::issue_time(backend_instruction *inst0)
{ {
const unsigned overhead = v->bank_conflict_cycles((fs_inst *)inst); const fs_inst *inst = static_cast<fs_inst *>(inst0);
if (is_compressed((fs_inst *)inst)) const unsigned overhead = v->grf_used && has_bank_conflict(v->devinfo, inst) ?
DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE) : 0;
if (is_compressed(inst))
return 4 + overhead; return 4 + overhead;
else else
return 2 + overhead; return 2 + overhead;