KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

r600g: split cayman common state out into a shared function 

And use it for compute.  This should improve compute support
on cayman.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Alex Deucher 2012-10-23 12:24:45 -04:00
parent 67c875117c
commit bd274eb8f4
3 changed files with 35 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/gallium/drivers/r600/evergreen_compute.c
View File

@ -681,8 +681,12 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
}
/* Config Registers */
evergreen_init_common_regs(cb, ctx->chip_class
, ctx->family, ctx->screen->info.drm_minor);
if (ctx->chip_class < CAYMAN)
evergreen_init_common_regs(cb, ctx->chip_class, ctx->family,
ctx->screen->info.drm_minor);
else
cayman_init_common_regs(cb, ctx->chip_class, ctx->family,
ctx->screen->info.drm_minor);
/* The primitive type always needs to be POINTLIST for compute. */
r600_store_config_reg(cb, R_008958_VGT_PRIMITIVE_TYPE,

39
src/gallium/drivers/r600/evergreen_state.c
View File

@ -2427,6 +2427,29 @@ void evergreen_init_state_functions(struct r600_context *rctx)
evergreen_init_compute_state_functions(rctx);
}
void cayman_init_common_regs(struct r600_command_buffer *cb,
enum chip_class ctx_chip_class,
enum radeon_family ctx_family,
int ctx_drm_minor)
{
r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
/* always set the temp clauses */
r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
}
static void cayman_init_atom_start_cs(struct r600_context *rctx)
{
struct r600_command_buffer *cb = &rctx->start_cs_cmd;
@ -2442,18 +2465,8 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
/* always set the temp clauses */
r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
cayman_init_common_regs(cb, rctx->chip_class,
rctx->family, rctx->screen->info.drm_minor);
r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
@ -2622,8 +2635,6 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, 0);
r600_store_value(cb, 0);
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
if (rctx->screen->has_streamout) {
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}

4
src/gallium/drivers/r600/r600_pipe.h
View File

@ -513,6 +513,10 @@ void evergreen_init_common_regs(struct r600_command_buffer *cb,
enum chip_class ctx_chip_class,
enum radeon_family ctx_family,
int ctx_drm_minor);
void cayman_init_common_regs(struct r600_command_buffer *cb,
enum chip_class ctx_chip_class,
enum radeon_family ctx_family,
int ctx_drm_minor);
void evergreen_init_state_functions(struct r600_context *rctx);
void evergreen_init_atom_start_cs(struct r600_context *rctx);