diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 347230012aa..ed7b8c12b26 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -403,6 +403,9 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
    ctx->flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
                  SI_CONTEXT_INV_L2 | SI_CONTEXT_START_PIPELINE_STATS;
 
+   radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->border_color_buffer,
+                             RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS);
+
    ctx->cs_shader_state.initialized = false;
    si_add_all_descriptors_to_bo_list(ctx);
    si_shader_pointers_mark_dirty(ctx);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 485716678f4..95775b4207d 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5348,7 +5348,6 @@ static void si_init_config(struct si_context *sctx)
    if (sctx->chip_class >= GFX7) {
       si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, S_028084_ADDRESS(border_color_va >> 40));
    }
-   si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS);
 
    if (sctx->chip_class >= GFX9) {
       si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,