swr/rast: New execution engine per JIT
Fixes relocation errors with LLVM 7.0.0
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b135db5d58
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@ -63,39 +63,29 @@ JitManager::JitManager(uint32_t simdWidth, const char* arch, const char* core) :
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mContext(), mBuilder(mContext), mIsModuleFinalized(true), mJitNumber(0), mVWidth(simdWidth),
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mArch(arch)
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{
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mpCurrentModule = nullptr;
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mpExec = nullptr;
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InitializeNativeTarget();
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InitializeNativeTargetAsmPrinter();
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InitializeNativeTargetDisassembler();
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TargetOptions tOpts;
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tOpts.AllowFPOpFusion = FPOpFusion::Fast;
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tOpts.NoInfsFPMath = false;
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tOpts.NoNaNsFPMath = false;
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tOpts.UnsafeFPMath = false;
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// tOpts.PrintMachineCode = true;
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std::unique_ptr<Module> newModule(new Module("", mContext));
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mpCurrentModule = newModule.get();
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StringRef hostCPUName;
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// force JIT to use the same CPU arch as the rest of swr
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if (mArch.AVX512F())
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{
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#if USE_SIMD16_SHADERS
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if (mArch.AVX512ER())
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{
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hostCPUName = StringRef("knl");
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mHostCpuName = StringRef("knl");
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}
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else
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{
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hostCPUName = StringRef("skylake-avx512");
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mHostCpuName = StringRef("skylake-avx512");
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}
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mUsingAVX512 = true;
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#else
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hostCPUName = StringRef("core-avx2");
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mHostCpuName = StringRef("core-avx2");
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#endif
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if (mVWidth == 0)
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{
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@ -104,7 +94,7 @@ JitManager::JitManager(uint32_t simdWidth, const char* arch, const char* core) :
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}
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else if (mArch.AVX2())
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{
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hostCPUName = StringRef("core-avx2");
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mHostCpuName = StringRef("core-avx2");
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if (mVWidth == 0)
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{
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mVWidth = 8;
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@ -114,11 +104,11 @@ JitManager::JitManager(uint32_t simdWidth, const char* arch, const char* core) :
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{
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if (mArch.F16C())
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{
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hostCPUName = StringRef("core-avx-i");
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mHostCpuName = StringRef("core-avx-i");
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}
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else
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{
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hostCPUName = StringRef("corei7-avx");
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mHostCpuName = StringRef("corei7-avx");
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}
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if (mVWidth == 0)
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{
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@ -131,31 +121,21 @@ JitManager::JitManager(uint32_t simdWidth, const char* arch, const char* core) :
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}
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auto optLevel = CodeGenOpt::Aggressive;
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mOptLevel = CodeGenOpt::Aggressive;
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if (KNOB_JIT_OPTIMIZATION_LEVEL >= CodeGenOpt::None &&
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KNOB_JIT_OPTIMIZATION_LEVEL <= CodeGenOpt::Aggressive)
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{
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optLevel = CodeGenOpt::Level(KNOB_JIT_OPTIMIZATION_LEVEL);
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mOptLevel = CodeGenOpt::Level(KNOB_JIT_OPTIMIZATION_LEVEL);
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}
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mpCurrentModule->setTargetTriple(sys::getProcessTriple());
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mpExec = EngineBuilder(std::move(newModule))
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.setTargetOptions(tOpts)
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.setOptLevel(optLevel)
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.setMCPU(hostCPUName)
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.create();
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if (KNOB_JIT_ENABLE_CACHE)
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{
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mCache.Init(this, hostCPUName, optLevel);
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mpExec->setObjectCache(&mCache);
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mCache.Init(this, mHostCpuName, mOptLevel);
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}
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#if LLVM_USE_INTEL_JITEVENTS
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JITEventListener* vTune = JITEventListener::createIntelJITEventListener();
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mpExec->RegisterJITEventListener(vTune);
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#endif
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SetupNewModule();
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mIsModuleFinalized = true;
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// fetch function signature
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#if USE_SIMD16_SHADERS
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@ -198,6 +178,35 @@ JitManager::JitManager(uint32_t simdWidth, const char* arch, const char* core) :
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#endif
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}
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void JitManager::CreateExecEngine(std::unique_ptr<Module> pModule)
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{
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TargetOptions tOpts;
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tOpts.AllowFPOpFusion = FPOpFusion::Fast;
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tOpts.NoInfsFPMath = false;
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tOpts.NoNaNsFPMath = false;
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tOpts.UnsafeFPMath = false;
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// tOpts.PrintMachineCode = true;
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mpExec = EngineBuilder(std::move(pModule))
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.setTargetOptions(tOpts)
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.setOptLevel(mOptLevel)
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.setMCPU(mHostCpuName)
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.create();
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if (KNOB_JIT_ENABLE_CACHE)
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{
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mpExec->setObjectCache(&mCache);
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}
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#if LLVM_USE_INTEL_JITEVENTS
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JITEventListener* vTune = JITEventListener::createIntelJITEventListener();
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mpExec->RegisterJITEventListener(vTune);
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#endif
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mvExecEngines.push_back(mpExec);
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}
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//////////////////////////////////////////////////////////////////////////
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/// @brief Create new LLVM module.
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void JitManager::SetupNewModule()
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@ -207,7 +216,7 @@ void JitManager::SetupNewModule()
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std::unique_ptr<Module> newModule(new Module("", mContext));
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mpCurrentModule = newModule.get();
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mpCurrentModule->setTargetTriple(sys::getProcessTriple());
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mpExec->addModule(std::move(newModule));
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CreateExecEngine(std::move(newModule));
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mIsModuleFinalized = false;
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}
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@ -124,12 +124,21 @@ private:
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struct JitManager
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{
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JitManager(uint32_t w, const char* arch, const char* core);
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~JitManager(){};
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~JitManager()
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{
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for (auto* pExec : mvExecEngines)
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{
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delete pExec;
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}
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}
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JitLLVMContext mContext; ///< LLVM compiler
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llvm::IRBuilder<> mBuilder; ///< LLVM IR Builder
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llvm::ExecutionEngine* mpExec;
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JitCache mCache;
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JitLLVMContext mContext; ///< LLVM compiler
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llvm::IRBuilder<> mBuilder; ///< LLVM IR Builder
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llvm::ExecutionEngine* mpExec;
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std::vector<llvm::ExecutionEngine*> mvExecEngines;
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JitCache mCache;
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llvm::StringRef mHostCpuName;
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llvm::CodeGenOpt::Level mOptLevel;
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// Need to be rebuilt after a JIT and before building new IR
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llvm::Module* mpCurrentModule;
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@ -148,11 +157,14 @@ struct JitManager
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// Debugging support
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std::unordered_map<llvm::StructType*, llvm::DIType*> mDebugStructMap;
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void CreateExecEngine(std::unique_ptr<llvm::Module> M);
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void SetupNewModule();
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void DumpAsm(llvm::Function* pFunction, const char* fileName);
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static void DumpToFile(llvm::Function* f, const char* fileName);
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static void DumpToFile(llvm::Module* M, const char* fileName, llvm::AssemblyAnnotationWriter* annotater = nullptr);
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static void DumpToFile(llvm::Module* M,
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const char* fileName,
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llvm::AssemblyAnnotationWriter* annotater = nullptr);
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static std::string GetOutputDir();
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// Debugging support methods
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@ -183,8 +195,10 @@ struct JitManager
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class InterleaveAssemblyAnnotater : public llvm::AssemblyAnnotationWriter
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{
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public:
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void emitInstructionAnnot(const llvm::Instruction *pInst, llvm::formatted_raw_ostream &OS) override;
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void emitInstructionAnnot(const llvm::Instruction* pInst,
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llvm::formatted_raw_ostream& OS) override;
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std::vector<std::string> mAssembly;
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private:
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uint32_t mCurrentLineNo = 0;
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};
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