radeonsi: Go back to using llvm.pow intrinsic for nir_op_fpow
ARB_vertex_program and ARB_fragment_program define 0^0 = 1 (while GLSL leaves it undefined). Performing fpow lowering in NIR would break this behavior, preventing us from using prog_to_nir. According to llvm/lib/Target/AMDGPU/SIInstructions.td, POW_common expands to <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>, which presumably does a zero-wins multiply. Lowering in NIR results in a non-legacy multiply, where: pow(0, 0) = 2^(log2(0) * 0) = 2^(-INF * 0) = 2^(-NaN) = -NaN which isn't the desired result. This reverts: - commitd6b7539206
(ac/nir: remove emission of nir_op_fpow) - commit22430224fe
(radeonsi/nir: enable lowering of fpow) and prevents a regression in gl-1.0-spot-light with AMD_DEBUG=nir after enabling prog_to_nir in st/mesa later in this series. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
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@ -801,6 +801,10 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
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result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.frexp.mant.f64",
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ctx->ac.f64, src, 1, AC_FUNC_ATTR_READNONE);
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break;
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case nir_op_fpow:
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result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
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ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
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break;
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case nir_op_fmax:
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result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
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ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
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@ -486,7 +486,6 @@ static const struct nir_shader_compiler_options nir_options = {
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.lower_scmp = true,
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.lower_flrp32 = true,
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.lower_flrp64 = true,
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.lower_fpow = true,
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.lower_fsat = true,
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.lower_fdiv = true,
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.lower_sub = true,
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