gallium/radeon: define RADEON_SURF_MODE_* as enums
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -37,8 +37,9 @@
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static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
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struct r600_texture *rtex);
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static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
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const struct pipe_resource *templ);
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static enum radeon_surf_mode
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r600_choose_tiling(struct r600_common_screen *rscreen,
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const struct pipe_resource *templ);
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bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
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@ -191,7 +192,7 @@ static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned leve
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static int r600_init_surface(struct r600_common_screen *rscreen,
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struct radeon_surf *surface,
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const struct pipe_resource *ptex,
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unsigned array_mode,
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enum radeon_surf_mode array_mode,
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unsigned pitch_in_bytes_override,
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unsigned offset,
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bool is_imported,
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@ -1200,8 +1201,9 @@ r600_texture_create_object(struct pipe_screen *screen,
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return rtex;
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}
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static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
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const struct pipe_resource *templ)
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static enum radeon_surf_mode
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r600_choose_tiling(struct r600_common_screen *rscreen,
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const struct pipe_resource *templ)
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{
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const struct util_format_description *desc = util_format_description(templ->format);
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bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
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@ -257,6 +257,12 @@ enum radeon_feature_id {
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#define RADEON_SURF_MAX_LEVEL 32
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enum radeon_surf_mode {
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RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
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RADEON_SURF_MODE_1D = 2,
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RADEON_SURF_MODE_2D = 3,
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};
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#define RADEON_SURF_TYPE_MASK 0xFF
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#define RADEON_SURF_TYPE_SHIFT 0
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#define RADEON_SURF_TYPE_1D 0
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@ -267,9 +273,6 @@ enum radeon_feature_id {
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#define RADEON_SURF_TYPE_2D_ARRAY 5
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#define RADEON_SURF_MODE_MASK 0xFF
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#define RADEON_SURF_MODE_SHIFT 8
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#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
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#define RADEON_SURF_MODE_1D 2
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#define RADEON_SURF_MODE_2D 3
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#define RADEON_SURF_SCANOUT (1 << 16)
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#define RADEON_SURF_ZBUFFER (1 << 17)
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#define RADEON_SURF_SBUFFER (1 << 18)
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@ -295,7 +298,7 @@ struct radeon_surf_level {
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uint32_t nblk_y;
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uint32_t nblk_z;
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uint32_t pitch_bytes;
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uint32_t mode;
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enum radeon_surf_mode mode;
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uint64_t dcc_offset;
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uint64_t dcc_fast_clear_size;
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bool dcc_enabled;
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