anv: implement VK_KHR_synchronization2
v2: Use u_foreach_bit64() (Samuel) v3: Add missing handling of VkMemoryBarrier2KHR in pNext of VkSubpassDependency2KHR (Samuel) v4: Remove unused ANV_PIPELINE_STAGE_PIPELINED_BITS (Ivan) v5: fix missing anv_measure_submit() (Jason) constify anv_pipeline_stage_pipelined_bits (Jason) v6: Split flushes & invalidation emissions on vkCmdSetEvent2KHR()/vkCmdWaitEvents2KHR() (Jason) v7: Only apply flushes once on events (Jason) v8: Drop split flushes for this patch v9: Add comment about ignore some fields of VkMemoryBarrier2 in VkSubpassDependency2KHR (Jason) Drop spurious PIPE_CONTROL change s/,/;/ (Jason) v10: Fix build issue on Android (Lionel) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9045>
This commit is contained in:
parent
dff9098059
commit
b996fa8efa
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@ -15,3 +15,4 @@ VK_KHR_shader_float16_int8 on lavapipe
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VK_KHR_shader_subgroup_extended_types on lavapipe
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VK_KHR_spirv_1_4 on lavapipe
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Experimental raytracing support on RADV
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VK_KHR_synchronization2 on Intel
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@ -34,6 +34,7 @@
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#include <sync/sync.h>
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#include "anv_private.h"
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#include "vk_common_entrypoints.h"
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#include "vk_util.h"
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static int anv_hal_open(const struct hw_module_t* mod, const char* id, struct hw_device_t** dev);
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@ -875,7 +876,7 @@ anv_QueueSignalReleaseImageANDROID(
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if (waitSemaphoreCount == 0)
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goto done;
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result = anv_QueueSubmit(queue, 1,
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result = vk_common_QueueSubmit(queue, 1,
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&(VkSubmitInfo) {
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.sType = VK_STRUCTURE_TYPE_SUBMIT_INFO,
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.waitSemaphoreCount = 1,
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@ -230,6 +230,7 @@ get_device_extensions(const struct anv_physical_device *device,
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.KHR_swapchain = true,
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.KHR_swapchain_mutable_format = true,
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#endif
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.KHR_synchronization2 = true,
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.KHR_timeline_semaphore = true,
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.KHR_uniform_buffer_standard_layout = true,
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.KHR_variable_pointers = true,
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@ -1689,6 +1690,13 @@ void anv_GetPhysicalDeviceFeatures2(
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SYNCHRONIZATION_2_FEATURES_KHR: {
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VkPhysicalDeviceSynchronization2FeaturesKHR *features =
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(VkPhysicalDeviceSynchronization2FeaturesKHR *)ext;
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features->synchronization2 = true;
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
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VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
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(VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
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@ -31,22 +31,36 @@ anv_render_pass_add_subpass_dep(struct anv_device *device,
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struct anv_render_pass *pass,
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const VkSubpassDependency2KHR *dep)
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{
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/* From the Vulkan 1.2.195 spec:
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*
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* "If an instance of VkMemoryBarrier2 is included in the pNext chain,
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* srcStageMask, dstStageMask, srcAccessMask, and dstAccessMask
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* parameters are ignored. The synchronization and access scopes instead
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* are defined by the parameters of VkMemoryBarrier2."
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*/
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const VkMemoryBarrier2KHR *barrier =
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vk_find_struct_const(dep->pNext, MEMORY_BARRIER_2_KHR);
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VkAccessFlags2KHR src_access_mask =
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barrier ? barrier->srcAccessMask : dep->srcAccessMask;
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VkAccessFlags2KHR dst_access_mask =
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barrier ? barrier->dstAccessMask : dep->dstAccessMask;
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if (dep->dstSubpass == VK_SUBPASS_EXTERNAL) {
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pass->subpass_flushes[pass->subpass_count] |=
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anv_pipe_invalidate_bits_for_access_flags(device, dep->dstAccessMask);
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anv_pipe_invalidate_bits_for_access_flags(device, dst_access_mask);
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} else {
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assert(dep->dstSubpass < pass->subpass_count);
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pass->subpass_flushes[dep->dstSubpass] |=
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anv_pipe_invalidate_bits_for_access_flags(device, dep->dstAccessMask);
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anv_pipe_invalidate_bits_for_access_flags(device, dst_access_mask);
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}
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if (dep->srcSubpass == VK_SUBPASS_EXTERNAL) {
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pass->subpass_flushes[0] |=
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anv_pipe_flush_bits_for_access_flags(device, dep->srcAccessMask);
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anv_pipe_flush_bits_for_access_flags(device, src_access_mask);
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} else {
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assert(dep->srcSubpass < pass->subpass_count);
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pass->subpass_flushes[dep->srcSubpass + 1] |=
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anv_pipe_flush_bits_for_access_flags(device, dep->srcAccessMask);
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anv_pipe_flush_bits_for_access_flags(device, src_access_mask);
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}
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}
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@ -66,6 +66,7 @@
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#include "vk_alloc.h"
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#include "vk_debug_report.h"
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#include "vk_device.h"
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#include "vk_enum_defines.h"
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#include "vk_image.h"
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#include "vk_instance.h"
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#include "vk_physical_device.h"
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@ -2538,34 +2539,35 @@ enum anv_pipe_bits {
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static inline enum anv_pipe_bits
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anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
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VkAccessFlags flags)
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VkAccessFlags2KHR flags)
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{
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enum anv_pipe_bits pipe_bits = 0;
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u_foreach_bit(b, flags) {
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switch ((VkAccessFlagBits)(1 << b)) {
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case VK_ACCESS_SHADER_WRITE_BIT:
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u_foreach_bit64(b, flags) {
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switch ((VkAccessFlags2KHR)(1 << b)) {
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case VK_ACCESS_2_SHADER_WRITE_BIT_KHR:
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case VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR:
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/* We're transitioning a buffer that was previously used as write
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* destination through the data port. To make its content available
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* to future operations, flush the hdc pipeline.
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*/
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pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
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break;
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case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
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case VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR:
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/* We're transitioning a buffer that was previously used as render
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* target. To make its content available to future operations, flush
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* the render target cache.
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*/
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pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
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break;
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case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
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case VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR:
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/* We're transitioning a buffer that was previously used as depth
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* buffer. To make its content available to future operations, flush
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* the depth cache.
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*/
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pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
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break;
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case VK_ACCESS_TRANSFER_WRITE_BIT:
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case VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR:
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/* We're transitioning a buffer that was previously used as a
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* transfer write destination. Generic write operations include color
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* & depth operations as well as buffer operations like :
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pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
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pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
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break;
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case VK_ACCESS_MEMORY_WRITE_BIT:
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case VK_ACCESS_2_MEMORY_WRITE_BIT_KHR:
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/* We're transitioning a buffer for generic write operations. Flush
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* all the caches.
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*/
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pipe_bits |= ANV_PIPE_FLUSH_BITS;
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break;
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case VK_ACCESS_HOST_WRITE_BIT:
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case VK_ACCESS_2_HOST_WRITE_BIT_KHR:
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/* We're transitioning a buffer for access by CPU. Invalidate
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* all the caches. Since data and tile caches don't have invalidate,
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* we are forced to flush those as well.
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pipe_bits |= ANV_PIPE_FLUSH_BITS;
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pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
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break;
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case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
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case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
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case VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
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case VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
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/* We're transitioning a buffer written either from VS stage or from
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* the command streamer (see CmdEndTransformFeedbackEXT), we just
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* need to stall the CS.
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@ -2614,13 +2616,13 @@ anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
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static inline enum anv_pipe_bits
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anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
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VkAccessFlags flags)
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VkAccessFlags2KHR flags)
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{
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enum anv_pipe_bits pipe_bits = 0;
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u_foreach_bit(b, flags) {
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switch ((VkAccessFlagBits)(1 << b)) {
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case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
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u_foreach_bit64(b, flags) {
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switch ((VkAccessFlags2KHR)(1 << b)) {
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case VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR:
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/* Indirect draw commands take a buffer as input that we're going to
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* read from the command streamer to load some of the HW registers
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* (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
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*/
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pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
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break;
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case VK_ACCESS_INDEX_READ_BIT:
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case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
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case VK_ACCESS_2_INDEX_READ_BIT_KHR:
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case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR:
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/* We transitioning a buffer to be used for as input for vkCmdDraw*
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* commands, so we invalidate the VF cache to make sure there is no
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* stale data when we start rendering.
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*/
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pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
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break;
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case VK_ACCESS_UNIFORM_READ_BIT:
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case VK_ACCESS_2_UNIFORM_READ_BIT_KHR:
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/* We transitioning a buffer to be used as uniform data. Because
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* uniform is accessed through the data port & sampler, we need to
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* invalidate the texture cache (sampler) & constant cache (data
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@ -2662,28 +2664,28 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
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else
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pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
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break;
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case VK_ACCESS_SHADER_READ_BIT:
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case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
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case VK_ACCESS_TRANSFER_READ_BIT:
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case VK_ACCESS_2_SHADER_READ_BIT_KHR:
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case VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR:
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case VK_ACCESS_2_TRANSFER_READ_BIT_KHR:
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/* Transitioning a buffer to be read through the sampler, so
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* invalidate the texture cache, we don't want any stale data.
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*/
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pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
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break;
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case VK_ACCESS_MEMORY_READ_BIT:
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case VK_ACCESS_2_MEMORY_READ_BIT_KHR:
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/* Transitioning a buffer for generic read, invalidate all the
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* caches.
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*/
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pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
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break;
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case VK_ACCESS_MEMORY_WRITE_BIT:
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case VK_ACCESS_2_MEMORY_WRITE_BIT_KHR:
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/* Generic write, make sure all previously written things land in
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* memory.
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*/
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pipe_bits |= ANV_PIPE_FLUSH_BITS;
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break;
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case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
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case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT:
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case VK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT:
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case VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT:
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/* Transitioning a buffer for conditional rendering or transform
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* feedback. We'll load the content of this buffer into HW registers
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* using the command streamer, so we need to stall the command
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@ -2694,7 +2696,7 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
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pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
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pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
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break;
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case VK_ACCESS_HOST_READ_BIT:
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case VK_ACCESS_2_HOST_READ_BIT_KHR:
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/* We're transitioning a buffer that was written by CPU. Flush
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* all the caches.
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*/
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@ -1206,10 +1206,10 @@ anv_queue_submit_post_and_alloc_new(struct anv_queue *queue,
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return VK_SUCCESS;
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}
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VkResult anv_QueueSubmit(
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VkResult anv_QueueSubmit2KHR(
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VkQueue _queue,
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uint32_t submitCount,
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const VkSubmitInfo* pSubmits,
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const VkSubmitInfo2KHR* pSubmits,
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VkFence _fence)
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{
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ANV_FROM_HANDLE(anv_queue, queue, _queue);
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@ -1242,23 +1242,14 @@ VkResult anv_QueueSubmit(
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mem_signal_info && mem_signal_info->memory != VK_NULL_HANDLE ?
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anv_device_memory_from_handle(mem_signal_info->memory)->bo : NULL;
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const VkTimelineSemaphoreSubmitInfoKHR *timeline_info =
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vk_find_struct_const(pSubmits[i].pNext,
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TIMELINE_SEMAPHORE_SUBMIT_INFO_KHR);
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const VkPerformanceQuerySubmitInfoKHR *perf_info =
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vk_find_struct_const(pSubmits[i].pNext,
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PERFORMANCE_QUERY_SUBMIT_INFO_KHR);
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const int perf_pass = perf_info ? perf_info->counterPassIndex : 0;
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const uint64_t *wait_values =
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timeline_info && timeline_info->waitSemaphoreValueCount ?
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timeline_info->pWaitSemaphoreValues : NULL;
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const uint64_t *signal_values =
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timeline_info && timeline_info->signalSemaphoreValueCount ?
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timeline_info->pSignalSemaphoreValues : NULL;
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if (!anv_queue_submit_can_add_submit(submit,
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pSubmits[i].waitSemaphoreCount,
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pSubmits[i].signalSemaphoreCount,
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pSubmits[i].waitSemaphoreInfoCount,
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pSubmits[i].signalSemaphoreInfoCount,
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perf_pass)) {
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result = anv_queue_submit_post_and_alloc_new(queue, &submit);
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if (result != VK_SUCCESS)
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@ -1266,19 +1257,19 @@ VkResult anv_QueueSubmit(
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}
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/* Wait semaphores */
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for (uint32_t j = 0; j < pSubmits[i].waitSemaphoreCount; j++) {
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for (uint32_t j = 0; j < pSubmits[i].waitSemaphoreInfoCount; j++) {
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result = anv_queue_submit_add_in_semaphore(submit,
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device,
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pSubmits[i].pWaitSemaphores[j],
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wait_values ? wait_values[j] : 0);
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pSubmits[i].pWaitSemaphoreInfos[j].semaphore,
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pSubmits[i].pWaitSemaphoreInfos[j].value);
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if (result != VK_SUCCESS)
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goto out;
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}
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/* Command buffers */
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for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
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for (uint32_t j = 0; j < pSubmits[i].commandBufferInfoCount; j++) {
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer,
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pSubmits[i].pCommandBuffers[j]);
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pSubmits[i].pCommandBufferInfos[j].commandBuffer);
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assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
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assert(!anv_batch_has_error(&cmd_buffer->batch));
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anv_measure_submit(cmd_buffer);
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|
@ -1298,11 +1289,11 @@ VkResult anv_QueueSubmit(
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}
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/* Signal semaphores */
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for (uint32_t j = 0; j < pSubmits[i].signalSemaphoreCount; j++) {
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for (uint32_t j = 0; j < pSubmits[i].signalSemaphoreInfoCount; j++) {
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result = anv_queue_submit_add_out_semaphore(submit,
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device,
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pSubmits[i].pSignalSemaphores[j],
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signal_values ? signal_values[j] : 0);
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pSubmits[i].pSignalSemaphoreInfos[j].semaphore,
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pSubmits[i].pSignalSemaphoreInfos[j].value);
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if (result != VK_SUCCESS)
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goto out;
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}
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|
@ -1350,7 +1341,7 @@ out:
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* anv_device_set_lost() would have been called already by a callee of
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* anv_queue_submit().
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*/
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result = anv_device_set_lost(device, "vkQueueSubmit() failed");
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result = anv_device_set_lost(device, "vkQueueSubmit2KHR() failed");
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}
|
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|
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return result;
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|
|
|
@ -2403,43 +2403,37 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.pending_pipe_bits = bits;
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}
|
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|
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void genX(CmdPipelineBarrier)(
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VkCommandBuffer commandBuffer,
|
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VkPipelineStageFlags srcStageMask,
|
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VkPipelineStageFlags destStageMask,
|
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VkBool32 byRegion,
|
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uint32_t memoryBarrierCount,
|
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const VkMemoryBarrier* pMemoryBarriers,
|
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uint32_t bufferMemoryBarrierCount,
|
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const VkBufferMemoryBarrier* pBufferMemoryBarriers,
|
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uint32_t imageMemoryBarrierCount,
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const VkImageMemoryBarrier* pImageMemoryBarriers)
|
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static void
|
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cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
|
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const VkDependencyInfoKHR *dep_info,
|
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const char *reason)
|
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{
|
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
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|
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/* XXX: Right now, we're really dumb and just flush whatever categories
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* the app asks for. One of these days we may make this a bit better
|
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* but right now that's all the hardware allows for in most areas.
|
||||
*/
|
||||
VkAccessFlags src_flags = 0;
|
||||
VkAccessFlags dst_flags = 0;
|
||||
VkAccessFlags2KHR src_flags = 0;
|
||||
VkAccessFlags2KHR dst_flags = 0;
|
||||
|
||||
for (uint32_t i = 0; i < memoryBarrierCount; i++) {
|
||||
src_flags |= pMemoryBarriers[i].srcAccessMask;
|
||||
dst_flags |= pMemoryBarriers[i].dstAccessMask;
|
||||
for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
|
||||
src_flags |= dep_info->pMemoryBarriers[i].srcAccessMask;
|
||||
dst_flags |= dep_info->pMemoryBarriers[i].dstAccessMask;
|
||||
}
|
||||
|
||||
for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
|
||||
src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
|
||||
dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
|
||||
for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
|
||||
src_flags |= dep_info->pBufferMemoryBarriers[i].srcAccessMask;
|
||||
dst_flags |= dep_info->pBufferMemoryBarriers[i].dstAccessMask;
|
||||
}
|
||||
|
||||
for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
|
||||
src_flags |= pImageMemoryBarriers[i].srcAccessMask;
|
||||
dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
|
||||
ANV_FROM_HANDLE(anv_image, image, pImageMemoryBarriers[i].image);
|
||||
const VkImageSubresourceRange *range =
|
||||
&pImageMemoryBarriers[i].subresourceRange;
|
||||
for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
|
||||
const VkImageMemoryBarrier2KHR *img_barrier =
|
||||
&dep_info->pImageMemoryBarriers[i];
|
||||
|
||||
src_flags |= img_barrier->srcAccessMask;
|
||||
dst_flags |= img_barrier->dstAccessMask;
|
||||
|
||||
ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
|
||||
const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
|
||||
|
||||
uint32_t base_layer, layer_count;
|
||||
if (image->vk.image_type == VK_IMAGE_TYPE_3D) {
|
||||
|
@ -2455,8 +2449,8 @@ void genX(CmdPipelineBarrier)(
|
|||
if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
|
||||
transition_depth_buffer(cmd_buffer, image,
|
||||
base_layer, layer_count,
|
||||
pImageMemoryBarriers[i].oldLayout,
|
||||
pImageMemoryBarriers[i].newLayout,
|
||||
img_barrier->oldLayout,
|
||||
img_barrier->newLayout,
|
||||
false /* will_full_fast_clear */);
|
||||
}
|
||||
|
||||
|
@ -2464,8 +2458,8 @@ void genX(CmdPipelineBarrier)(
|
|||
transition_stencil_buffer(cmd_buffer, image,
|
||||
range->baseMipLevel, level_count,
|
||||
base_layer, layer_count,
|
||||
pImageMemoryBarriers[i].oldLayout,
|
||||
pImageMemoryBarriers[i].newLayout,
|
||||
img_barrier->oldLayout,
|
||||
img_barrier->newLayout,
|
||||
false /* will_full_fast_clear */);
|
||||
}
|
||||
|
||||
|
@ -2476,19 +2470,29 @@ void genX(CmdPipelineBarrier)(
|
|||
transition_color_buffer(cmd_buffer, image, 1UL << aspect_bit,
|
||||
range->baseMipLevel, level_count,
|
||||
base_layer, layer_count,
|
||||
pImageMemoryBarriers[i].oldLayout,
|
||||
pImageMemoryBarriers[i].newLayout,
|
||||
pImageMemoryBarriers[i].srcQueueFamilyIndex,
|
||||
pImageMemoryBarriers[i].dstQueueFamilyIndex,
|
||||
img_barrier->oldLayout,
|
||||
img_barrier->newLayout,
|
||||
img_barrier->srcQueueFamilyIndex,
|
||||
img_barrier->dstQueueFamilyIndex,
|
||||
false /* will_full_fast_clear */);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
anv_add_pending_pipe_bits(cmd_buffer,
|
||||
anv_pipe_flush_bits_for_access_flags(cmd_buffer->device, src_flags) |
|
||||
anv_pipe_invalidate_bits_for_access_flags(cmd_buffer->device, dst_flags),
|
||||
"pipe barrier");
|
||||
enum anv_pipe_bits bits =
|
||||
anv_pipe_flush_bits_for_access_flags(cmd_buffer->device, src_flags) |
|
||||
anv_pipe_invalidate_bits_for_access_flags(cmd_buffer->device, dst_flags);
|
||||
|
||||
anv_add_pending_pipe_bits(cmd_buffer, bits, reason);
|
||||
}
|
||||
|
||||
void genX(CmdPipelineBarrier2KHR)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
const VkDependencyInfoKHR* pDependencyInfo)
|
||||
{
|
||||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
|
||||
cmd_buffer_barrier(cmd_buffer, pDependencyInfo, "pipe barrier");
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -6866,24 +6870,33 @@ void genX(CmdEndConditionalRenderingEXT)(
|
|||
* by the command streamer for later execution.
|
||||
*/
|
||||
#define ANV_PIPELINE_STAGE_PIPELINED_BITS \
|
||||
~(VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT | \
|
||||
VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT | \
|
||||
VK_PIPELINE_STAGE_HOST_BIT | \
|
||||
VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT)
|
||||
~(VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR | \
|
||||
VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR | \
|
||||
VK_PIPELINE_STAGE_2_HOST_BIT_KHR | \
|
||||
VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT)
|
||||
|
||||
void genX(CmdSetEvent)(
|
||||
void genX(CmdSetEvent2KHR)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
VkEvent _event,
|
||||
VkPipelineStageFlags stageMask)
|
||||
const VkDependencyInfoKHR* pDependencyInfo)
|
||||
{
|
||||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
ANV_FROM_HANDLE(anv_event, event, _event);
|
||||
|
||||
VkPipelineStageFlags2KHR src_stages = 0;
|
||||
|
||||
for (uint32_t i = 0; i < pDependencyInfo->memoryBarrierCount; i++)
|
||||
src_stages |= pDependencyInfo->pMemoryBarriers[i].srcStageMask;
|
||||
for (uint32_t i = 0; i < pDependencyInfo->bufferMemoryBarrierCount; i++)
|
||||
src_stages |= pDependencyInfo->pBufferMemoryBarriers[i].srcStageMask;
|
||||
for (uint32_t i = 0; i < pDependencyInfo->imageMemoryBarrierCount; i++)
|
||||
src_stages |= pDependencyInfo->pImageMemoryBarriers[i].srcStageMask;
|
||||
|
||||
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
|
||||
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
|
||||
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||||
if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
|
||||
if (src_stages & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
|
||||
pc.StallAtPixelScoreboard = true;
|
||||
pc.CommandStreamerStallEnable = true;
|
||||
}
|
||||
|
@ -6899,10 +6912,10 @@ void genX(CmdSetEvent)(
|
|||
}
|
||||
}
|
||||
|
||||
void genX(CmdResetEvent)(
|
||||
void genX(CmdResetEvent2KHR)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
VkEvent _event,
|
||||
VkPipelineStageFlags stageMask)
|
||||
VkPipelineStageFlags2KHR stageMask)
|
||||
{
|
||||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
ANV_FROM_HANDLE(anv_event, event, _event);
|
||||
|
@ -6927,22 +6940,15 @@ void genX(CmdResetEvent)(
|
|||
}
|
||||
}
|
||||
|
||||
void genX(CmdWaitEvents)(
|
||||
void genX(CmdWaitEvents2KHR)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
uint32_t eventCount,
|
||||
const VkEvent* pEvents,
|
||||
VkPipelineStageFlags srcStageMask,
|
||||
VkPipelineStageFlags destStageMask,
|
||||
uint32_t memoryBarrierCount,
|
||||
const VkMemoryBarrier* pMemoryBarriers,
|
||||
uint32_t bufferMemoryBarrierCount,
|
||||
const VkBufferMemoryBarrier* pBufferMemoryBarriers,
|
||||
uint32_t imageMemoryBarrierCount,
|
||||
const VkImageMemoryBarrier* pImageMemoryBarriers)
|
||||
const VkDependencyInfoKHR* pDependencyInfos)
|
||||
{
|
||||
#if GFX_VER >= 8
|
||||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
|
||||
#if GFX_VER >= 8
|
||||
for (uint32_t i = 0; i < eventCount; i++) {
|
||||
ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
|
||||
|
||||
|
@ -6960,11 +6966,7 @@ void genX(CmdWaitEvents)(
|
|||
anv_finishme("Implement events on gfx7");
|
||||
#endif
|
||||
|
||||
genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
|
||||
false, /* byRegion */
|
||||
memoryBarrierCount, pMemoryBarriers,
|
||||
bufferMemoryBarrierCount, pBufferMemoryBarriers,
|
||||
imageMemoryBarrierCount, pImageMemoryBarriers);
|
||||
cmd_buffer_barrier(cmd_buffer, pDependencyInfos, "wait event");
|
||||
}
|
||||
|
||||
VkResult genX(CmdSetPerformanceOverrideINTEL)(
|
||||
|
|
|
@ -1226,9 +1226,9 @@ void genX(CmdEndQueryIndexedEXT)(
|
|||
|
||||
#define TIMESTAMP 0x2358
|
||||
|
||||
void genX(CmdWriteTimestamp)(
|
||||
void genX(CmdWriteTimestamp2KHR)(
|
||||
VkCommandBuffer commandBuffer,
|
||||
VkPipelineStageFlagBits pipelineStage,
|
||||
VkPipelineStageFlags2KHR stage,
|
||||
VkQueryPool queryPool,
|
||||
uint32_t query)
|
||||
{
|
||||
|
@ -1241,13 +1241,10 @@ void genX(CmdWriteTimestamp)(
|
|||
struct mi_builder b;
|
||||
mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch);
|
||||
|
||||
switch (pipelineStage) {
|
||||
case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
|
||||
if (stage == VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR) {
|
||||
mi_store(&b, mi_mem64(anv_address_add(query_addr, 8)),
|
||||
mi_reg64(TIMESTAMP));
|
||||
break;
|
||||
|
||||
default:
|
||||
} else {
|
||||
/* Everything else is bottom-of-pipe */
|
||||
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
|
||||
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
|
||||
|
@ -1260,7 +1257,6 @@ void genX(CmdWriteTimestamp)(
|
|||
if (GFX_VER == 9 && cmd_buffer->device->info.gt == 4)
|
||||
pc.CommandStreamerStallEnable = true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
emit_query_pc_availability(cmd_buffer, query_addr, true);
|
||||
|
|
Loading…
Reference in New Issue