nir: Add tests for nir_extract_bits
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@ -268,6 +268,18 @@ idep_nir = declare_dependency(
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nir_algebraic_py = files('nir_algebraic.py')
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if with_tests
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test(
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'nir_builder',
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executable(
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'nir_builder_test',
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files('tests/builder_tests.cpp'),
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cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
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include_directories : [inc_common],
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dependencies : [dep_thread, idep_gtest, idep_nir, idep_mesautil],
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),
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suite : ['compiler', 'nir'],
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)
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test(
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'nir_control_flow',
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executable(
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@ -0,0 +1,155 @@
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/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <gtest/gtest.h>
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#include "nir.h"
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#include "nir_builder.h"
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namespace {
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class nir_builder_test : public ::testing::Test {
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private:
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const glsl_type *type_for_def(nir_ssa_def *def)
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{
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switch (def->bit_size) {
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case 8: return glsl_type::u8vec(def->num_components);
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case 16: return glsl_type::u16vec(def->num_components);
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case 32: return glsl_type::uvec(def->num_components);
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case 64: return glsl_type::u64vec(def->num_components);
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default: unreachable("Invalid bit size");
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}
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}
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protected:
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nir_builder_test();
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~nir_builder_test();
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void store_test_val(nir_ssa_def *val)
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{
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nir_variable *var = nir_variable_create(b->shader, nir_var_mem_ssbo,
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type_for_def(val), NULL);
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nir_intrinsic_instr *store =
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nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_deref);
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store->num_components = val->num_components;
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store->src[0] = nir_src_for_ssa(&nir_build_deref_var(b, var)->dest.ssa);
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store->src[1] = nir_src_for_ssa(val);
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nir_intrinsic_set_write_mask(store, ((1 << val->num_components) - 1));
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nir_builder_instr_insert(b, &store->instr);
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stores.push_back(store);
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}
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nir_ssa_def *test_val(unsigned idx)
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{
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return stores[idx]->src[1].ssa;
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}
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std::vector<nir_intrinsic_instr *> stores;
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void *mem_ctx;
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void *lin_ctx;
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nir_builder *b;
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};
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nir_builder_test::nir_builder_test()
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{
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glsl_type_singleton_init_or_ref();
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mem_ctx = ralloc_context(NULL);
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lin_ctx = linear_alloc_parent(mem_ctx, 0);
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static const nir_shader_compiler_options options = { };
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b = rzalloc(mem_ctx, nir_builder);
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nir_builder_init_simple_shader(b, mem_ctx, MESA_SHADER_COMPUTE, &options);
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}
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nir_builder_test::~nir_builder_test()
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{
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if (HasFailure()) {
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printf("\nShader from the failed test:\n\n");
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nir_print_shader(b->shader, stdout);
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}
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ralloc_free(mem_ctx);
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glsl_type_singleton_decref();
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}
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/* Allow grouping the tests while still sharing the helpers. */
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class nir_extract_bits_test : public nir_builder_test {};
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} // namespace
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// TODO: Re-enable this once we get vec8 support in NIR
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TEST_F(nir_extract_bits_test, DISABLED_unaligned8)
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{
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nir_ssa_def *srcs[] = {
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nir_imm_int(b, 0x03020100),
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nir_imm_ivec2(b, 0x07060504, 0x0b0a0908),
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};
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store_test_val(nir_extract_bits(b, srcs, 2, 24, 1, 64));
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NIR_PASS_V(b->shader, nir_opt_constant_folding);
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nir_src val = nir_src_for_ssa(test_val(0));
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ASSERT_EQ(nir_src_as_uint(val), 0x0a09080706050403);
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}
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TEST_F(nir_extract_bits_test, unaligned16_disabled)
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{
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nir_ssa_def *srcs[] = {
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nir_imm_int(b, 0x03020100),
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nir_imm_ivec2(b, 0x07060504, 0x0b0a0908),
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};
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store_test_val(nir_extract_bits(b, srcs, 2, 16, 1, 64));
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NIR_PASS_V(b->shader, nir_opt_constant_folding);
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nir_src val = nir_src_for_ssa(test_val(0));
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ASSERT_EQ(nir_src_as_uint(val), 0x0908070605040302);
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}
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TEST_F(nir_extract_bits_test, mixed_bit_sizes)
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{
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nir_ssa_def *srcs[] = {
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nir_imm_int(b, 0x03020100),
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nir_imm_intN_t(b, 0x04, 8),
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nir_imm_intN_t(b, 0x08070605, 32),
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nir_vec2(b, nir_imm_intN_t(b, 0x0a09, 16),
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nir_imm_intN_t(b, 0x0c0b, 16)),
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};
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store_test_val(nir_extract_bits(b, srcs, 4, 24, 2, 32));
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NIR_PASS_V(b->shader, nir_opt_constant_folding);
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nir_src val = nir_src_for_ssa(test_val(0));
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ASSERT_EQ(nir_src_comp_as_uint(val, 0), 0x06050403);
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ASSERT_EQ(nir_src_comp_as_uint(val, 1), 0x0a090807);
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}
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