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i965: Fix Crystal Well PCI IDs. 

The second digit was off by one, which meant we accidentally treated
GTn as GT(n-1).  This also meant no support for GT1 at all.

NOTE: This is a candidate for stable branches.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Kenneth Graunke 2013-03-01 15:23:53 -08:00
parent 83e7d111af
commit b88f74d63d
2 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
include/pci_ids/i965_pci_ids.h
View File

@ -53,12 +53,12 @@ CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1)
CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2)
CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1)
CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2)
CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1)
CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2)
CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1)
CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2)
CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1)
CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2)
CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1)
CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2)
CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1)
CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2)
CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)

18
src/mesa/drivers/dri/intel/intel_chipset.h
View File

@ -114,15 +114,15 @@
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I915_GM || \