mesa: add gallium flush_flags param into ctx->Driver.Flush
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11341>
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ee6929a779
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@ -355,7 +355,7 @@ _intel_flush(struct gl_context *ctx, const char *file, int line)
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}
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static void
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intel_glFlush(struct gl_context *ctx)
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intel_glFlush(struct gl_context *ctx, unsigned gallium_flush_flags)
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{
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struct intel_context *intel = intel_context(ctx);
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@ -302,7 +302,7 @@ brw_display_shared_buffer(struct brw_context *brw)
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}
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static void
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brw_glFlush(struct gl_context *ctx)
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brw_glFlush(struct gl_context *ctx, unsigned gallium_flush_flags)
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{
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struct brw_context *brw = brw_context(ctx);
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@ -342,7 +342,7 @@ brw_finish(struct gl_context * ctx)
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{
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struct brw_context *brw = brw_context(ctx);
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brw_glFlush(ctx);
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brw_glFlush(ctx, 0);
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if (brw->batch.last_bo)
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brw_bo_wait_rendering(brw->batch.last_bo);
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@ -64,7 +64,7 @@ nouveau_get_string(struct gl_context *ctx, GLenum name)
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}
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static void
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nouveau_flush(struct gl_context *ctx)
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nouveau_flush(struct gl_context *ctx, unsigned gallium_flush_flags)
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{
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struct nouveau_context *nctx = to_nouveau_context(ctx);
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struct nouveau_pushbuf *push = context_push(ctx);
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@ -90,7 +90,7 @@ nouveau_finish(struct gl_context *ctx)
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struct nouveau_pushbuf_refn refn =
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{ nctx->fence, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR };
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nouveau_flush(ctx);
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nouveau_flush(ctx, 0);
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if (!nouveau_pushbuf_space(push, 16, 0, 0) &&
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!nouveau_pushbuf_refn(push, &refn, 1)) {
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@ -534,7 +534,7 @@ unsigned r200_blit(struct gl_context *ctx,
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}
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/* Flush is needed to make sure that source buffer has correct data */
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radeonFlush(&r200->radeon.glCtx);
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radeonFlush(&r200->radeon.glCtx, 0);
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rcommonEnsureCmdBufSpace(&r200->radeon, 102, __func__);
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@ -554,7 +554,7 @@ unsigned r200_blit(struct gl_context *ctx,
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reg_width, reg_height,
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flip_y);
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radeonFlush(ctx);
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radeonFlush(ctx, 0);
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/* We submitted those packets outside our state atom mechanism. Thus
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* make sure the atoms are resubmitted the next time. */
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@ -61,7 +61,7 @@ static void r200Clear( struct gl_context *ctx, GLbitfield mask )
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BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL |
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BUFFER_BIT_COLOR0;
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radeonFlush( ctx );
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radeonFlush( ctx, 0 );
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hwmask = mask & hwbits;
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swmask = mask & ~hwbits;
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@ -386,7 +386,7 @@ unsigned r100_blit(struct gl_context *ctx,
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}
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/* Flush is needed to make sure that source buffer has correct data */
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radeonFlush(ctx);
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radeonFlush(ctx, 0);
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rcommonEnsureCmdBufSpace(&r100->radeon, 59, __func__);
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@ -406,7 +406,7 @@ unsigned r100_blit(struct gl_context *ctx,
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reg_width, reg_height,
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flip_y);
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radeonFlush(ctx);
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radeonFlush(ctx, 0);
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/* We submitted those packets outside our state atom mechanism. Thus
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* make sure they are all resubmitted the next time. */
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@ -185,7 +185,7 @@ radeonMapBufferRange(struct gl_context * ctx,
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(access & (GL_MAP_READ_BIT | GL_MAP_WRITE_BIT)) == GL_MAP_WRITE_BIT;
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if (write_only) {
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ctx->Driver.Flush(ctx);
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ctx->Driver.Flush(ctx, 0);
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}
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if (radeon_obj->bo == NULL) {
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@ -101,7 +101,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
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static inline void radeon_firevertices(radeonContextPtr radeon)
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{
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if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
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radeon->glCtx.Driver.Flush(&radeon->glCtx); /* +r6/r7 */
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radeon->glCtx.Driver.Flush(&radeon->glCtx, 0); /* +r6/r7 */
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}
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#endif
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@ -369,7 +369,7 @@ void radeon_viewport(struct gl_context *ctx)
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if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
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if (_mesa_is_front_buffer_drawing(ctx->DrawBuffer)) {
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ctx->Driver.Flush(ctx);
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ctx->Driver.Flush(ctx, 0);
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}
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radeon_update_renderbuffers(driContext, driContext->driDrawablePriv, GL_FALSE);
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if (driContext->driDrawablePriv != driContext->driReadablePriv)
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@ -523,7 +523,7 @@ void radeonEmitState(radeonContextPtr radeon)
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}
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void radeonFlush(struct gl_context *ctx)
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void radeonFlush(struct gl_context *ctx, unsigned gallium_flush_flags)
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{
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radeonContextPtr radeon = RADEON_CONTEXT(ctx);
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if (RADEON_DEBUG & RADEON_IOCTL)
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@ -572,7 +572,7 @@ void radeonFinish(struct gl_context * ctx)
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int i;
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if (ctx->Driver.Flush)
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ctx->Driver.Flush(ctx); /* +r6/r7 */
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ctx->Driver.Flush(ctx, 0); /* +r6/r7 */
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for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
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struct radeon_renderbuffer *rrb;
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@ -12,7 +12,7 @@ void radeonScissor(struct gl_context *ctx);
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extern uint32_t radeonGetAge(radeonContextPtr radeon);
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void radeonFlush(struct gl_context *ctx);
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void radeonFlush(struct gl_context *ctx, unsigned gallium_flush_flags);
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void radeonFinish(struct gl_context * ctx);
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void radeonEmitState(radeonContextPtr radeon);
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GLuint radeonCountStateEmitSize(radeonContextPtr radeon);
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@ -534,7 +534,7 @@ radeon_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffe
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rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat);
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if (ctx->Driver.Flush)
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ctx->Driver.Flush(ctx); /* +r6/r7 */
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ctx->Driver.Flush(ctx, 0); /* +r6/r7 */
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if (rrb->bo)
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radeon_bo_unref(rrb->bo);
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@ -578,7 +578,7 @@ radeon_image_target_renderbuffer_storage(struct gl_context *ctx,
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rrb = radeon_renderbuffer(rb);
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if (ctx->Driver.Flush)
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ctx->Driver.Flush(ctx); /* +r6/r7 */
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ctx->Driver.Flush(ctx, 0); /* +r6/r7 */
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if (rrb->bo)
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radeon_bo_unref(rrb->bo);
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@ -720,7 +720,7 @@ radeon_framebuffer_renderbuffer(struct gl_context * ctx,
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{
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if (ctx->Driver.Flush)
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ctx->Driver.Flush(ctx); /* +r6/r7 */
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ctx->Driver.Flush(ctx, 0); /* +r6/r7 */
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radeon_print(RADEON_TEXTURE, RADEON_TRACE,
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"%s(%p, fb %p, rb %p) \n",
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@ -829,7 +829,7 @@ radeon_finish_render_texture(struct gl_context *ctx, struct gl_renderbuffer *rb)
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radeon_image->used_as_render_target = GL_FALSE;
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if (ctx->Driver.Flush)
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ctx->Driver.Flush(ctx); /* +r6/r7 */
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ctx->Driver.Flush(ctx, 0); /* +r6/r7 */
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}
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static void
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radeon_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
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@ -76,7 +76,7 @@ extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags );
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extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * );
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extern void radeonFlush( struct gl_context *ctx );
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extern void radeonFlush( struct gl_context *ctx, unsigned gallium_flush_flags );
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extern void radeonFinish( struct gl_context *ctx );
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extern void radeonInitIoctlFuncs( struct gl_context *ctx );
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extern void radeonGetAllParams( r100ContextPtr rmesa );
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@ -91,7 +91,7 @@ static void radeonWaitQuery(struct gl_context *ctx, struct gl_query_object *q)
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/* If the cmdbuf with packets for this query hasn't been flushed yet, do it now */
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if (radeon_bo_is_referenced_by_cs(query->bo, radeon->cmdbuf.cs))
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ctx->Driver.Flush(ctx);
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ctx->Driver.Flush(ctx, 0);
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radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s: query id %d, bo %p, offset %d\n", __func__, q->Id, query->bo, query->curr_offset);
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@ -169,7 +169,7 @@ static void radeonCheckQuery(struct gl_context *ctx, struct gl_query_object *q)
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/* Need to perform a flush, as per ARB_occlusion_query spec */
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if (radeon_bo_is_referenced_by_cs(query->bo, radeon->cmdbuf.cs)) {
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ctx->Driver.Flush(ctx);
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ctx->Driver.Flush(ctx, 0);
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}
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if (radeon_bo_is_busy(query->bo, &domain) == 0) {
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@ -192,7 +192,7 @@ radeonDRI2Flush(__DRIdrawable *drawable)
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radeonContextPtr rmesa;
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rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate;
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radeonFlush(&rmesa->glCtx);
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radeonFlush(&rmesa->glCtx, 0);
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}
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static const struct __DRI2flushExtensionRec radeonFlushExtension = {
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@ -51,7 +51,7 @@
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static void
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finish_or_flush( struct gl_context *ctx )
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finish(struct gl_context *ctx)
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{
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const XMesaContext xmesa = XMESA_CONTEXT(ctx);
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if (xmesa) {
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@ -62,6 +62,13 @@ finish_or_flush( struct gl_context *ctx )
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}
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static void
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flush(struct gl_context *ctx, unsigned gallium_flush_flags)
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{
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finish(ctx);
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}
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/* Implements glColorMask() */
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static void
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color_mask(struct gl_context *ctx,
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@ -837,8 +844,8 @@ xmesa_init_driver_functions( XMesaVisual xmvisual,
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{
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driver->GetString = get_string;
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driver->UpdateState = xmesa_update_state;
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driver->Flush = finish_or_flush;
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driver->Finish = finish_or_flush;
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driver->Flush = flush;
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driver->Finish = finish;
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driver->ColorMask = color_mask;
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driver->Enable = enable;
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driver->Viewport = xmesa_viewport;
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@ -184,7 +184,7 @@ _mesa_notifySwapBuffers(struct gl_context *ctx)
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_mesa_debug(ctx, "SwapBuffers\n");
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FLUSH_VERTICES(ctx, 0, 0);
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if (ctx->Driver.Flush) {
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ctx->Driver.Flush(ctx);
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ctx->Driver.Flush(ctx, 0);
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}
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}
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@ -1634,7 +1634,9 @@ _mesa_make_current( struct gl_context *newCtx,
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curCtx != newCtx &&
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curCtx->Const.ContextReleaseBehavior ==
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GL_CONTEXT_RELEASE_BEHAVIOR_FLUSH) {
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_mesa_flush(curCtx);
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FLUSH_VERTICES(curCtx, 0, 0);
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if (curCtx->Driver.Flush)
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curCtx->Driver.Flush(curCtx, 0);
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}
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/* Call this periodically to detect when the user has begun using
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@ -1791,7 +1793,7 @@ _mesa_flush(struct gl_context *ctx)
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{
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FLUSH_VERTICES(ctx, 0, 0);
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if (ctx->Driver.Flush) {
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ctx->Driver.Flush(ctx);
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ctx->Driver.Flush(ctx, 0);
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}
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}
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@ -125,7 +125,7 @@ struct dd_function_table {
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/**
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* This is called whenever glFlush() is called.
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*/
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void (*Flush)( struct gl_context *ctx );
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void (*Flush)(struct gl_context *ctx, unsigned gallium_flush_flags);
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/**
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* Clear the color/depth/stencil/accum buffer(s).
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@ -641,7 +641,7 @@ _mesa_GetPerfQueryDataINTEL(GLuint queryHandle, GLuint flags,
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if (!obj->Ready) {
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if (flags == GL_PERFQUERY_FLUSH_INTEL) {
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ctx->Driver.Flush(ctx);
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ctx->Driver.Flush(ctx, 0);
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} else if (flags == GL_PERFQUERY_WAIT_INTEL) {
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ctx->Driver.WaitPerfQuery(ctx, obj);
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obj->Ready = true;
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@ -87,7 +87,7 @@ st_finish(struct st_context *st)
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* Called via ctx->Driver.Flush()
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*/
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static void
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st_glFlush(struct gl_context *ctx)
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st_glFlush(struct gl_context *ctx, unsigned gallium_flush_flags)
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{
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struct st_context *st = st_context(ctx);
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@ -96,7 +96,7 @@ st_glFlush(struct gl_context *ctx)
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* synchronization issues. Calling finish() here will just hide
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* problems that need to be fixed elsewhere.
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*/
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st_flush(st, NULL, 0);
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st_flush(st, NULL, gallium_flush_flags);
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st_manager_flush_frontbuffer(st);
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}
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