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intel/disasm: Fix decoding of src0 of SENDS 

There is no instruction field for the register file for src0 because
it's always GRF.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
This commit is contained in:
Jason Ekstrand 2020-01-06 22:14:29 -06:00
parent 8dcff01c8b
commit b788cccfe2
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw_disasm.c
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@ -1446,7 +1446,7 @@ src0(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
return src_sends_da(file,
devinfo,
BRW_REGISTER_TYPE_UD,
brw_inst_send_src0_reg_file(devinfo, inst),
BRW_GENERAL_REGISTER_FILE,
brw_inst_src0_da_reg_nr(devinfo, inst),
brw_inst_src0_da16_subreg_nr(devinfo, inst));
} else {