freedreno: slurp in rnndb
Pull in all of $envytools/rnndb (including display, etc) from envytools commit 6ccdda33ac4d88e19d2a70e1b4edaaab5ec4b026 This changes the directory structure to match the organization in the envytools tree. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>
This commit is contained in:
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7de0842d42
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<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<import file="freedreno_copyright.xml"/>
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<import file="adreno/a2xx.xml"/>
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<import file="adreno/a3xx.xml"/>
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<import file="adreno/a4xx.xml"/>
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<import file="adreno/a5xx.xml"/>
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<import file="adreno/a6xx.xml"/>
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<import file="adreno/a6xx_gmu.xml"/>
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<import file="adreno/ocmem.xml"/>
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<import file="adreno/adreno_control_regs.xml"/>
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<import file="adreno/adreno_pipe_regs.xml"/>
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</database>
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<?xml version="1.0" encoding="UTF-8"?>
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<database xmlns="http://nouveau.freedesktop.org/"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
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<import file="freedreno_copyright.xml"/>
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<domain name="A6XX" width="32">
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<bitset name="A6XX_GMU_GPU_IDLE_STATUS">
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<bitfield name="BUSY_IGN_AHB" pos="23"/>
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<bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/>
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</bitset>
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<bitset name="A6XX_GMU_OOB">
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<bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/>
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<bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/>
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<bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/>
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<bitfield name="DCVS_SET_MASK" pos="23"/>
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<bitfield name="DCVS_CHECK_MASK" pos="31"/>
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<bitfield name="DCVS_CLEAR_MASK" pos="31"/>
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<bitfield name="GPU_SET_MASK" pos="18"/>
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<bitfield name="GPU_CHECK_MASK" pos="26"/>
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<bitfield name="GPU_CLEAR_MASK" pos="26"/>
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<bitfield name="PERFCNTR_SET_MASK" pos="17"/>
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<bitfield name="PERFCNTR_CHECK_MASK" pos="25"/>
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<bitfield name="PERFCNTR_CLEAR_MASK" pos="25"/>
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</bitset>
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<bitset name="A6XX_HFI_IRQ">
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<bitfield name="MSGQ_MASK" pos="0" />
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<bitfield name="DSGQ_MASK" pos="1"/>
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<bitfield name="BLOCKED_MSG_MASK" pos="2"/>
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<bitfield name="CM3_FAULT_MASK" pos="23"/>
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<bitfield name="GMU_ERR_MASK" low="16" high="22"/>
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<bitfield name="OOB_MASK" low="24" high="31"/>
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</bitset>
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<bitset name="A6XX_HFI_H2F">
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<bitfield name="IRQ_MASK_BIT" pos="0" />
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</bitset>
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<reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
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<reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
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<reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
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<reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
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<reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
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<reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
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<reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
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<reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
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<reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
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<reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
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<reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>
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<reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>
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<reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/>
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<reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/>
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<reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>
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<reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/>
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<reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/>
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<reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/>
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<reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/>
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<reg32 offset="0x502d" name="GMU_CM3_CFG"/>
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<reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
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<reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
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<reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
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<reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
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<reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
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<reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
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<reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
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<reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
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<reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
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<reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
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<reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
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<reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
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<reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
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<reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
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<reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
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<reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
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<bitfield name="IFPC_ENABLE" pos="0" type="boolean"/>
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<bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/>
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<bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/>
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<bitfield name="NUM_PASS_SKIPS" low="10" high="13"/>
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<bitfield name="MIN_PASS_LENGTH" low="14" high="31"/>
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</reg32>
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<reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
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<reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
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<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
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<bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/>
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<bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/>
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<bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/>
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<bitfield name="SPTPRAC_GDSC_POWER_ON" pos="3" type="boolean"/>
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<bitfield name="SP_CLOCK_OFF" pos="4" type="boolean"/>
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<bitfield name="GMU_UP_POWER_STATE" pos="5" type="boolean"/>
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<bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
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<bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
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</reg32>
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<reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
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<bitfield name="HW_NAP_ENABLE" pos="0"/>
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<bitfield name="SID" low="4" high="8"/>
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</reg32>
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<reg32 offset="0x50e8" name="GMU_RPMH_CTRL">
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<bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/>
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<bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/>
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<bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/>
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<bitfield name="MX_VOTE_ENABLE" pos="9" type="boolean"/>
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<bitfield name="CX_VOTE_ENABLE" pos="10" type="boolean"/>
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<bitfield name="GFX_VOTE_ENABLE" pos="11" type="boolean"/>
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<bitfield name="DDR_MIN_VOTE_ENABLE" pos="12" type="boolean"/>
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<bitfield name="MX_MIN_VOTE_ENABLE" pos="13" type="boolean"/>
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<bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/>
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<bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/>
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</reg32>
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<reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
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<reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
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<reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
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<reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
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<reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
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<reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
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<reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/>
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<reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/>
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<reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
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<reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
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<reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
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<reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
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<reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
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<reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
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<reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/>
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<reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/>
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<reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/>
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<reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/>
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<reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/>
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<reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/>
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<reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO">
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<bitfield name="MSGQ" pos="0" type="boolean"/>
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<bitfield name="CM3_FAULT" pos="23" type="boolean"/>
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</reg32>
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<reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/>
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<reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/>
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<reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/>
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<reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
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<reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/>
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<reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/>
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<reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/>
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<reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/>
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<reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/>
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<reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
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<reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
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<reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
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<reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
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<reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
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<reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
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<reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
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<reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
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<reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
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<reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
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<reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/>
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<reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/>
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<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
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<reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
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<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
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<reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
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<reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
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<reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
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<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
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<reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/>
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<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
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<reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
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<reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/>
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<reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/>
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<reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS">
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<bitfield name="WDOG_BITE" pos="0" type="boolean"/>
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<bitfield name="RSCC_COMP" pos="1" type="boolean"/>
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<bitfield name="VDROOP" pos="2" type="boolean"/>
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<bitfield name="FENCE_ERR" pos="3" type="boolean"/>
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<bitfield name="DBD_WAKEUP" pos="4" type="boolean"/>
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<bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/>
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</reg32>
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<reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/>
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<reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
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<reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
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<reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
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<reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
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<bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/>
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</reg32>
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<reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
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<reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
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<reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
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<reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
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<reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
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<reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
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<reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
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<reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/>
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<reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/>
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<reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
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<reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
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<reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
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<!-- starts at offset 0x8c00 on most gpus -->
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<reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
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<reg32 offset="0x0008" name="RSCC_PDC_SEQ_START_ADDR"/>
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<reg32 offset="0x0009" name="RSCC_PDC_MATCH_VALUE_LO"/>
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<reg32 offset="0x000a" name="RSCC_PDC_MATCH_VALUE_HI"/>
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<reg32 offset="0x000b" name="RSCC_PDC_SLAVE_ID_DRV0"/>
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<reg32 offset="0x000d" name="RSCC_HIDDEN_TCS_CMD0_ADDR"/>
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<reg32 offset="0x000e" name="RSCC_HIDDEN_TCS_CMD0_DATA"/>
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<reg32 offset="0x0082" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0"/>
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<reg32 offset="0x0083" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0"/>
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<reg32 offset="0x0089" name="RSCC_TIMESTAMP_UNIT1_EN_DRV0"/>
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<reg32 offset="0x008c" name="RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0"/>
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<reg32 offset="0x0100" name="RSCC_OVERRIDE_START_ADDR"/>
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<reg32 offset="0x0101" name="RSCC_SEQ_BUSY_DRV0"/>
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<reg32 offset="0x0180" name="RSCC_SEQ_MEM_0_DRV0"/>
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<reg32 offset="0x0346" name="RSCC_TCS0_DRV0_STATUS"/>
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<reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/>
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<reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/>
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<reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/>
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</domain>
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|
|
||||||
|
</database>
|
|
@ -0,0 +1,131 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
|
||||||
|
<!--
|
||||||
|
This documents the internal register space used by the CP firmware since
|
||||||
|
the afuc instruction set was introduced.
|
||||||
|
-->
|
||||||
|
|
||||||
|
<domain name="A5XX_CONTROL_REG" width="32">
|
||||||
|
<reg64 name="IB1_BASE" offset="0x0b0"/>
|
||||||
|
<reg32 name="IB1_DWORDS" offset="0x0b2"/>
|
||||||
|
<reg64 name="IB2_BASE" offset="0x0b4"/>
|
||||||
|
<reg32 name="IB2_DWORDS" offset="0x0b6"/>
|
||||||
|
|
||||||
|
<doc>
|
||||||
|
To use these, write the address and number of dwords, then read
|
||||||
|
the result from $addr.
|
||||||
|
</doc>
|
||||||
|
<reg64 name="MEM_READ_ADDR" offset="0x0b8"/>
|
||||||
|
<reg32 name="MEM_READ_DWORDS" offset="0x0ba"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="A6XX_CONTROL_REG" width="32">
|
||||||
|
<reg32 name="RB_RPTR" offset="0x001"/>
|
||||||
|
<doc>
|
||||||
|
Instruction to jump to when the CP is preempted to perform a
|
||||||
|
context switch, initialized to entry 15 of the jump table at
|
||||||
|
bootup.
|
||||||
|
</doc>
|
||||||
|
<reg32 name="PREEMPT_INSTR" offset="0x004"/>
|
||||||
|
|
||||||
|
<reg64 name="IB1_BASE" offset="0x010"/>
|
||||||
|
<reg32 name="IB1_DWORDS" offset="0x012"/>
|
||||||
|
<reg64 name="IB2_BASE" offset="0x014"/>
|
||||||
|
<reg32 name="IB2_DWORDS" offset="0x016"/>
|
||||||
|
|
||||||
|
<reg64 name="MEM_READ_ADDR" offset="0x018"/>
|
||||||
|
<reg32 name="MEM_READ_DWORDS" offset="0x01a"/>
|
||||||
|
|
||||||
|
<reg32 name="REG_WRITE_ADDR" offset="0x024"/>
|
||||||
|
<doc>
|
||||||
|
Writing to this triggers a register write and auto-increments
|
||||||
|
REG_WRITE_ADDR.
|
||||||
|
</doc>
|
||||||
|
<reg32 name="REG_WRITE" offset="0x025"/>
|
||||||
|
|
||||||
|
<doc> After setting these, read result from $addr2 </doc>
|
||||||
|
<reg32 name="REG_READ_DWORDS" offset="0x026"/>
|
||||||
|
<reg32 name="REG_READ_ADDR" offset="0x027"/>
|
||||||
|
|
||||||
|
<doc>
|
||||||
|
Write to increase WFI_PEND_CTR, decremented by WFI_PEND_DECR
|
||||||
|
pipe register.
|
||||||
|
</doc>
|
||||||
|
<reg32 name="WFI_PEND_INCR" offset="0x030"/>
|
||||||
|
<reg32 name="QUERY_PEND_INCR" offset="0x031"/>
|
||||||
|
<reg32 name="CACHE_FLUSH_PEND_INCR" offset="0x031"/>
|
||||||
|
|
||||||
|
<reg32 name="WFI_PEND_CTR" offset="0x038"/>
|
||||||
|
<reg32 name="QUERY_PEND_CTR" offset="0x039"/>
|
||||||
|
<reg32 name="CACHE_FLUSH_PEND_CTR" offset="0x03a"/>
|
||||||
|
|
||||||
|
<reg32 name="DRAW_STATE_SEL" offset="0x041"/>
|
||||||
|
<reg32 name="DRAW_STATE_ACTIVE_BITMASK" offset="0x049"/>
|
||||||
|
<reg32 name="DRAW_STATE_SET" offset="0x04a"/>
|
||||||
|
|
||||||
|
<doc> Controls whether RB, IB1, or IB2 is executed </doc>
|
||||||
|
<reg32 name="IB_LEVEL" offset="0x054"/>
|
||||||
|
|
||||||
|
<doc> Controls high 32 bits used by load and store afuc instructions </doc>
|
||||||
|
<reg32 name="LOAD_STORE_HI" offset="0x058"/>
|
||||||
|
|
||||||
|
<doc> Used to initialize the jump table for handling packets at bootup </doc>
|
||||||
|
<reg32 name="PACKET_TABLE_WRITE_ADDR" offset="0x060"/>
|
||||||
|
<reg32 name="PACKET_TABLE_WRITE" offset="0x061"/>
|
||||||
|
|
||||||
|
<reg32 name="PREEMPT_ENABLE" offset="0x071"/>
|
||||||
|
<reg32 name="SECURE_MODE" offset="0x075"/>
|
||||||
|
|
||||||
|
<!--
|
||||||
|
Note: I think that registers above 0x100 are actually just a
|
||||||
|
scratch space which can be used by firmware however it wants,
|
||||||
|
so these might change if the the firmware is updated.
|
||||||
|
-->
|
||||||
|
|
||||||
|
<doc>
|
||||||
|
These are addresses of various preemption records for the
|
||||||
|
current context. When context switching, the CP will save the
|
||||||
|
current state into these buffers, restore the state of the
|
||||||
|
next context from the buffers in the corresponding
|
||||||
|
CP_CONTEXT_SWITCH_PRIV_* registers written by the kernel,
|
||||||
|
then set these internal registers to the contents of
|
||||||
|
those registers. The kernel sets the initial values via
|
||||||
|
CP_SET_PSEUDO_REG on startup, and from then on the firmware
|
||||||
|
keeps track of them.
|
||||||
|
</doc>
|
||||||
|
<reg64 name="SAVE_REGISTER_SMMU_INFO" offset="0x110"/>
|
||||||
|
<reg64 name="SAVE_REGISTER_PRIV_NON_SECURE" offset="0x112"/>
|
||||||
|
<reg64 name="SAVE_REGISTER_PRIV_SECURE" offset="0x114"/>
|
||||||
|
<reg64 name="SAVE_REGISTER_NON_PRIV" offset="0x116"/>
|
||||||
|
<reg64 name="SAVE_REGISTER_COUNTER" offset="0x118"/>
|
||||||
|
|
||||||
|
<doc>
|
||||||
|
Used only during preemption, saved and restored from the "info"
|
||||||
|
field of a6xx_preemption_record. From the downstream kernel:
|
||||||
|
|
||||||
|
"Type of record. Written non-zero (usually) by CP.
|
||||||
|
we must set to zero for all ringbuffers."
|
||||||
|
</doc>
|
||||||
|
|
||||||
|
<reg32 name="PREEMPTION_INFO" offset="0x126"/>
|
||||||
|
|
||||||
|
<doc>
|
||||||
|
Set by SET_MARKER, used to conditionally execute
|
||||||
|
CP_COND_REG_EXEC and draw states.
|
||||||
|
</doc>
|
||||||
|
<reg32 name="MODE_BITMASK" offset="0x12b"/>
|
||||||
|
|
||||||
|
<reg32 name="SCRATCH_REG0" offset="0x170"/>
|
||||||
|
<reg32 name="SCRATCH_REG1" offset="0x171"/>
|
||||||
|
<reg32 name="SCRATCH_REG2" offset="0x172"/>
|
||||||
|
<reg32 name="SCRATCH_REG3" offset="0x173"/>
|
||||||
|
<reg32 name="SCRATCH_REG4" offset="0x174"/>
|
||||||
|
<reg32 name="SCRATCH_REG5" offset="0x175"/>
|
||||||
|
<reg32 name="SCRATCH_REG6" offset="0x176"/>
|
||||||
|
<reg32 name="SCRATCH_REG7" offset="0x177"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,77 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
|
||||||
|
<!--
|
||||||
|
Pipe registers are a special kind of registers used by SQE on a6xxx, and
|
||||||
|
on a5xx by the ME, to control the CP. They only exist inside the CP, can
|
||||||
|
only be written to, and use the high 8 bits of the $addr register. For
|
||||||
|
example, this is how CP_WAIT_MEM_WRITES is implemented on a6xx:
|
||||||
|
|
||||||
|
CP_WAIT_MEM_WRITES:
|
||||||
|
053b: 8b1d0084 mov $addr, 0x0084 << 24
|
||||||
|
053c: d8000000 waitin
|
||||||
|
053d: 981f0806 mov $01, $data
|
||||||
|
|
||||||
|
and on a5xx ME:
|
||||||
|
|
||||||
|
CP_WAIT_MEM_WRITES:
|
||||||
|
05c3: 8b1d00c4 mov $addr, 0x00c4 << 24
|
||||||
|
05c4: d8000000 waitin
|
||||||
|
05c5: 981f0806 mov $01, $data
|
||||||
|
|
||||||
|
This writes to pipe register 0x84, or 0xc4 on a5xx. In this case the
|
||||||
|
value written is ignored, but for other registers it isn't.
|
||||||
|
|
||||||
|
Note that on a6xx, pipe register writes are pipelined together with
|
||||||
|
regular register writes in what replaced the MEQ.
|
||||||
|
-->
|
||||||
|
|
||||||
|
<bitset name="void" inline="yes">
|
||||||
|
<doc>Special type to mark registers with no payload.</doc>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<domain name="A6XX_PIPE_REG" width="32">
|
||||||
|
<!-- This replaces CP_WFI_PEND_CTR on a3xx-a5xx -->
|
||||||
|
<reg32 name="WFI_PEND_DECR" offset="0x81" type="void"/>
|
||||||
|
<!-- This is only used for WRITE_PRIMITIVE_COUNTS/ZPASS_DONE events -->
|
||||||
|
<reg32 name="QUERY_PEND_DECR" offset="0x82" type="void"/>
|
||||||
|
<reg32 name="WAIT_MEM_WRITES" offset="0x84" type="void"/>
|
||||||
|
|
||||||
|
<!-- Replaces CP_ME_NRT_ADDR/DATA on a3xx-a5xx -->
|
||||||
|
<reg64 name="NRT_ADDR" offset="0xa0"/>
|
||||||
|
<reg32 name="NRT_DATA" offset="0xa2"/>
|
||||||
|
|
||||||
|
<reg32 name="EVENT_CMD" offset="0xe7">
|
||||||
|
<enum name="a6xx_event_type">
|
||||||
|
<value value="0" name="UNK_EVENT"/> <!-- sometimes used with binning draws? -->
|
||||||
|
<value value="1" name="EVENT"/>
|
||||||
|
<value value="2" name="DRAW"/>
|
||||||
|
<value value="3" name="DISPATCH"/>
|
||||||
|
</enum>
|
||||||
|
<bitfield name="EVENT_TYPE" low="0" high="1" type="a6xx_event_type"/>
|
||||||
|
<!-- set for all *_TS events (i.e. ones that write something) -->
|
||||||
|
<bitfield name="TS_WRITE" pos="2" type="boolean"/>
|
||||||
|
<!-- Decrement CACHE_FLUSH_PEND_CTR when event happens -->
|
||||||
|
<bitfield name="CACHE_FLUSH_PEND_DECR" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg64 name="EVENT_TS_ADDR" offset="0xe8"/>
|
||||||
|
<reg32 name="EVENT_TS_CTRL" offset="0xea">
|
||||||
|
<bitfield name="TIMESTAMP" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="INTERRUPT" pos="2" type="boolean"/>
|
||||||
|
<enum name="a6xx_ts_event">
|
||||||
|
<value value="1" name="CACHE_FLUSH"/>
|
||||||
|
<value value="2" name="WT_DONE"/>
|
||||||
|
<value value="3" name="RB_DONE"/>
|
||||||
|
<value value="4" name="CCU_FLUSH_DEPTH"/>
|
||||||
|
<value value="5" name="CCU_FLUSH_COLOR"/>
|
||||||
|
<value value="6" name="CCU_RESOLVE"/>
|
||||||
|
</enum>
|
||||||
|
<bitfield name="EVENT" low="8" high="10" type="a6xx_ts_event"/>
|
||||||
|
</reg32>
|
||||||
|
<!-- data to write when !EVENT_TS_CTRL::TIMESTAMP -->
|
||||||
|
<reg32 name="EVENT_TS_DATA" offset="0xeb"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,42 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
|
||||||
|
<domain name="OCMEM" width="32">
|
||||||
|
<enum name="ocmem_macro_state">
|
||||||
|
<value name="PASSTHROUGH" value="0"/>
|
||||||
|
<value name="PERI_ON" value="1"/>
|
||||||
|
<value name="CORE_ON" value="2"/>
|
||||||
|
<value name="CLK_OFF" value="4"/>
|
||||||
|
</enum>
|
||||||
|
<reg32 offset="0x00" name="HW_VERSION"/>
|
||||||
|
<reg32 offset="0x04" name="HW_PROFILE">
|
||||||
|
<bitfield name="NUM_PORTS" low="0" high="3" type="uint"/>
|
||||||
|
<bitfield name="NUM_MACROS" low="8" high="13" type="uint"/>
|
||||||
|
<bitfield name="LAST_REGN_HALFSIZE" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="INTERLEAVING" pos="17" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0c" name="GEN_STATUS"/>
|
||||||
|
<reg32 offset="0x38" name="PSGSC_STATUS"/>
|
||||||
|
<!-- length is 4 for 8084, 3 for 8974/8092, 1 for 8226: -->
|
||||||
|
<array offset="0x3c" name="PSGSC" stride="1" length="4">
|
||||||
|
<reg32 offset="0x0" name="CTL">
|
||||||
|
<bitfield name="MACRO0_MODE" low="0" high="2" type="ocmem_macro_state"/>
|
||||||
|
<bitfield name="MACRO1_MODE" low="4" high="6" type="ocmem_macro_state"/>
|
||||||
|
<bitfield name="MACRO2_MODE" low="8" high="10" type="ocmem_macro_state"/>
|
||||||
|
<bitfield name="MACRO3_MODE" low="12" high="14" type="ocmem_macro_state"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x1000" name="REGION_MODE_CTL">
|
||||||
|
<bitfield name="REG0_THIN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="REG1_THIN" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="REG2_THIN" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="REG3_THIN" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x1004" name="GFX_MPU_START"/>
|
||||||
|
<reg32 offset="0x1008" name="GFX_MPU_END"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,997 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
|
||||||
|
<domain name="DSI" width="32">
|
||||||
|
<enum name="dsi_traffic_mode">
|
||||||
|
<value name="NON_BURST_SYNCH_PULSE" value="0"/>
|
||||||
|
<value name="NON_BURST_SYNCH_EVENT" value="1"/>
|
||||||
|
<value name="BURST_MODE" value="2"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="dsi_vid_dst_format">
|
||||||
|
<value name="VID_DST_FORMAT_RGB565" value="0"/>
|
||||||
|
<value name="VID_DST_FORMAT_RGB666" value="1"/>
|
||||||
|
<value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
|
||||||
|
<value name="VID_DST_FORMAT_RGB888" value="3"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="dsi_rgb_swap">
|
||||||
|
<value name="SWAP_RGB" value="0"/>
|
||||||
|
<value name="SWAP_RBG" value="1"/>
|
||||||
|
<value name="SWAP_BGR" value="2"/>
|
||||||
|
<value name="SWAP_BRG" value="3"/>
|
||||||
|
<value name="SWAP_GRB" value="4"/>
|
||||||
|
<value name="SWAP_GBR" value="5"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="dsi_cmd_trigger">
|
||||||
|
<value name="TRIGGER_NONE" value="0"/>
|
||||||
|
<value name="TRIGGER_SEOF" value="1"/>
|
||||||
|
<value name="TRIGGER_TE" value="2"/>
|
||||||
|
<value name="TRIGGER_SW" value="4"/>
|
||||||
|
<value name="TRIGGER_SW_SEOF" value="5"/>
|
||||||
|
<value name="TRIGGER_SW_TE" value="6"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="dsi_cmd_dst_format">
|
||||||
|
<value name="CMD_DST_FORMAT_RGB111" value="0"/>
|
||||||
|
<value name="CMD_DST_FORMAT_RGB332" value="3"/>
|
||||||
|
<value name="CMD_DST_FORMAT_RGB444" value="4"/>
|
||||||
|
<value name="CMD_DST_FORMAT_RGB565" value="6"/>
|
||||||
|
<value name="CMD_DST_FORMAT_RGB666" value="7"/>
|
||||||
|
<value name="CMD_DST_FORMAT_RGB888" value="8"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="dsi_lane_swap">
|
||||||
|
<value name="LANE_SWAP_0123" value="0"/>
|
||||||
|
<value name="LANE_SWAP_3012" value="1"/>
|
||||||
|
<value name="LANE_SWAP_2301" value="2"/>
|
||||||
|
<value name="LANE_SWAP_1230" value="3"/>
|
||||||
|
<value name="LANE_SWAP_0321" value="4"/>
|
||||||
|
<value name="LANE_SWAP_1032" value="5"/>
|
||||||
|
<value name="LANE_SWAP_2103" value="6"/>
|
||||||
|
<value name="LANE_SWAP_3210" value="7"/>
|
||||||
|
</enum>
|
||||||
|
<bitset name="DSI_IRQ">
|
||||||
|
<bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="CMD_MDP_DONE" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="VIDEO_DONE" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="BTA_DONE" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/>
|
||||||
|
<bitfield name="ERROR" pos="24" type="boolean"/>
|
||||||
|
<bitfield name="MASK_ERROR" pos="25" type="boolean"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<reg32 offset="0x00000" name="6G_HW_VERSION">
|
||||||
|
<bitfield name="MAJOR" low="28" high="31" type="uint"/>
|
||||||
|
<bitfield name="MINOR" low="16" high="27" type="uint"/>
|
||||||
|
<bitfield name="STEP" low="0" high="15" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00000" name="CTRL">
|
||||||
|
<bitfield name="ENABLE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="VID_MODE_EN" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="CMD_MODE_EN" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="LANE0" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="LANE1" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="LANE2" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="LANE3" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="CLK_EN" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="ECC_CHECK" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="CRC_CHECK" pos="24" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00004" name="STATUS0">
|
||||||
|
<bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="CMD_MODE_DMA_BUSY" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="CMD_MODE_MDP_BUSY" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="VIDEO_MODE_ENGINE_BUSY" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="DSI_BUSY" pos="4" type="boolean"/> <!-- see mipi_dsi_cmd_bta_sw_trigger() -->
|
||||||
|
<bitfield name="INTERLEAVE_OP_CONTENTION" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00008" name="FIFO_STATUS">
|
||||||
|
<bitfield name="VIDEO_MDP_FIFO_OVERFLOW" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="VIDEO_MDP_FIFO_UNDERFLOW" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="CMD_MDP_FIFO_UNDERFLOW" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="CMD_DMA_FIFO_RD_WATERMARK_REACH" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="CMD_DMA_FIFO_WR_WATERMARK_REACH" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="CMD_DMA_FIFO_UNDERFLOW" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_LP_FIFO_EMPTY" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_LP_FIFO_FULL" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_LP_FIFO_OVERFLOW" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_HS_FIFO_EMPTY" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_HS_FIFO_FULL" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_HS_FIFO_OVERFLOW" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_HS_FIFO_UNDERFLOW" pos="19" type="boolean"/>
|
||||||
|
<bitfield name="DLN1_HS_FIFO_EMPTY" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="DLN1_HS_FIFO_FULL" pos="21" type="boolean"/>
|
||||||
|
<bitfield name="DLN1_HS_FIFO_OVERFLOW" pos="22" type="boolean"/>
|
||||||
|
<bitfield name="DLN1_HS_FIFO_UNDERFLOW" pos="23" type="boolean"/>
|
||||||
|
<bitfield name="DLN2_HS_FIFO_EMPTY" pos="24" type="boolean"/>
|
||||||
|
<bitfield name="DLN2_HS_FIFO_FULL" pos="25" type="boolean"/>
|
||||||
|
<bitfield name="DLN2_HS_FIFO_OVERFLOW" pos="26" type="boolean"/>
|
||||||
|
<bitfield name="DLN2_HS_FIFO_UNDERFLOW" pos="27" type="boolean"/>
|
||||||
|
<bitfield name="DLN3_HS_FIFO_EMPTY" pos="28" type="boolean"/>
|
||||||
|
<bitfield name="DLN3_HS_FIFO_FULL" pos="29" type="boolean"/>
|
||||||
|
<bitfield name="DLN3_HS_FIFO_OVERFLOW" pos="30" type="boolean"/>
|
||||||
|
<bitfield name="DLN3_HS_FIFO_UNDERFLOW" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0000c" name="VID_CFG0">
|
||||||
|
<bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> <!-- always zero? -->
|
||||||
|
<bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
|
||||||
|
<bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
|
||||||
|
<bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="HSA_POWER_STOP" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="HBP_POWER_STOP" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="HFP_POWER_STOP" pos="24" type="boolean"/>
|
||||||
|
<bitfield name="PULSE_MODE_HSA_HE" pos="28" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0001c" name="VID_CFG1">
|
||||||
|
<bitfield name="R_SEL" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="G_SEL" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="B_SEL" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00020" name="ACTIVE_H">
|
||||||
|
<bitfield name="START" low="0" high="11" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="27" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00024" name="ACTIVE_V">
|
||||||
|
<bitfield name="START" low="0" high="11" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="27" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00028" name="TOTAL">
|
||||||
|
<bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
|
||||||
|
<bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0002c" name="ACTIVE_HSYNC">
|
||||||
|
<bitfield name="START" low="0" high="11" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="27" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">
|
||||||
|
<bitfield name="START" low="0" high="11" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="27" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">
|
||||||
|
<bitfield name="START" low="0" high="11" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="27" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00038" name="CMD_DMA_CTRL">
|
||||||
|
<bitfield name="BROADCAST_EN" pos="31" type="boolean"/>
|
||||||
|
<bitfield name="FROM_FRAME_BUFFER" pos="28" type="boolean"/>
|
||||||
|
<bitfield name="LOW_POWER" pos="26" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0003c" name="CMD_CFG0">
|
||||||
|
<bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/>
|
||||||
|
<bitfield name="R_SEL" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="G_SEL" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="B_SEL" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/>
|
||||||
|
<bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00040" name="CMD_CFG1">
|
||||||
|
<bitfield name="WR_MEM_START" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="WR_MEM_CONTINUE" low="8" high="15" type="uint"/>
|
||||||
|
<bitfield name="INSERT_DCS_COMMAND" pos="16" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00044" name="DMA_BASE"/>
|
||||||
|
<reg32 offset="0x00048" name="DMA_LEN"/>
|
||||||
|
<reg32 offset="0x00054" name="CMD_MDP_STREAM0_CTRL">
|
||||||
|
<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
|
||||||
|
<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
|
||||||
|
<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL">
|
||||||
|
<bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
|
||||||
|
<bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL">
|
||||||
|
<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
|
||||||
|
<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
|
||||||
|
<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00060" name="CMD_MDP_STREAM1_TOTAL">
|
||||||
|
<bitfield name="H_TOTAL" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="V_TOTAL" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00064" name="ACK_ERR_STATUS"/>
|
||||||
|
<array offset="0x00068" name="RDBK" length="4" stride="4">
|
||||||
|
<reg32 offset="0x0" name="DATA"/>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x00080" name="TRIG_CTRL">
|
||||||
|
<bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/>
|
||||||
|
<bitfield name="MDP_TRIGGER" low="4" high="6" type="dsi_cmd_trigger"/>
|
||||||
|
<bitfield name="STREAM" low="8" high="9" type="uint"/>
|
||||||
|
<bitfield name="BLOCK_DMA_WITHIN_FRAME" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="TE" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0008c" name="TRIG_DMA"/>
|
||||||
|
<reg32 offset="0x000b0" name="DLN0_PHY_ERR">
|
||||||
|
<bitfield name="DLN0_ERR_ESC" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_ERR_SYNC_ESC" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_ERR_CONTROL" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_ERR_CONTENTION_LP0" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_ERR_CONTENTION_LP1" pos="16" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000b4" name="LP_TIMER_CTRL">
|
||||||
|
<bitfield name="LP_RX_TO" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="BTA_TO" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000b8" name="HS_TIMER_CTRL">
|
||||||
|
<bitfield name="HS_TX_TO" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="TIMER_RESOLUTION" low="16" high="19" type="uint"/>
|
||||||
|
<bitfield name="HS_TX_TO_STOP_EN" pos="28" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000bc" name="TIMEOUT_STATUS"/>
|
||||||
|
<reg32 offset="0x000c0" name="CLKOUT_TIMING_CTRL">
|
||||||
|
<bitfield name="T_CLK_PRE" low="0" high="5" type="uint"/>
|
||||||
|
<bitfield name="T_CLK_POST" low="8" high="13" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000c8" name="EOT_PACKET_CTRL">
|
||||||
|
<bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="RX_EOT_IGNORE" pos="4" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000a4" name="LANE_STATUS">
|
||||||
|
<bitfield name="DLN0_STOPSTATE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="DLN1_STOPSTATE" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="DLN2_STOPSTATE" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="DLN3_STOPSTATE" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="CLKLN_STOPSTATE" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_ULPS_ACTIVE_NOT" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="DLN1_ULPS_ACTIVE_NOT" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="DLN2_ULPS_ACTIVE_NOT" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="DLN3_ULPS_ACTIVE_NOT" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="CLKLN_ULPS_ACTIVE_NOT" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000a8" name="LANE_CTRL">
|
||||||
|
<bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000ac" name="LANE_SWAP_CTRL">
|
||||||
|
<bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00108" name="ERR_INT_MASK0"/>
|
||||||
|
<reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/>
|
||||||
|
<reg32 offset="0x00114" name="RESET"/>
|
||||||
|
<reg32 offset="0x00118" name="CLK_CTRL">
|
||||||
|
<bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="AHBM_SCLK_ON" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="PCLK_ON" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="DSICLK_ON" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="BYTECLK_ON" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="ESCCLK_ON" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="FORCE_ON_DYN_AHBM_HCLK" pos="9" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0011c" name="CLK_STATUS">
|
||||||
|
<bitfield name="DSI_AON_AHBM_HCLK_ACTIVE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="DSI_DYN_AHBM_HCLK_ACTIVE" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="DSI_AON_AHBS_HCLK_ACTIVE" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="DSI_DYN_AHBS_HCLK_ACTIVE" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="DSI_AON_DSICLK_ACTIVE" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="DSI_DYN_DSICLK_ACTIVE" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="DSI_AON_BYTECLK_ACTIVE" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="DSI_DYN_BYTECLK_ACTIVE" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="DSI_AON_ESCCLK_ACTIVE" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="DSI_AON_PCLK_ACTIVE" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="DSI_DYN_PCLK_ACTIVE" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="DSI_DYN_CMD_PCLK_ACTIVE" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="DSI_CMD_PCLK_ACTIVE" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="DSI_VID_PCLK_ACTIVE" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="DSI_CAM_BIST_PCLK_ACT" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="PLL_UNLOCKED" pos="16" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00128" name="PHY_RESET">
|
||||||
|
<bitfield name="RESET" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND">
|
||||||
|
<bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x001b4" name="CMD_MODE_MDP_CTRL2">
|
||||||
|
<bitfield name="DST_FORMAT2" low="0" high="3" type="dsi_cmd_dst_format"/>
|
||||||
|
<bitfield name="R_SEL" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="G_SEL" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="B_SEL" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="BYTE_MSB_LSB_FLIP" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="RGB_SWAP" low="8" high="10" type="dsi_rgb_swap"/>
|
||||||
|
<bitfield name="INPUT_RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
|
||||||
|
<bitfield name="BURST_MODE" pos="16" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x001b8" name="CMD_MODE_MDP_STREAM2_CTRL">
|
||||||
|
<bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
|
||||||
|
<bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
|
||||||
|
<bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x001d0" name="RDBK_DATA_CTRL">
|
||||||
|
<bitfield name="COUNT" low="16" high="23" type="uint"/>
|
||||||
|
<bitfield name="CLR" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x001f0" name="VERSION">
|
||||||
|
<bitfield name="MAJOR" low="24" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00200" name="PHY_PLL_CTRL_0">
|
||||||
|
<bitfield name="ENABLE" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00204" name="PHY_PLL_CTRL_1"/>
|
||||||
|
<reg32 offset="0x00208" name="PHY_PLL_CTRL_2"/>
|
||||||
|
<reg32 offset="0x0020c" name="PHY_PLL_CTRL_3"/>
|
||||||
|
<reg32 offset="0x00210" name="PHY_PLL_CTRL_4"/>
|
||||||
|
<reg32 offset="0x00214" name="PHY_PLL_CTRL_5"/>
|
||||||
|
<reg32 offset="0x00218" name="PHY_PLL_CTRL_6"/>
|
||||||
|
<reg32 offset="0x0021c" name="PHY_PLL_CTRL_7"/>
|
||||||
|
<reg32 offset="0x00220" name="PHY_PLL_CTRL_8"/>
|
||||||
|
<reg32 offset="0x00224" name="PHY_PLL_CTRL_9"/>
|
||||||
|
<reg32 offset="0x00228" name="PHY_PLL_CTRL_10"/>
|
||||||
|
<reg32 offset="0x0022c" name="PHY_PLL_CTRL_11"/>
|
||||||
|
<reg32 offset="0x00230" name="PHY_PLL_CTRL_12"/>
|
||||||
|
<reg32 offset="0x00234" name="PHY_PLL_CTRL_13"/>
|
||||||
|
<reg32 offset="0x00238" name="PHY_PLL_CTRL_14"/>
|
||||||
|
<reg32 offset="0x0023c" name="PHY_PLL_CTRL_15"/>
|
||||||
|
<reg32 offset="0x00240" name="PHY_PLL_CTRL_16"/>
|
||||||
|
<reg32 offset="0x00244" name="PHY_PLL_CTRL_17"/>
|
||||||
|
<reg32 offset="0x00248" name="PHY_PLL_CTRL_18"/>
|
||||||
|
<reg32 offset="0x0024c" name="PHY_PLL_CTRL_19"/>
|
||||||
|
<reg32 offset="0x00250" name="PHY_PLL_CTRL_20"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00280" name="PHY_PLL_STATUS">
|
||||||
|
<bitfield name="PLL_BUSY" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_8x60" width="32">
|
||||||
|
<reg32 offset="0x00258" name="PHY_TPA_CTRL_1"/>
|
||||||
|
<reg32 offset="0x0025c" name="PHY_TPA_CTRL_2"/>
|
||||||
|
<reg32 offset="0x00260" name="PHY_TIMING_CTRL_0"/>
|
||||||
|
<reg32 offset="0x00264" name="PHY_TIMING_CTRL_1"/>
|
||||||
|
<reg32 offset="0x00268" name="PHY_TIMING_CTRL_2"/>
|
||||||
|
<reg32 offset="0x0026c" name="PHY_TIMING_CTRL_3"/>
|
||||||
|
<reg32 offset="0x00270" name="PHY_TIMING_CTRL_4"/>
|
||||||
|
<reg32 offset="0x00274" name="PHY_TIMING_CTRL_5"/>
|
||||||
|
<reg32 offset="0x00278" name="PHY_TIMING_CTRL_6"/>
|
||||||
|
<reg32 offset="0x0027c" name="PHY_TIMING_CTRL_7"/>
|
||||||
|
<reg32 offset="0x00280" name="PHY_TIMING_CTRL_8"/>
|
||||||
|
<reg32 offset="0x00284" name="PHY_TIMING_CTRL_9"/>
|
||||||
|
<reg32 offset="0x00288" name="PHY_TIMING_CTRL_10"/>
|
||||||
|
<reg32 offset="0x0028c" name="PHY_TIMING_CTRL_11"/>
|
||||||
|
<reg32 offset="0x00290" name="PHY_CTRL_0"/>
|
||||||
|
<reg32 offset="0x00294" name="PHY_CTRL_1"/>
|
||||||
|
<reg32 offset="0x00298" name="PHY_CTRL_2"/>
|
||||||
|
<reg32 offset="0x0029c" name="PHY_CTRL_3"/>
|
||||||
|
<reg32 offset="0x002a0" name="PHY_STRENGTH_0"/>
|
||||||
|
<reg32 offset="0x002a4" name="PHY_STRENGTH_1"/>
|
||||||
|
<reg32 offset="0x002a8" name="PHY_STRENGTH_2"/>
|
||||||
|
<reg32 offset="0x002ac" name="PHY_STRENGTH_3"/>
|
||||||
|
<reg32 offset="0x002cc" name="PHY_REGULATOR_CTRL_0"/>
|
||||||
|
<reg32 offset="0x002d0" name="PHY_REGULATOR_CTRL_1"/>
|
||||||
|
<reg32 offset="0x002d4" name="PHY_REGULATOR_CTRL_2"/>
|
||||||
|
<reg32 offset="0x002d8" name="PHY_REGULATOR_CTRL_3"/>
|
||||||
|
<reg32 offset="0x002dc" name="PHY_REGULATOR_CTRL_4"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x000f0" name="PHY_CAL_HW_TRIGGER"/>
|
||||||
|
<reg32 offset="0x000f4" name="PHY_CAL_CTRL"/>
|
||||||
|
<reg32 offset="0x000fc" name="PHY_CAL_STATUS">
|
||||||
|
<bitfield name="CAL_BUSY" pos="28" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_28nm_8960_PHY" width="32">
|
||||||
|
|
||||||
|
<array offset="0x00000" name="LN" length="4" stride="0x40">
|
||||||
|
<reg32 offset="0x00" name="CFG_0"/>
|
||||||
|
<reg32 offset="0x04" name="CFG_1"/>
|
||||||
|
<reg32 offset="0x08" name="CFG_2"/>
|
||||||
|
<reg32 offset="0x0c" name="TEST_DATAPATH"/>
|
||||||
|
<reg32 offset="0x14" name="TEST_STR_0"/>
|
||||||
|
<reg32 offset="0x18" name="TEST_STR_1"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<reg32 offset="0x00100" name="LNCK_CFG_0"/>
|
||||||
|
<reg32 offset="0x00104" name="LNCK_CFG_1"/>
|
||||||
|
<reg32 offset="0x00108" name="LNCK_CFG_2"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x0010c" name="LNCK_TEST_DATAPATH"/>
|
||||||
|
<reg32 offset="0x00114" name="LNCK_TEST_STR0"/>
|
||||||
|
<reg32 offset="0x00118" name="LNCK_TEST_STR1"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00140" name="TIMING_CTRL_0">
|
||||||
|
<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00144" name="TIMING_CTRL_1">
|
||||||
|
<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00148" name="TIMING_CTRL_2">
|
||||||
|
<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0014c" name="TIMING_CTRL_3"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00150" name="TIMING_CTRL_4">
|
||||||
|
<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00154" name="TIMING_CTRL_5">
|
||||||
|
<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00158" name="TIMING_CTRL_6">
|
||||||
|
<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0015c" name="TIMING_CTRL_7">
|
||||||
|
<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00160" name="TIMING_CTRL_8">
|
||||||
|
<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00164" name="TIMING_CTRL_9">
|
||||||
|
<bitfield name="TA_GO" low="0" high="2" type="uint"/>
|
||||||
|
<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00168" name="TIMING_CTRL_10">
|
||||||
|
<bitfield name="TA_GET" low="0" high="2" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0016c" name="TIMING_CTRL_11">
|
||||||
|
<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00170" name="CTRL_0"/>
|
||||||
|
<reg32 offset="0x00174" name="CTRL_1"/>
|
||||||
|
<reg32 offset="0x00178" name="CTRL_2"/>
|
||||||
|
<reg32 offset="0x0017c" name="CTRL_3"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00180" name="STRENGTH_0"/>
|
||||||
|
<reg32 offset="0x00184" name="STRENGTH_1"/>
|
||||||
|
<reg32 offset="0x00188" name="STRENGTH_2"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x0018c" name="BIST_CTRL_0"/>
|
||||||
|
<reg32 offset="0x00190" name="BIST_CTRL_1"/>
|
||||||
|
<reg32 offset="0x00194" name="BIST_CTRL_2"/>
|
||||||
|
<reg32 offset="0x00198" name="BIST_CTRL_3"/>
|
||||||
|
<reg32 offset="0x0019c" name="BIST_CTRL_4"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x001b0" name="LDO_CTRL"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_28nm_8960_PHY_MISC" width="32">
|
||||||
|
<reg32 offset="0x00000" name="REGULATOR_CTRL_0"/>
|
||||||
|
<reg32 offset="0x00004" name="REGULATOR_CTRL_1"/>
|
||||||
|
<reg32 offset="0x00008" name="REGULATOR_CTRL_2"/>
|
||||||
|
<reg32 offset="0x0000c" name="REGULATOR_CTRL_3"/>
|
||||||
|
<reg32 offset="0x00010" name="REGULATOR_CTRL_4"/>
|
||||||
|
<reg32 offset="0x00014" name="REGULATOR_CTRL_5"/>
|
||||||
|
<reg32 offset="0x00018" name="REGULATOR_CAL_PWR_CFG"/>
|
||||||
|
<reg32 offset="0x00028" name="CAL_HW_TRIGGER"/>
|
||||||
|
<reg32 offset="0x0002c" name="CAL_SW_CFG_0"/>
|
||||||
|
<reg32 offset="0x00030" name="CAL_SW_CFG_1"/>
|
||||||
|
<reg32 offset="0x00034" name="CAL_SW_CFG_2"/>
|
||||||
|
<reg32 offset="0x00038" name="CAL_HW_CFG_0"/>
|
||||||
|
<reg32 offset="0x0003c" name="CAL_HW_CFG_1"/>
|
||||||
|
<reg32 offset="0x00040" name="CAL_HW_CFG_2"/>
|
||||||
|
<reg32 offset="0x00044" name="CAL_HW_CFG_3"/>
|
||||||
|
<reg32 offset="0x00048" name="CAL_HW_CFG_4"/>
|
||||||
|
<reg32 offset="0x00050" name="CAL_STATUS">
|
||||||
|
<bitfield name="CAL_BUSY" pos="4" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_28nm_8960_PHY_PLL" width="32">
|
||||||
|
<reg32 offset="0x00000" name="CTRL_0">
|
||||||
|
<bitfield name="ENABLE" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00004" name="CTRL_1"/>
|
||||||
|
<reg32 offset="0x00008" name="CTRL_2"/>
|
||||||
|
<reg32 offset="0x0000c" name="CTRL_3"/>
|
||||||
|
<reg32 offset="0x00010" name="CTRL_4"/>
|
||||||
|
<reg32 offset="0x00014" name="CTRL_5"/>
|
||||||
|
<reg32 offset="0x00018" name="CTRL_6"/>
|
||||||
|
<reg32 offset="0x0001c" name="CTRL_7"/>
|
||||||
|
<reg32 offset="0x00020" name="CTRL_8"/>
|
||||||
|
<reg32 offset="0x00024" name="CTRL_9"/>
|
||||||
|
<reg32 offset="0x00028" name="CTRL_10"/>
|
||||||
|
<reg32 offset="0x0002c" name="CTRL_11"/>
|
||||||
|
<reg32 offset="0x00030" name="CTRL_12"/>
|
||||||
|
<reg32 offset="0x00034" name="CTRL_13"/>
|
||||||
|
<reg32 offset="0x00038" name="CTRL_14"/>
|
||||||
|
<reg32 offset="0x0003c" name="CTRL_15"/>
|
||||||
|
<reg32 offset="0x00040" name="CTRL_16"/>
|
||||||
|
<reg32 offset="0x00044" name="CTRL_17"/>
|
||||||
|
<reg32 offset="0x00048" name="CTRL_18"/>
|
||||||
|
<reg32 offset="0x0004c" name="CTRL_19"/>
|
||||||
|
<reg32 offset="0x00050" name="CTRL_20"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00080" name="RDY">
|
||||||
|
<bitfield name="PLL_RDY" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_28nm_PHY" width="32">
|
||||||
|
<array offset="0x00000" name="LN" length="4" stride="0x40">
|
||||||
|
<reg32 offset="0x00" name="CFG_0"/>
|
||||||
|
<reg32 offset="0x04" name="CFG_1"/>
|
||||||
|
<reg32 offset="0x08" name="CFG_2"/>
|
||||||
|
<reg32 offset="0x0c" name="CFG_3"/>
|
||||||
|
<reg32 offset="0x10" name="CFG_4"/>
|
||||||
|
<reg32 offset="0x14" name="TEST_DATAPATH"/>
|
||||||
|
<reg32 offset="0x18" name="DEBUG_SEL"/>
|
||||||
|
<reg32 offset="0x1c" name="TEST_STR_0"/>
|
||||||
|
<reg32 offset="0x20" name="TEST_STR_1"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<reg32 offset="0x00100" name="LNCK_CFG_0"/>
|
||||||
|
<reg32 offset="0x00104" name="LNCK_CFG_1"/>
|
||||||
|
<reg32 offset="0x00108" name="LNCK_CFG_2"/>
|
||||||
|
<reg32 offset="0x0010c" name="LNCK_CFG_3"/>
|
||||||
|
<reg32 offset="0x00110" name="LNCK_CFG_4"/>
|
||||||
|
<reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
|
||||||
|
<reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
|
||||||
|
<reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
|
||||||
|
<reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00140" name="TIMING_CTRL_0">
|
||||||
|
<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00144" name="TIMING_CTRL_1">
|
||||||
|
<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00148" name="TIMING_CTRL_2">
|
||||||
|
<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0014c" name="TIMING_CTRL_3">
|
||||||
|
<bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00150" name="TIMING_CTRL_4">
|
||||||
|
<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00154" name="TIMING_CTRL_5">
|
||||||
|
<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00158" name="TIMING_CTRL_6">
|
||||||
|
<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0015c" name="TIMING_CTRL_7">
|
||||||
|
<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00160" name="TIMING_CTRL_8">
|
||||||
|
<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00164" name="TIMING_CTRL_9">
|
||||||
|
<bitfield name="TA_GO" low="0" high="2" type="uint"/>
|
||||||
|
<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00168" name="TIMING_CTRL_10">
|
||||||
|
<bitfield name="TA_GET" low="0" high="2" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0016c" name="TIMING_CTRL_11">
|
||||||
|
<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00170" name="CTRL_0"/>
|
||||||
|
<reg32 offset="0x00174" name="CTRL_1"/>
|
||||||
|
<reg32 offset="0x00178" name="CTRL_2"/>
|
||||||
|
<reg32 offset="0x0017c" name="CTRL_3"/>
|
||||||
|
<reg32 offset="0x00180" name="CTRL_4"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00184" name="STRENGTH_0"/>
|
||||||
|
<reg32 offset="0x00188" name="STRENGTH_1"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x001b4" name="BIST_CTRL_0"/>
|
||||||
|
<reg32 offset="0x001b8" name="BIST_CTRL_1"/>
|
||||||
|
<reg32 offset="0x001bc" name="BIST_CTRL_2"/>
|
||||||
|
<reg32 offset="0x001c0" name="BIST_CTRL_3"/>
|
||||||
|
<reg32 offset="0x001c4" name="BIST_CTRL_4"/>
|
||||||
|
<reg32 offset="0x001c8" name="BIST_CTRL_5"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
|
||||||
|
<bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x001dc" name="LDO_CNTRL"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_28nm_PHY_REGULATOR" width="32">
|
||||||
|
<reg32 offset="0x00000" name="CTRL_0"/>
|
||||||
|
<reg32 offset="0x00004" name="CTRL_1"/>
|
||||||
|
<reg32 offset="0x00008" name="CTRL_2"/>
|
||||||
|
<reg32 offset="0x0000c" name="CTRL_3"/>
|
||||||
|
<reg32 offset="0x00010" name="CTRL_4"/>
|
||||||
|
<reg32 offset="0x00014" name="CTRL_5"/>
|
||||||
|
<reg32 offset="0x00018" name="CAL_PWR_CFG"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_28nm_PHY_PLL" width="32">
|
||||||
|
<reg32 offset="0x00000" name="REFCLK_CFG">
|
||||||
|
<bitfield name="DBLR" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00004" name="POSTDIV1_CFG"/>
|
||||||
|
<reg32 offset="0x00008" name="CHGPUMP_CFG"/>
|
||||||
|
<reg32 offset="0x0000C" name="VCOLPF_CFG"/>
|
||||||
|
<reg32 offset="0x00010" name="VREG_CFG">
|
||||||
|
<bitfield name="POSTDIV1_BYPASS_B" pos="1" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00014" name="PWRGEN_CFG"/>
|
||||||
|
<reg32 offset="0x00018" name="DMUX_CFG"/>
|
||||||
|
<reg32 offset="0x0001C" name="AMUX_CFG"/>
|
||||||
|
<reg32 offset="0x00020" name="GLB_CFG">
|
||||||
|
<bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00024" name="POSTDIV2_CFG"/>
|
||||||
|
<reg32 offset="0x00028" name="POSTDIV3_CFG"/>
|
||||||
|
<reg32 offset="0x0002C" name="LPFR_CFG"/>
|
||||||
|
<reg32 offset="0x00030" name="LPFC1_CFG"/>
|
||||||
|
<reg32 offset="0x00034" name="LPFC2_CFG"/>
|
||||||
|
<reg32 offset="0x00038" name="SDM_CFG0">
|
||||||
|
<bitfield name="BYP_DIV" low="0" high="5" type="uint"/>
|
||||||
|
<bitfield name="BYP" pos="6" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0003C" name="SDM_CFG1">
|
||||||
|
<bitfield name="DC_OFFSET" low="0" high="5" type="uint"/>
|
||||||
|
<bitfield name="DITHER_EN" pos="6" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00040" name="SDM_CFG2">
|
||||||
|
<bitfield name="FREQ_SEED_7_0" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00044" name="SDM_CFG3">
|
||||||
|
<bitfield name="FREQ_SEED_15_8" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00048" name="SDM_CFG4"/>
|
||||||
|
<reg32 offset="0x0004C" name="SSC_CFG0"/>
|
||||||
|
<reg32 offset="0x00050" name="SSC_CFG1"/>
|
||||||
|
<reg32 offset="0x00054" name="SSC_CFG2"/>
|
||||||
|
<reg32 offset="0x00058" name="SSC_CFG3"/>
|
||||||
|
<reg32 offset="0x0005C" name="LKDET_CFG0"/>
|
||||||
|
<reg32 offset="0x00060" name="LKDET_CFG1"/>
|
||||||
|
<reg32 offset="0x00064" name="LKDET_CFG2"/>
|
||||||
|
<reg32 offset="0x00068" name="TEST_CFG">
|
||||||
|
<bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0006C" name="CAL_CFG0"/>
|
||||||
|
<reg32 offset="0x00070" name="CAL_CFG1"/>
|
||||||
|
<reg32 offset="0x00074" name="CAL_CFG2"/>
|
||||||
|
<reg32 offset="0x00078" name="CAL_CFG3"/>
|
||||||
|
<reg32 offset="0x0007C" name="CAL_CFG4"/>
|
||||||
|
<reg32 offset="0x00080" name="CAL_CFG5"/>
|
||||||
|
<reg32 offset="0x00084" name="CAL_CFG6"/>
|
||||||
|
<reg32 offset="0x00088" name="CAL_CFG7"/>
|
||||||
|
<reg32 offset="0x0008C" name="CAL_CFG8"/>
|
||||||
|
<reg32 offset="0x00090" name="CAL_CFG9"/>
|
||||||
|
<reg32 offset="0x00094" name="CAL_CFG10"/>
|
||||||
|
<reg32 offset="0x00098" name="CAL_CFG11"/>
|
||||||
|
<reg32 offset="0x0009C" name="EFUSE_CFG"/>
|
||||||
|
<reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
|
||||||
|
<reg32 offset="0x000A4" name="CTRL_42"/>
|
||||||
|
<reg32 offset="0x000A8" name="CTRL_43"/>
|
||||||
|
<reg32 offset="0x000AC" name="CTRL_44"/>
|
||||||
|
<reg32 offset="0x000B0" name="CTRL_45"/>
|
||||||
|
<reg32 offset="0x000B4" name="CTRL_46"/>
|
||||||
|
<reg32 offset="0x000B8" name="CTRL_47"/>
|
||||||
|
<reg32 offset="0x000BC" name="CTRL_48"/>
|
||||||
|
<reg32 offset="0x000C0" name="STATUS">
|
||||||
|
<bitfield name="PLL_RDY" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000C4" name="DEBUG_BUS0"/>
|
||||||
|
<reg32 offset="0x000C8" name="DEBUG_BUS1"/>
|
||||||
|
<reg32 offset="0x000CC" name="DEBUG_BUS2"/>
|
||||||
|
<reg32 offset="0x000D0" name="DEBUG_BUS3"/>
|
||||||
|
<reg32 offset="0x000D4" name="CTRL_54"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_20nm_PHY" width="32">
|
||||||
|
<array offset="0x00000" name="LN" length="4" stride="0x40">
|
||||||
|
<reg32 offset="0x00" name="CFG_0"/>
|
||||||
|
<reg32 offset="0x04" name="CFG_1"/>
|
||||||
|
<reg32 offset="0x08" name="CFG_2"/>
|
||||||
|
<reg32 offset="0x0c" name="CFG_3"/>
|
||||||
|
<reg32 offset="0x10" name="CFG_4"/>
|
||||||
|
<reg32 offset="0x14" name="TEST_DATAPATH"/>
|
||||||
|
<reg32 offset="0x18" name="DEBUG_SEL"/>
|
||||||
|
<reg32 offset="0x1c" name="TEST_STR_0"/>
|
||||||
|
<reg32 offset="0x20" name="TEST_STR_1"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<reg32 offset="0x00100" name="LNCK_CFG_0"/>
|
||||||
|
<reg32 offset="0x00104" name="LNCK_CFG_1"/>
|
||||||
|
<reg32 offset="0x00108" name="LNCK_CFG_2"/>
|
||||||
|
<reg32 offset="0x0010c" name="LNCK_CFG_3"/>
|
||||||
|
<reg32 offset="0x00110" name="LNCK_CFG_4"/>
|
||||||
|
<reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
|
||||||
|
<reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
|
||||||
|
<reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
|
||||||
|
<reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00140" name="TIMING_CTRL_0">
|
||||||
|
<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00144" name="TIMING_CTRL_1">
|
||||||
|
<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00148" name="TIMING_CTRL_2">
|
||||||
|
<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0014c" name="TIMING_CTRL_3">
|
||||||
|
<bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00150" name="TIMING_CTRL_4">
|
||||||
|
<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00154" name="TIMING_CTRL_5">
|
||||||
|
<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00158" name="TIMING_CTRL_6">
|
||||||
|
<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0015c" name="TIMING_CTRL_7">
|
||||||
|
<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00160" name="TIMING_CTRL_8">
|
||||||
|
<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00164" name="TIMING_CTRL_9">
|
||||||
|
<bitfield name="TA_GO" low="0" high="2" type="uint"/>
|
||||||
|
<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00168" name="TIMING_CTRL_10">
|
||||||
|
<bitfield name="TA_GET" low="0" high="2" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0016c" name="TIMING_CTRL_11">
|
||||||
|
<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00170" name="CTRL_0"/>
|
||||||
|
<reg32 offset="0x00174" name="CTRL_1"/>
|
||||||
|
<reg32 offset="0x00178" name="CTRL_2"/>
|
||||||
|
<reg32 offset="0x0017c" name="CTRL_3"/>
|
||||||
|
<reg32 offset="0x00180" name="CTRL_4"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00184" name="STRENGTH_0"/>
|
||||||
|
<reg32 offset="0x00188" name="STRENGTH_1"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x001b4" name="BIST_CTRL_0"/>
|
||||||
|
<reg32 offset="0x001b8" name="BIST_CTRL_1"/>
|
||||||
|
<reg32 offset="0x001bc" name="BIST_CTRL_2"/>
|
||||||
|
<reg32 offset="0x001c0" name="BIST_CTRL_3"/>
|
||||||
|
<reg32 offset="0x001c4" name="BIST_CTRL_4"/>
|
||||||
|
<reg32 offset="0x001c8" name="BIST_CTRL_5"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
|
||||||
|
<bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x001dc" name="LDO_CNTRL"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_20nm_PHY_REGULATOR" width="32">
|
||||||
|
<reg32 offset="0x00000" name="CTRL_0"/>
|
||||||
|
<reg32 offset="0x00004" name="CTRL_1"/>
|
||||||
|
<reg32 offset="0x00008" name="CTRL_2"/>
|
||||||
|
<reg32 offset="0x0000c" name="CTRL_3"/>
|
||||||
|
<reg32 offset="0x00010" name="CTRL_4"/>
|
||||||
|
<reg32 offset="0x00014" name="CTRL_5"/>
|
||||||
|
<reg32 offset="0x00018" name="CAL_PWR_CFG"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_14nm_PHY_CMN" width="32">
|
||||||
|
<reg32 offset="0x00000" name="REVISION_ID0"/>
|
||||||
|
<reg32 offset="0x00004" name="REVISION_ID1"/>
|
||||||
|
<reg32 offset="0x00008" name="REVISION_ID2"/>
|
||||||
|
<reg32 offset="0x0000c" name="REVISION_ID3"/>
|
||||||
|
<reg32 offset="0x00010" name="CLK_CFG0">
|
||||||
|
<bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/>
|
||||||
|
<bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00014" name="CLK_CFG1">
|
||||||
|
<bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00018" name="GLBL_TEST_CTRL">
|
||||||
|
<bitfield name="BITCLK_HS_SEL" pos="2" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0001C" name="CTRL_0"/>
|
||||||
|
<reg32 offset="0x00020" name="CTRL_1">
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00024" name="HW_TRIGGER"/>
|
||||||
|
<reg32 offset="0x00028" name="SW_CFG0"/>
|
||||||
|
<reg32 offset="0x0002C" name="SW_CFG1"/>
|
||||||
|
<reg32 offset="0x00030" name="SW_CFG2"/>
|
||||||
|
<reg32 offset="0x00034" name="HW_CFG0"/>
|
||||||
|
<reg32 offset="0x00038" name="HW_CFG1"/>
|
||||||
|
<reg32 offset="0x0003C" name="HW_CFG2"/>
|
||||||
|
<reg32 offset="0x00040" name="HW_CFG3"/>
|
||||||
|
<reg32 offset="0x00044" name="HW_CFG4"/>
|
||||||
|
<reg32 offset="0x00048" name="PLL_CNTRL">
|
||||||
|
<bitfield name="PLL_START" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0004C" name="LDO_CNTRL">
|
||||||
|
<bitfield name="VREG_CTRL" low="0" high="5" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_14nm_PHY" width="32">
|
||||||
|
<array offset="0x00000" name="LN" length="5" stride="0x80">
|
||||||
|
<reg32 offset="0x00" name="CFG0">
|
||||||
|
<bitfield name="PREPARE_DLY" low="6" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x04" name="CFG1">
|
||||||
|
<bitfield name="HALFBYTECLK_EN" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x08" name="CFG2"/>
|
||||||
|
<reg32 offset="0x0c" name="CFG3"/>
|
||||||
|
<reg32 offset="0x10" name="TEST_DATAPATH"/>
|
||||||
|
<reg32 offset="0x14" name="TEST_STR"/>
|
||||||
|
<reg32 offset="0x18" name="TIMING_CTRL_4">
|
||||||
|
<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x1c" name="TIMING_CTRL_5">
|
||||||
|
<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x20" name="TIMING_CTRL_6">
|
||||||
|
<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x24" name="TIMING_CTRL_7">
|
||||||
|
<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x28" name="TIMING_CTRL_8">
|
||||||
|
<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x2c" name="TIMING_CTRL_9">
|
||||||
|
<bitfield name="TA_GO" low="0" high="2" type="uint"/>
|
||||||
|
<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x30" name="TIMING_CTRL_10">
|
||||||
|
<bitfield name="TA_GET" low="0" high="2" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x34" name="TIMING_CTRL_11">
|
||||||
|
<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x38" name="STRENGTH_CTRL_0"/>
|
||||||
|
<reg32 offset="0x3c" name="STRENGTH_CTRL_1"/>
|
||||||
|
<reg32 offset="0x64" name="VREG_CNTRL"/>
|
||||||
|
</array>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_14nm_PHY_PLL" width="32">
|
||||||
|
<reg32 offset="0x000" name="IE_TRIM"/>
|
||||||
|
<reg32 offset="0x004" name="IP_TRIM"/>
|
||||||
|
<reg32 offset="0x010" name="IPTAT_TRIM"/>
|
||||||
|
<reg32 offset="0x01c" name="CLKBUFLR_EN"/>
|
||||||
|
<reg32 offset="0x028" name="SYSCLK_EN_RESET"/>
|
||||||
|
<reg32 offset="0x02c" name="RESETSM_CNTRL"/>
|
||||||
|
<reg32 offset="0x030" name="RESETSM_CNTRL2"/>
|
||||||
|
<reg32 offset="0x034" name="RESETSM_CNTRL3"/>
|
||||||
|
<reg32 offset="0x038" name="RESETSM_CNTRL4"/>
|
||||||
|
<reg32 offset="0x03c" name="RESETSM_CNTRL5"/>
|
||||||
|
<reg32 offset="0x040" name="KVCO_DIV_REF1"/>
|
||||||
|
<reg32 offset="0x044" name="KVCO_DIV_REF2"/>
|
||||||
|
<reg32 offset="0x048" name="KVCO_COUNT1"/>
|
||||||
|
<reg32 offset="0x04c" name="KVCO_COUNT2"/>
|
||||||
|
<reg32 offset="0x05c" name="VREF_CFG1"/>
|
||||||
|
<reg32 offset="0x058" name="KVCO_CODE"/>
|
||||||
|
<reg32 offset="0x06c" name="VCO_DIV_REF1"/>
|
||||||
|
<reg32 offset="0x070" name="VCO_DIV_REF2"/>
|
||||||
|
<reg32 offset="0x074" name="VCO_COUNT1"/>
|
||||||
|
<reg32 offset="0x078" name="VCO_COUNT2"/>
|
||||||
|
<reg32 offset="0x07c" name="PLLLOCK_CMP1"/>
|
||||||
|
<reg32 offset="0x080" name="PLLLOCK_CMP2"/>
|
||||||
|
<reg32 offset="0x084" name="PLLLOCK_CMP3"/>
|
||||||
|
<reg32 offset="0x088" name="PLLLOCK_CMP_EN"/>
|
||||||
|
<reg32 offset="0x08c" name="PLL_VCO_TUNE"/>
|
||||||
|
<reg32 offset="0x090" name="DEC_START"/>
|
||||||
|
<reg32 offset="0x094" name="SSC_EN_CENTER"/>
|
||||||
|
<reg32 offset="0x098" name="SSC_ADJ_PER1"/>
|
||||||
|
<reg32 offset="0x09c" name="SSC_ADJ_PER2"/>
|
||||||
|
<reg32 offset="0x0a0" name="SSC_PER1"/>
|
||||||
|
<reg32 offset="0x0a4" name="SSC_PER2"/>
|
||||||
|
<reg32 offset="0x0a8" name="SSC_STEP_SIZE1"/>
|
||||||
|
<reg32 offset="0x0ac" name="SSC_STEP_SIZE2"/>
|
||||||
|
<reg32 offset="0x0b4" name="DIV_FRAC_START1"/>
|
||||||
|
<reg32 offset="0x0b8" name="DIV_FRAC_START2"/>
|
||||||
|
<reg32 offset="0x0bc" name="DIV_FRAC_START3"/>
|
||||||
|
<reg32 offset="0x0c0" name="TXCLK_EN"/>
|
||||||
|
<reg32 offset="0x0c4" name="PLL_CRCTRL"/>
|
||||||
|
<reg32 offset="0x0cc" name="RESET_SM_READY_STATUS"/>
|
||||||
|
<reg32 offset="0x0e8" name="PLL_MISC1"/>
|
||||||
|
<reg32 offset="0x0f0" name="CP_SET_CUR"/>
|
||||||
|
<reg32 offset="0x0f4" name="PLL_ICPMSET"/>
|
||||||
|
<reg32 offset="0x0f8" name="PLL_ICPCSET"/>
|
||||||
|
<reg32 offset="0x0fc" name="PLL_ICP_SET"/>
|
||||||
|
<reg32 offset="0x100" name="PLL_LPF1"/>
|
||||||
|
<reg32 offset="0x104" name="PLL_LPF2_POSTDIV"/>
|
||||||
|
<reg32 offset="0x108" name="PLL_BANDGAP"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_10nm_PHY_CMN" width="32">
|
||||||
|
<reg32 offset="0x00000" name="REVISION_ID0"/>
|
||||||
|
<reg32 offset="0x00004" name="REVISION_ID1"/>
|
||||||
|
<reg32 offset="0x00008" name="REVISION_ID2"/>
|
||||||
|
<reg32 offset="0x0000c" name="REVISION_ID3"/>
|
||||||
|
<reg32 offset="0x00010" name="CLK_CFG0"/>
|
||||||
|
<reg32 offset="0x00014" name="CLK_CFG1"/>
|
||||||
|
<reg32 offset="0x00018" name="GLBL_CTRL"/>
|
||||||
|
<reg32 offset="0x0001c" name="RBUF_CTRL"/>
|
||||||
|
<reg32 offset="0x00020" name="VREG_CTRL"/>
|
||||||
|
<reg32 offset="0x00024" name="CTRL_0"/>
|
||||||
|
<reg32 offset="0x00028" name="CTRL_1"/>
|
||||||
|
<reg32 offset="0x0002c" name="CTRL_2"/>
|
||||||
|
<reg32 offset="0x00030" name="LANE_CFG0"/>
|
||||||
|
<reg32 offset="0x00034" name="LANE_CFG1"/>
|
||||||
|
<reg32 offset="0x00038" name="PLL_CNTRL"/>
|
||||||
|
<reg32 offset="0x00098" name="LANE_CTRL0"/>
|
||||||
|
<reg32 offset="0x0009c" name="LANE_CTRL1"/>
|
||||||
|
<reg32 offset="0x000a0" name="LANE_CTRL2"/>
|
||||||
|
<reg32 offset="0x000a4" name="LANE_CTRL3"/>
|
||||||
|
<reg32 offset="0x000a8" name="LANE_CTRL4"/>
|
||||||
|
<reg32 offset="0x000ac" name="TIMING_CTRL_0"/>
|
||||||
|
<reg32 offset="0x000b0" name="TIMING_CTRL_1"/>
|
||||||
|
<reg32 offset="0x000b4" name="TIMING_CTRL_2"/>
|
||||||
|
<reg32 offset="0x000b8" name="TIMING_CTRL_3"/>
|
||||||
|
<reg32 offset="0x000bc" name="TIMING_CTRL_4"/>
|
||||||
|
<reg32 offset="0x000c0" name="TIMING_CTRL_5"/>
|
||||||
|
<reg32 offset="0x000c4" name="TIMING_CTRL_6"/>
|
||||||
|
<reg32 offset="0x000c8" name="TIMING_CTRL_7"/>
|
||||||
|
<reg32 offset="0x000cc" name="TIMING_CTRL_8"/>
|
||||||
|
<reg32 offset="0x000d0" name="TIMING_CTRL_9"/>
|
||||||
|
<reg32 offset="0x000d4" name="TIMING_CTRL_10"/>
|
||||||
|
<reg32 offset="0x000d8" name="TIMING_CTRL_11"/>
|
||||||
|
<reg32 offset="0x000ec" name="PHY_STATUS"/>
|
||||||
|
<reg32 offset="0x000f4" name="LANE_STATUS0"/>
|
||||||
|
<reg32 offset="0x000f8" name="LANE_STATUS1"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_10nm_PHY" width="32">
|
||||||
|
<array offset="0x00000" name="LN" length="5" stride="0x80">
|
||||||
|
<reg32 offset="0x00" name="CFG0"/>
|
||||||
|
<reg32 offset="0x04" name="CFG1"/>
|
||||||
|
<reg32 offset="0x08" name="CFG2"/>
|
||||||
|
<reg32 offset="0x0c" name="CFG3"/>
|
||||||
|
<reg32 offset="0x10" name="TEST_DATAPATH"/>
|
||||||
|
<reg32 offset="0x14" name="PIN_SWAP"/>
|
||||||
|
<reg32 offset="0x18" name="HSTX_STR_CTRL"/>
|
||||||
|
<reg32 offset="0x1c" name="OFFSET_TOP_CTRL"/>
|
||||||
|
<reg32 offset="0x20" name="OFFSET_BOT_CTRL"/>
|
||||||
|
<reg32 offset="0x24" name="LPTX_STR_CTRL"/>
|
||||||
|
<reg32 offset="0x28" name="LPRX_CTRL"/>
|
||||||
|
<reg32 offset="0x2c" name="TX_DCTRL"/>
|
||||||
|
</array>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="DSI_10nm_PHY_PLL" width="32">
|
||||||
|
<reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
|
||||||
|
<reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
|
||||||
|
<reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
|
||||||
|
<reg32 offset="0x001c" name="DSM_DIVIDER"/>
|
||||||
|
<reg32 offset="0x0020" name="FEEDBACK_DIVIDER"/>
|
||||||
|
<reg32 offset="0x0024" name="SYSTEM_MUXES"/>
|
||||||
|
<reg32 offset="0x002c" name="CMODE"/>
|
||||||
|
<reg32 offset="0x0030" name="CALIBRATION_SETTINGS"/>
|
||||||
|
<reg32 offset="0x0054" name="BAND_SEL_CAL_SETTINGS_THREE"/>
|
||||||
|
<reg32 offset="0x0064" name="FREQ_DETECT_SETTINGS_ONE"/>
|
||||||
|
<reg32 offset="0x007c" name="PFILT"/>
|
||||||
|
<reg32 offset="0x0080" name="IFILT"/>
|
||||||
|
<reg32 offset="0x0094" name="OUTDIV"/>
|
||||||
|
<reg32 offset="0x00a4" name="CORE_OVERRIDE"/>
|
||||||
|
<reg32 offset="0x00a8" name="CORE_INPUT_OVERRIDE"/>
|
||||||
|
<reg32 offset="0x00b4" name="PLL_DIGITAL_TIMERS_TWO"/>
|
||||||
|
<reg32 offset="0x00cc" name="DECIMAL_DIV_START_1"/>
|
||||||
|
<reg32 offset="0x00d0" name="FRAC_DIV_START_LOW_1"/>
|
||||||
|
<reg32 offset="0x00d4" name="FRAC_DIV_START_MID_1"/>
|
||||||
|
<reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH_1"/>
|
||||||
|
<reg32 offset="0x010c" name="SSC_STEPSIZE_LOW_1"/>
|
||||||
|
<reg32 offset="0x0110" name="SSC_STEPSIZE_HIGH_1"/>
|
||||||
|
<reg32 offset="0x0114" name="SSC_DIV_PER_LOW_1"/>
|
||||||
|
<reg32 offset="0x0118" name="SSC_DIV_PER_HIGH_1"/>
|
||||||
|
<reg32 offset="0x011c" name="SSC_DIV_ADJPER_LOW_1"/>
|
||||||
|
<reg32 offset="0x0120" name="SSC_DIV_ADJPER_HIGH_1"/>
|
||||||
|
<reg32 offset="0x013c" name="SSC_CONTROL"/>
|
||||||
|
<reg32 offset="0x0140" name="PLL_OUTDIV_RATE"/>
|
||||||
|
<reg32 offset="0x0144" name="PLL_LOCKDET_RATE_1"/>
|
||||||
|
<reg32 offset="0x014c" name="PLL_PROP_GAIN_RATE_1"/>
|
||||||
|
<reg32 offset="0x0154" name="PLL_BAND_SET_RATE_1"/>
|
||||||
|
<reg32 offset="0x015c" name="PLL_INT_GAIN_IFILT_BAND_1"/>
|
||||||
|
<reg32 offset="0x0164" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
|
||||||
|
<reg32 offset="0x0180" name="PLL_LOCK_OVERRIDE"/>
|
||||||
|
<reg32 offset="0x0184" name="PLL_LOCK_DELAY"/>
|
||||||
|
<reg32 offset="0x018c" name="CLOCK_INVERTERS"/>
|
||||||
|
<reg32 offset="0x01a0" name="COMMON_STATUS_ONE"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,48 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
|
||||||
|
<domain name="MMSS_CC" width="32">
|
||||||
|
<brief>
|
||||||
|
Multimedia sub-system clock control.. appears to be used by DSI
|
||||||
|
for clocks..
|
||||||
|
</brief>
|
||||||
|
|
||||||
|
<reg32 offset="0x0008" name="AHB"/>
|
||||||
|
|
||||||
|
<enum name="mmss_cc_clk">
|
||||||
|
<value name="CLK" value="0"/>
|
||||||
|
<value name="PCLK" value="1"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<!--
|
||||||
|
possibly these sequences of registers are same, except pre_div_func
|
||||||
|
is shifted by 12 in pclk and 14 in clk.. I'm going to guess that
|
||||||
|
the register is same and they just multiply value by 4..
|
||||||
|
-->
|
||||||
|
<array offsets="0x004c,0x0130" name="CLK" length="2" stride="0x10" index="mmss_cc_clk">
|
||||||
|
<reg32 offset="0x00" name="CC">
|
||||||
|
<bitfield name="CLK_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="ROOT_EN" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="MND_EN" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="MND_MODE" low="6" high="7"/>
|
||||||
|
<bitfield name="PMXO_SEL" low="8" high="9"/> <!-- not sure high -->
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x04" name="MD">
|
||||||
|
<bitfield name="D" low="0" high="7"/>
|
||||||
|
<bitfield name="M" low="8" high="15"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x08" name="NS">
|
||||||
|
<bitfield name="SRC" low="0" high="3"/> <!-- not sure high, but it is >= 1 -->
|
||||||
|
<bitfield name="PRE_DIV_FUNC" low="12" high="23"/>
|
||||||
|
<bitfield name="VAL" low="24" high="31"></bitfield>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x0094" name="DSI2_PIXEL_CC"/>
|
||||||
|
<reg32 offset="0x00e4" name="DSI2_PIXEL_NS"/>
|
||||||
|
<reg32 offset="0x0264" name="DSI2_PIXEL_CC2"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,17 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
|
||||||
|
<domain name="SFPB" width="32">
|
||||||
|
<enum name="sfpb_ahb_arb_master_port_en">
|
||||||
|
<value name="SFPB_MASTER_PORT_ENABLE" value="3"/>
|
||||||
|
<value name="SFPB_MASTER_PORT_DISABLE" value="0"/>
|
||||||
|
</enum>
|
||||||
|
<reg32 offset="0x0058" name="GPREG">
|
||||||
|
<bitfield name="MASTER_PORT_EN" low="11" high="12" type="sfpb_ahb_arb_master_port_en"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,239 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
|
||||||
|
<domain name="EDP" width="32">
|
||||||
|
<enum name="edp_color_depth">
|
||||||
|
<value name="EDP_6BIT" value="0"/>
|
||||||
|
<value name="EDP_8BIT" value="1"/>
|
||||||
|
<value name="EDP_10BIT" value="2"/>
|
||||||
|
<value name="EDP_12BIT" value="3"/>
|
||||||
|
<value name="EDP_16BIT" value="4"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="edp_component_format">
|
||||||
|
<value name="EDP_RGB" value="0"/>
|
||||||
|
<value name="EDP_YUV422" value="1"/>
|
||||||
|
<value name="EDP_YUV444" value="2"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<reg32 offset="0x0004" name="MAINLINK_CTRL">
|
||||||
|
<bitfield name="ENABLE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="RESET" pos="1" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0008" name="STATE_CTRL">
|
||||||
|
<bitfield name="TRAIN_PATTERN_1" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="TRAIN_PATTERN_2" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="TRAIN_PATTERN_3" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="SYMBOL_ERR_RATE_MEAS" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="PRBS7" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="CUSTOM_80_BIT_PATTERN" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="SEND_VIDEO" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="PUSH_IDLE" pos="7" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x000c" name="CONFIGURATION_CTRL">
|
||||||
|
<!-- next two may be swapped? -->
|
||||||
|
<bitfield name="SYNC_CLK" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="STATIC_MVID" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="PROGRESSIVE" pos="2" type="boolean"/>
|
||||||
|
<!-- # of lanes minus one: -->
|
||||||
|
<bitfield name="LANES" low="4" high="5" type="uint"/>
|
||||||
|
<bitfield name="ENHANCED_FRAMING" pos="6" type="boolean"/>
|
||||||
|
<!--
|
||||||
|
NOTE: only 6bit and 8bit valid
|
||||||
|
-->
|
||||||
|
<bitfield name="COLOR" pos="8" type="edp_color_depth"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0014" name="SOFTWARE_MVID" type="uint"/>
|
||||||
|
<reg32 offset="0x0018" name="SOFTWARE_NVID" type="uint"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x001c" name="TOTAL_HOR_VER">
|
||||||
|
<bitfield name="HORIZ" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="VERT" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0020" name="START_HOR_VER_FROM_SYNC">
|
||||||
|
<bitfield name="HORIZ" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="VERT" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0024" name="HSYNC_VSYNC_WIDTH_POLARITY">
|
||||||
|
<bitfield name="HORIZ" low="0" high="14" type="uint"/>
|
||||||
|
<bitfield name="NHSYNC" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="VERT" low="16" high="30" type="uint"/>
|
||||||
|
<bitfield name="NVSYNC" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0028" name="ACTIVE_HOR_VER">
|
||||||
|
<bitfield name="HORIZ" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="VERT" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x002c" name="MISC1_MISC0">
|
||||||
|
<!-- MISC0 from DisplayPort v1.2 spec: -->
|
||||||
|
<bitfield name="MISC0" low="0" high="7"/>
|
||||||
|
<!-- aliased MISC0 bitfields: -->
|
||||||
|
<bitfield name="SYNC" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="COMPONENT_FORMAT" low="1" high="2" type="edp_component_format"/>
|
||||||
|
<!-- CEA (vs VESA) color range: -->
|
||||||
|
<bitfield name="CEA" pos="3" type="boolean"/>
|
||||||
|
<!-- YCbCr Colorimetry ITU-R BT709-5 (vs ITU-R BT601-5): -->
|
||||||
|
<bitfield name="BT709_5" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="COLOR" low="5" high="7" type="edp_color_depth"/>
|
||||||
|
|
||||||
|
<!-- MISC1 from DisplayPort v1.2 spec: -->
|
||||||
|
<bitfield name="MISC1" low="8" high="15"/>
|
||||||
|
<!-- aliased MISC1 bitfields: -->
|
||||||
|
<bitfield name="INTERLACED_ODD" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="STEREO" low="9" high="10" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0074" name="PHY_CTRL">
|
||||||
|
<bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="SW_RESET" pos="2" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0084" name="MAINLINK_READY">
|
||||||
|
<bitfield name="TRAIN_PATTERN_1_READY" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="TRAIN_PATTERN_2_READY" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="TRAIN_PATTERN_3_READY" pos="5" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0300" name="AUX_CTRL">
|
||||||
|
<bitfield name="ENABLE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="RESET" pos="1" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<!-- interrupt registers come in sets of 3 bits, status/ack/en -->
|
||||||
|
<reg32 offset="0x0308" name="INTERRUPT_REG_1">
|
||||||
|
<bitfield name="HPD" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="HPD_ACK" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="HPD_EN" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="AUX_I2C_DONE" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="AUX_I2C_DONE_ACK" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="AUX_I2C_DONE_EN" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="WRONG_ADDR" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="WRONG_ADDR_ACK" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="WRONG_ADDR_EN" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="TIMEOUT" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="TIMEOUT_ACK" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="TIMEOUT_EN" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="NACK_DEFER" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="NACK_DEFER_ACK" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="NACK_DEFER_EN" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="WRONG_DATA_CNT" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="WRONG_DATA_CNT_ACK" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="WRONG_DATA_CNT_EN" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="I2C_NACK" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="I2C_NACK_ACK" pos="19" type="boolean"/>
|
||||||
|
<bitfield name="I2C_NACK_EN" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="I2C_DEFER" pos="21" type="boolean"/>
|
||||||
|
<bitfield name="I2C_DEFER_ACK" pos="22" type="boolean"/>
|
||||||
|
<bitfield name="I2C_DEFER_EN" pos="23" type="boolean"/>
|
||||||
|
<bitfield name="PLL_UNLOCK" pos="24" type="boolean"/>
|
||||||
|
<bitfield name="PLL_UNLOCK_ACK" pos="25" type="boolean"/>
|
||||||
|
<bitfield name="PLL_UNLOCK_EN" pos="26" type="boolean"/>
|
||||||
|
<bitfield name="AUX_ERROR" pos="27" type="boolean"/>
|
||||||
|
<bitfield name="AUX_ERROR_ACK" pos="28" type="boolean"/>
|
||||||
|
<bitfield name="AUX_ERROR_EN" pos="29" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x030c" name="INTERRUPT_REG_2">
|
||||||
|
<bitfield name="READY_FOR_VIDEO" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="READY_FOR_VIDEO_ACK" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="READY_FOR_VIDEO_EN" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="IDLE_PATTERNs_SENT" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="IDLE_PATTERNs_SENT_ACK" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="IDLE_PATTERNs_SENT_EN" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="FRAME_END" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="FRAME_END_ACK" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="FRAME_END_EN" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="CRC_UPDATED" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="CRC_UPDATED_ACK" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="CRC_UPDATED_EN" pos="11" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0310" name="INTERRUPT_TRANS_NUM"/>
|
||||||
|
<reg32 offset="0x0314" name="AUX_DATA">
|
||||||
|
<bitfield name="READ" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="DATA" low="8" high="15"/>
|
||||||
|
<bitfield name="INDEX" low="16" high="23"/>
|
||||||
|
<bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0318" name="AUX_TRANS_CTRL">
|
||||||
|
<bitfield name="I2C" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="GO" pos="9" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0324" name="AUX_STATUS"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="EDP_PHY" width="32">
|
||||||
|
<array offset="0x0400" name="LN" length="4" stride="0x40">
|
||||||
|
<reg32 offset="0x04" name="PD_CTL"/>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x0510" name="GLB_VM_CFG0"/>
|
||||||
|
<reg32 offset="0x0514" name="GLB_VM_CFG1"/>
|
||||||
|
<reg32 offset="0x0518" name="GLB_MISC9"/>
|
||||||
|
<reg32 offset="0x0528" name="GLB_CFG"/>
|
||||||
|
<reg32 offset="0x052c" name="GLB_PD_CTL"/>
|
||||||
|
<reg32 offset="0x0598" name="GLB_PHY_STATUS"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="EDP_28nm_PHY_PLL" width="32">
|
||||||
|
<reg32 offset="0x00000" name="REFCLK_CFG"/>
|
||||||
|
<reg32 offset="0x00004" name="POSTDIV1_CFG"/>
|
||||||
|
<reg32 offset="0x00008" name="CHGPUMP_CFG"/>
|
||||||
|
<reg32 offset="0x0000C" name="VCOLPF_CFG"/>
|
||||||
|
<reg32 offset="0x00010" name="VREG_CFG"/>
|
||||||
|
<reg32 offset="0x00014" name="PWRGEN_CFG"/>
|
||||||
|
<reg32 offset="0x00018" name="DMUX_CFG"/>
|
||||||
|
<reg32 offset="0x0001C" name="AMUX_CFG"/>
|
||||||
|
<reg32 offset="0x00020" name="GLB_CFG">
|
||||||
|
<bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00024" name="POSTDIV2_CFG"/>
|
||||||
|
<reg32 offset="0x00028" name="POSTDIV3_CFG"/>
|
||||||
|
<reg32 offset="0x0002C" name="LPFR_CFG"/>
|
||||||
|
<reg32 offset="0x00030" name="LPFC1_CFG"/>
|
||||||
|
<reg32 offset="0x00034" name="LPFC2_CFG"/>
|
||||||
|
<reg32 offset="0x00038" name="SDM_CFG0"/>
|
||||||
|
<reg32 offset="0x0003C" name="SDM_CFG1"/>
|
||||||
|
<reg32 offset="0x00040" name="SDM_CFG2"/>
|
||||||
|
<reg32 offset="0x00044" name="SDM_CFG3"/>
|
||||||
|
<reg32 offset="0x00048" name="SDM_CFG4"/>
|
||||||
|
<reg32 offset="0x0004C" name="SSC_CFG0"/>
|
||||||
|
<reg32 offset="0x00050" name="SSC_CFG1"/>
|
||||||
|
<reg32 offset="0x00054" name="SSC_CFG2"/>
|
||||||
|
<reg32 offset="0x00058" name="SSC_CFG3"/>
|
||||||
|
<reg32 offset="0x0005C" name="LKDET_CFG0"/>
|
||||||
|
<reg32 offset="0x00060" name="LKDET_CFG1"/>
|
||||||
|
<reg32 offset="0x00064" name="LKDET_CFG2"/>
|
||||||
|
<reg32 offset="0x00068" name="TEST_CFG">
|
||||||
|
<bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0006C" name="CAL_CFG0"/>
|
||||||
|
<reg32 offset="0x00070" name="CAL_CFG1"/>
|
||||||
|
<reg32 offset="0x00074" name="CAL_CFG2"/>
|
||||||
|
<reg32 offset="0x00078" name="CAL_CFG3"/>
|
||||||
|
<reg32 offset="0x0007C" name="CAL_CFG4"/>
|
||||||
|
<reg32 offset="0x00080" name="CAL_CFG5"/>
|
||||||
|
<reg32 offset="0x00084" name="CAL_CFG6"/>
|
||||||
|
<reg32 offset="0x00088" name="CAL_CFG7"/>
|
||||||
|
<reg32 offset="0x0008C" name="CAL_CFG8"/>
|
||||||
|
<reg32 offset="0x00090" name="CAL_CFG9"/>
|
||||||
|
<reg32 offset="0x00094" name="CAL_CFG10"/>
|
||||||
|
<reg32 offset="0x00098" name="CAL_CFG11"/>
|
||||||
|
<reg32 offset="0x0009C" name="EFUSE_CFG"/>
|
||||||
|
<reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,964 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
|
||||||
|
<!--
|
||||||
|
NOTE: also see mdss_hdmi_util.h.. newer devices using MDSS appear
|
||||||
|
to have the same HDMI block (or maybe a newer version?) but for
|
||||||
|
some reason duplicate the code under drivers/video/msm/mdss
|
||||||
|
-->
|
||||||
|
|
||||||
|
<domain name="HDMI" width="32">
|
||||||
|
<enum name="hdmi_hdcp_key_state">
|
||||||
|
<value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/>
|
||||||
|
<value name="HDCP_KEYS_STATE_NOT_CHECKED" value="1"/>
|
||||||
|
<value name="HDCP_KEYS_STATE_CHECKING" value="2"/>
|
||||||
|
<value name="HDCP_KEYS_STATE_VALID" value="3"/>
|
||||||
|
<value name="HDCP_KEYS_STATE_AKSV_NOT_VALID" value="4"/>
|
||||||
|
<value name="HDCP_KEYS_STATE_CHKSUM_MISMATCH" value="5"/>
|
||||||
|
<value name="HDCP_KEYS_STATE_PROD_AKSV" value="6"/>
|
||||||
|
<value name="HDCP_KEYS_STATE_RESERVED" value="7"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="hdmi_ddc_read_write">
|
||||||
|
<value name="DDC_WRITE" value="0"/>
|
||||||
|
<value name="DDC_READ" value="1"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="hdmi_acr_cts">
|
||||||
|
<value name="ACR_NONE" value="0"/>
|
||||||
|
<value name="ACR_32" value="1"/>
|
||||||
|
<value name="ACR_44" value="2"/>
|
||||||
|
<value name="ACR_48" value="3"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<reg32 offset="0x00000" name="CTRL">
|
||||||
|
<bitfield name="ENABLE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="HDMI" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="ENCRYPTED" pos="2" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
|
||||||
|
<bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00024" name="ACR_PKT_CTRL">
|
||||||
|
<!--
|
||||||
|
Guessing on order of bitfields from these comments:
|
||||||
|
/* AUDIO_PRIORITY | SOURCE */
|
||||||
|
acr_pck_ctrl_reg |= 0x80000100;
|
||||||
|
/* N_MULTIPLE(multiplier) */
|
||||||
|
acr_pck_ctrl_reg |= (multiplier & 7) << 16;
|
||||||
|
/* SEND | CONT */
|
||||||
|
acr_pck_ctrl_reg |= 0x00000003;
|
||||||
|
-->
|
||||||
|
<bitfield name="CONT" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="SEND" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="SELECT" low="4" high="5" type="hdmi_acr_cts"/>
|
||||||
|
<bitfield name="SOURCE" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="N_MULTIPLIER" low="16" high="18" type="uint"/>
|
||||||
|
<bitfield name="AUDIO_PRIORITY" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0028" name="VBI_PKT_CTRL">
|
||||||
|
<!--
|
||||||
|
Guessing on the order of bits from:
|
||||||
|
/* GC packet enable (every frame) */
|
||||||
|
/* HDMI_VBI_PKT_CTRL[0x0028] */
|
||||||
|
hdmi_msm_rmw32or(0x0028, 3 << 4);
|
||||||
|
/* HDMI_VBI_PKT_CTRL[0x0028] */
|
||||||
|
/* ISRC Send + Continuous */
|
||||||
|
hdmi_msm_rmw32or(0x0028, 3 << 8);
|
||||||
|
/* HDMI_VBI_PKT_CTRL[0x0028] */
|
||||||
|
/* ACP send, s/w source */
|
||||||
|
hdmi_msm_rmw32or(0x0028, 3 << 12);
|
||||||
|
-->
|
||||||
|
<bitfield name="GC_ENABLE" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="GC_EVERY_FRAME" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="ISRC_SEND" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="ISRC_CONTINUOUS" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="ACP_SEND" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="ACP_SRC_SW" pos="13" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
|
||||||
|
<!--
|
||||||
|
Guessing on the order of these flags, from this comment:
|
||||||
|
/* Set these flags */
|
||||||
|
/* AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT
|
||||||
|
| AUDIO_INFO_SEND */
|
||||||
|
audio_info_ctrl_reg |= 0x000000F0;
|
||||||
|
/* 0x3 for AVI InfFrame enable (every frame) */
|
||||||
|
HDMI_OUTP(0x002C, HDMI_INP(0x002C) | 0x00000003L);
|
||||||
|
-->
|
||||||
|
<bitfield name="AVI_SEND" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="AVI_CONT" pos="1" type="boolean"/> <!-- every frame -->
|
||||||
|
<bitfield name="AUDIO_INFO_SEND" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="AUDIO_INFO_CONT" pos="5" type="boolean"/> <!-- every frame -->
|
||||||
|
<bitfield name="AUDIO_INFO_SOURCE" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="AUDIO_INFO_UPDATE" pos="7" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00030" name="INFOFRAME_CTRL1">
|
||||||
|
<bitfield name="AVI_INFO_LINE" low="0" high="5" type="uint"/>
|
||||||
|
<bitfield name="AUDIO_INFO_LINE" low="8" high="13" type="uint"/>
|
||||||
|
<bitfield name="MPEG_INFO_LINE" low="16" high="21" type="uint"/>
|
||||||
|
<bitfield name="VENSPEC_INFO_LINE" low="24" high="29" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00034" name="GEN_PKT_CTRL">
|
||||||
|
<!--
|
||||||
|
0x0034 GEN_PKT_CTRL
|
||||||
|
GENERIC0_SEND 0 0 = Disable Generic0 Packet Transmission
|
||||||
|
1 = Enable Generic0 Packet Transmission
|
||||||
|
GENERIC0_CONT 1 0 = Send Generic0 Packet on next frame only
|
||||||
|
1 = Send Generic0 Packet on every frame
|
||||||
|
GENERIC0_UPDATE 2 NUM
|
||||||
|
GENERIC1_SEND 4 0 = Disable Generic1 Packet Transmission
|
||||||
|
1 = Enable Generic1 Packet Transmission
|
||||||
|
GENERIC1_CONT 5 0 = Send Generic1 Packet on next frame only
|
||||||
|
1 = Send Generic1 Packet on every frame
|
||||||
|
GENERIC0_LINE 21:16 NUM
|
||||||
|
GENERIC1_LINE 29:24 NUM
|
||||||
|
|
||||||
|
GENERIC0_LINE | GENERIC0_UPDATE | GENERIC0_CONT | GENERIC0_SEND
|
||||||
|
Setup HDMI TX generic packet control
|
||||||
|
Enable this packet to transmit every frame
|
||||||
|
Enable this packet to transmit every frame
|
||||||
|
Enable HDMI TX engine to transmit Generic packet 0
|
||||||
|
HDMI_OUTP(0x0034, (1 << 16) | (1 << 2) | BIT(1) | BIT(0));
|
||||||
|
-->
|
||||||
|
<bitfield name="GENERIC0_SEND" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="GENERIC0_CONT" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="GENERIC0_UPDATE" low="2" high="3" type="uint"/> <!-- ??? -->
|
||||||
|
<bitfield name="GENERIC1_SEND" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="GENERIC1_CONT" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="GENERIC0_LINE" low="16" high="21" type="uint"/>
|
||||||
|
<bitfield name="GENERIC1_LINE" low="24" high="29" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00040" name="GC">
|
||||||
|
<bitfield name="MUTE" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
|
||||||
|
<bitfield name="OVERRIDE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="LAYOUT" pos="1" type="boolean"/> <!-- 1 for >2 channels -->
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<!--
|
||||||
|
AVI_INFO appears to be the infoframe in a slightly weird order..
|
||||||
|
starts with PB0 (checksum), and ends with version..
|
||||||
|
-->
|
||||||
|
<reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00084" name="GENERIC0_HDR"/>
|
||||||
|
<reg32 offset="0x00088" name="GENERIC0" stride="4" length="7"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x000a4" name="GENERIC1_HDR"/>
|
||||||
|
<reg32 offset="0x000a8" name="GENERIC1" stride="4" length="7"/>
|
||||||
|
|
||||||
|
<!--
|
||||||
|
TODO add a way to show symbolic offsets into array: hdmi_acr_cts-1
|
||||||
|
-->
|
||||||
|
<array offset="0x00c4" name="ACR" length="3" stride="8" index="hdmi_acr_cts">
|
||||||
|
<reg32 offset="0" name="0">
|
||||||
|
<bitfield name="CTS" low="12" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="4" name="1">
|
||||||
|
<!-- not sure the actual # of bits.. -->
|
||||||
|
<bitfield name="N" low="0" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<reg32 offset="0x000e4" name="AUDIO_INFO0">
|
||||||
|
<bitfield name="CHECKSUM" low="0" high="7"/>
|
||||||
|
<bitfield name="CC" low="8" high="10" type="uint"/> <!-- channel count -->
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x000e8" name="AUDIO_INFO1">
|
||||||
|
<bitfield name="CA" low="0" high="7"/> <!-- Channel Allocation -->
|
||||||
|
<bitfield name="LSV" low="11" high="14"/> <!-- Level Shift -->
|
||||||
|
<bitfield name="DM_INH" pos="15" type="boolean"/> <!-- down-mix inhibit flag -->
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00110" name="HDCP_CTRL">
|
||||||
|
<bitfield name="ENABLE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="ENCRYPTION_ENABLE" pos="8" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00114" name="HDCP_DEBUG_CTRL">
|
||||||
|
<bitfield name="RNG_CIPHER" pos="2" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00118" name="HDCP_INT_CTRL">
|
||||||
|
<bitfield name="AUTH_SUCCESS_INT" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_SUCCESS_ACK" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_SUCCESS_MASK" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_FAIL_INT" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_FAIL_ACK" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_FAIL_MASK" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_FAIL_INFO_ACK" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_XFER_REQ_INT" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_XFER_REQ_ACK" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_XFER_REQ_MASK" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_XFER_DONE_INT" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_XFER_DONE_ACK" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="AUTH_XFER_DONE_MASK" pos="14" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0011c" name="HDCP_LINK0_STATUS">
|
||||||
|
<bitfield name="AN_0_READY" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="AN_1_READY" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="RI_MATCHES" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="V_MATCHES" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="KEY_STATE" low="28" high="30" type="hdmi_hdcp_key_state"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00120" name="HDCP_DDC_CTRL_0">
|
||||||
|
<bitfield name="DISABLE" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00124" name="HDCP_DDC_CTRL_1">
|
||||||
|
<bitfield name="FAILED_ACK" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00128" name="HDCP_DDC_STATUS">
|
||||||
|
<bitfield name="XFER_REQ" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="XFER_DONE" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="ABORTED" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="TIMEOUT" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="NACK0" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="NACK1" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="FAILED" pos="16" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0012c" name="HDCP_ENTROPY_CTRL0"/>
|
||||||
|
<reg32 offset="0x0025c" name="HDCP_ENTROPY_CTRL1"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00130" name="HDCP_RESET">
|
||||||
|
<bitfield name="LINK0_DEAUTHENTICATE" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00134" name="HDCP_RCVPORT_DATA0"/>
|
||||||
|
<reg32 offset="0x00138" name="HDCP_RCVPORT_DATA1"/>
|
||||||
|
<reg32 offset="0x0013C" name="HDCP_RCVPORT_DATA2_0"/>
|
||||||
|
<reg32 offset="0x00140" name="HDCP_RCVPORT_DATA2_1"/>
|
||||||
|
<reg32 offset="0x00144" name="HDCP_RCVPORT_DATA3"/>
|
||||||
|
<reg32 offset="0x00148" name="HDCP_RCVPORT_DATA4"/>
|
||||||
|
<reg32 offset="0x0014c" name="HDCP_RCVPORT_DATA5"/>
|
||||||
|
<reg32 offset="0x00150" name="HDCP_RCVPORT_DATA6"/>
|
||||||
|
<reg32 offset="0x00154" name="HDCP_RCVPORT_DATA7"/>
|
||||||
|
<reg32 offset="0x00158" name="HDCP_RCVPORT_DATA8"/>
|
||||||
|
<reg32 offset="0x0015c" name="HDCP_RCVPORT_DATA9"/>
|
||||||
|
<reg32 offset="0x00160" name="HDCP_RCVPORT_DATA10"/>
|
||||||
|
<reg32 offset="0x00164" name="HDCP_RCVPORT_DATA11"/>
|
||||||
|
<reg32 offset="0x00168" name="HDCP_RCVPORT_DATA12"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x0016c" name="VENSPEC_INFO0"/>
|
||||||
|
<reg32 offset="0x00170" name="VENSPEC_INFO1"/>
|
||||||
|
<reg32 offset="0x00174" name="VENSPEC_INFO2"/>
|
||||||
|
<reg32 offset="0x00178" name="VENSPEC_INFO3"/>
|
||||||
|
<reg32 offset="0x0017c" name="VENSPEC_INFO4"/>
|
||||||
|
<reg32 offset="0x00180" name="VENSPEC_INFO5"/>
|
||||||
|
<reg32 offset="0x00184" name="VENSPEC_INFO6"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x001d0" name="AUDIO_CFG">
|
||||||
|
<bitfield name="ENGINE_ENABLE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="FIFO_WATERMARK" low="4" high="7" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00208" name="USEC_REFTIMER"/>
|
||||||
|
<reg32 offset="0x0020c" name="DDC_CTRL">
|
||||||
|
<!--
|
||||||
|
0x020C HDMI_DDC_CTRL
|
||||||
|
[21:20] TRANSACTION_CNT
|
||||||
|
Number of transactions to be done in current transfer.
|
||||||
|
* 0x0: transaction0 only
|
||||||
|
* 0x1: transaction0, transaction1
|
||||||
|
* 0x2: transaction0, transaction1, transaction2
|
||||||
|
* 0x3: transaction0, transaction1, transaction2, transaction3
|
||||||
|
[3] SW_STATUS_RESET
|
||||||
|
Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE,
|
||||||
|
ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW,
|
||||||
|
STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3
|
||||||
|
[2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no
|
||||||
|
data) at start of transfer. This sequence is sent after GO is
|
||||||
|
written to 1, before the first transaction only.
|
||||||
|
[1] SOFT_RESET Write 1 to reset DDC controller
|
||||||
|
[0] GO WRITE ONLY. Write 1 to start DDC transfer.
|
||||||
|
-->
|
||||||
|
<bitfield name="GO" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="SOFT_RESET" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="SEND_RESET" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="SW_STATUS_RESET" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="TRANSACTION_CNT" low="20" high="21" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00210" name="DDC_ARBITRATION">
|
||||||
|
<bitfield name="HW_ARBITRATION" pos="4" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00214" name="DDC_INT_CTRL">
|
||||||
|
<!--
|
||||||
|
HDMI_DDC_INT_CTRL[0x0214]
|
||||||
|
[2] SW_DONE_MK Mask bit for SW_DONE_INT. Set to 1 to enable
|
||||||
|
interrupt.
|
||||||
|
[1] SW_DONE_ACK WRITE ONLY. Acknowledge bit for SW_DONE_INT.
|
||||||
|
Write 1 to clear interrupt.
|
||||||
|
[0] SW_DONE_INT READ ONLY. SW_DONE interrupt status */
|
||||||
|
-->
|
||||||
|
<bitfield name="SW_DONE_INT" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="SW_DONE_ACK" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="SW_DONE_MASK" pos="2" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00218" name="DDC_SW_STATUS">
|
||||||
|
<bitfield name="NACK0" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="NACK1" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="NACK2" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="NACK3" pos="15" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0021c" name="DDC_HW_STATUS">
|
||||||
|
<bitfield name="DONE" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00220" name="DDC_SPEED">
|
||||||
|
<!--
|
||||||
|
0x0220 HDMI_DDC_SPEED
|
||||||
|
[31:16] PRESCALE prescale = (m * xtal_frequency) /
|
||||||
|
(desired_i2c_speed), where m is multiply
|
||||||
|
factor, default: m = 1
|
||||||
|
[1:0] THRESHOLD Select threshold to use to determine whether value
|
||||||
|
sampled on SDA is a 1 or 0. Specified in terms of the ratio
|
||||||
|
between the number of sampled ones and the total number of times
|
||||||
|
SDA is sampled.
|
||||||
|
* 0x0: >0
|
||||||
|
* 0x1: 1/4 of total samples
|
||||||
|
* 0x2: 1/2 of total samples
|
||||||
|
* 0x3: 3/4 of total samples */
|
||||||
|
-->
|
||||||
|
<bitfield name="THRESHOLD" low="0" high="1" type="uint"/>
|
||||||
|
<bitfield name="PRESCALE" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00224" name="DDC_SETUP">
|
||||||
|
<!--
|
||||||
|
* 0x0224 HDMI_DDC_SETUP
|
||||||
|
* Setting 31:24 bits : Time units to wait before timeout
|
||||||
|
* when clock is being stalled by external sink device
|
||||||
|
-->
|
||||||
|
<bitfield name="TIMEOUT" low="24" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<!-- Guessing length is 4, as elsewhere the are references to trans0 thru trans3 -->
|
||||||
|
<array offset="0x00228" name="I2C_TRANSACTION" length="4" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<!--
|
||||||
|
0x0228 HDMI_DDC_TRANS0
|
||||||
|
[23:16] CNT0 Byte count for first transaction (excluding the first
|
||||||
|
byte, which is usually the address).
|
||||||
|
[13] STOP0 Determines whether a stop bit will be sent after the first
|
||||||
|
transaction
|
||||||
|
* 0: NO STOP
|
||||||
|
* 1: STOP
|
||||||
|
[12] START0 Determines whether a start bit will be sent before the
|
||||||
|
first transaction
|
||||||
|
* 0: NO START
|
||||||
|
* 1: START
|
||||||
|
[8] STOP_ON_NACK0 Determines whether the current transfer will stop
|
||||||
|
if a NACK is received during the first transaction (current
|
||||||
|
transaction always stops).
|
||||||
|
* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
|
||||||
|
* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
|
||||||
|
[0] RW0 Read/write indicator for first transaction - set to 0 for
|
||||||
|
write, 1 for read. This bit only controls HDMI_DDC behaviour -
|
||||||
|
the R/W bit in the transaction is programmed into the DDC buffer
|
||||||
|
as the LSB of the address byte.
|
||||||
|
* 0: WRITE
|
||||||
|
* 1: READ
|
||||||
|
-->
|
||||||
|
<bitfield name="RW" pos="0" type="hdmi_ddc_read_write"/>
|
||||||
|
<bitfield name="STOP_ON_NACK" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="START" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="STOP" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="CNT" low="16" high="23" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x00238" name="DDC_DATA">
|
||||||
|
<!--
|
||||||
|
0x0238 HDMI_DDC_DATA
|
||||||
|
[31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to
|
||||||
|
1 while writing HDMI_DDC_DATA.
|
||||||
|
[23:16] INDEX Use to set index into DDC buffer for next read or
|
||||||
|
current write, or to read index of current read or next write.
|
||||||
|
Writable only when INDEX_WRITE=1.
|
||||||
|
[15:8] DATA Use to fill or read the DDC buffer
|
||||||
|
[0] DATA_RW Select whether buffer access will be a read or write.
|
||||||
|
For writes, address auto-increments on write to HDMI_DDC_DATA.
|
||||||
|
For reads, address autoincrements on reads to HDMI_DDC_DATA.
|
||||||
|
* 0: Write
|
||||||
|
* 1: Read
|
||||||
|
-->
|
||||||
|
<bitfield name="DATA_RW" pos="0" type="hdmi_ddc_read_write"/>
|
||||||
|
<bitfield name="DATA" low="8" high="15" type="uint"/>
|
||||||
|
<bitfield name="INDEX" low="16" high="23" type="uint"/>
|
||||||
|
<bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x0023c" name="HDCP_SHA_CTRL"/>
|
||||||
|
<reg32 offset="0x00240" name="HDCP_SHA_STATUS">
|
||||||
|
<bitfield name="BLOCK_DONE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="COMP_DONE" pos="4" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00244" name="HDCP_SHA_DATA">
|
||||||
|
<bitfield name="DONE" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00250" name="HPD_INT_STATUS">
|
||||||
|
<bitfield name="INT" pos="0" type="boolean"/> <!-- an irq has occurred -->
|
||||||
|
<bitfield name="CABLE_DETECTED" pos="1" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00254" name="HPD_INT_CTRL">
|
||||||
|
<!-- (this useful comment was removed in df6b645.. git archaeology is fun)
|
||||||
|
HPD_INT_CTRL[0x0254]
|
||||||
|
31:10 Reserved
|
||||||
|
9 RCV_PLUGIN_DET_MASK receiver plug in interrupt mask.
|
||||||
|
When programmed to 1,
|
||||||
|
RCV_PLUGIN_DET_INT will toggle
|
||||||
|
the interrupt line
|
||||||
|
8:6 Reserved
|
||||||
|
5 RX_INT_EN Panel RX interrupt enable
|
||||||
|
0: Disable
|
||||||
|
1: Enable
|
||||||
|
4 RX_INT_ACK WRITE ONLY. Panel RX interrupt
|
||||||
|
ack
|
||||||
|
3 Reserved
|
||||||
|
2 INT_EN Panel interrupt control
|
||||||
|
0: Disable
|
||||||
|
1: Enable
|
||||||
|
1 INT_POLARITY Panel interrupt polarity
|
||||||
|
0: generate interrupt on disconnect
|
||||||
|
1: generate interrupt on connect
|
||||||
|
0 INT_ACK WRITE ONLY. Panel interrupt ack
|
||||||
|
-->
|
||||||
|
<bitfield name="INT_ACK" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="INT_CONNECT" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="INT_EN" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="RX_INT_ACK" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="RX_INT_EN" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="RCV_PLUGIN_DET_MASK" pos="9" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00258" name="HPD_CTRL">
|
||||||
|
<bitfield name="TIMEOUT" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="ENABLE" pos="28" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0027c" name="DDC_REF">
|
||||||
|
<!--
|
||||||
|
0x027C HDMI_DDC_REF
|
||||||
|
[16] REFTIMER_ENABLE Enable the timer
|
||||||
|
* 0: Disable
|
||||||
|
* 1: Enable
|
||||||
|
[15:0] REFTIMER Value to set the register in order to generate
|
||||||
|
DDC strobe. This register counts on HDCP application clock
|
||||||
|
|
||||||
|
/* Enable reference timer
|
||||||
|
* 27 micro-seconds */
|
||||||
|
HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0));
|
||||||
|
-->
|
||||||
|
<bitfield name="REFTIMER_ENABLE" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="REFTIMER" low="0" high="15" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00284" name="HDCP_SW_UPPER_AKSV"/>
|
||||||
|
<reg32 offset="0x00288" name="HDCP_SW_LOWER_AKSV"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x0028c" name="CEC_CTRL"/>
|
||||||
|
<reg32 offset="0x00290" name="CEC_WR_DATA"/>
|
||||||
|
<reg32 offset="0x00294" name="CEC_CEC_RETRANSMIT"/>
|
||||||
|
<reg32 offset="0x00298" name="CEC_STATUS"/>
|
||||||
|
<reg32 offset="0x0029c" name="CEC_INT"/>
|
||||||
|
<reg32 offset="0x002a0" name="CEC_ADDR"/>
|
||||||
|
<reg32 offset="0x002a4" name="CEC_TIME"/>
|
||||||
|
<reg32 offset="0x002a8" name="CEC_REFTIMER"/>
|
||||||
|
<reg32 offset="0x002ac" name="CEC_RD_DATA"/>
|
||||||
|
<reg32 offset="0x002b0" name="CEC_RD_FILTER"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x002b4" name="ACTIVE_HSYNC">
|
||||||
|
<bitfield name="START" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="27" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x002b8" name="ACTIVE_VSYNC">
|
||||||
|
<bitfield name="START" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x002bc" name="VSYNC_ACTIVE_F2">
|
||||||
|
<!-- interlaced, frame 2 -->
|
||||||
|
<bitfield name="START" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x002c0" name="TOTAL">
|
||||||
|
<bitfield name="H_TOTAL" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="V_TOTAL" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x002c4" name="VSYNC_TOTAL_F2">
|
||||||
|
<!-- interlaced, frame 2 -->
|
||||||
|
<bitfield name="V_TOTAL" low="0" high="12" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x002c8" name="FRAME_CTRL">
|
||||||
|
<bitfield name="RGB_MUX_SEL_BGR" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="VSYNC_LOW" pos="28" type="boolean"/>
|
||||||
|
<bitfield name="HSYNC_LOW" pos="29" type="boolean"/>
|
||||||
|
<bitfield name="INTERLACED_EN" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x002cc" name="AUD_INT">
|
||||||
|
<!--
|
||||||
|
HDMI_AUD_INT[0x02CC]
|
||||||
|
[3] AUD_SAM_DROP_MASK [R/W]
|
||||||
|
[2] AUD_SAM_DROP_ACK [W], AUD_SAM_DROP_INT [R]
|
||||||
|
[1] AUD_FIFO_URUN_MASK [R/W]
|
||||||
|
[0] AUD_FIFO_URUN_ACK [W], AUD_FIFO_URUN_INT [R]
|
||||||
|
-->
|
||||||
|
<bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/> <!-- write to ack irq -->
|
||||||
|
<bitfield name="AUD_FIFO_URAN_MASK" pos="1" type="boolean"/> <!-- r/w, enables irq -->
|
||||||
|
<bitfield name="AUD_SAM_DROP_INT" pos="2" type="boolean"/> <!-- write to ack irq -->
|
||||||
|
<bitfield name="AUD_SAM_DROP_MASK" pos="3" type="boolean"/> <!-- r/w, enables irq -->
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x002d4" name="PHY_CTRL">
|
||||||
|
<!--
|
||||||
|
in hdmi_phy_reset() it appears to be toggling SW_RESET/
|
||||||
|
SW_RESET_PLL based on the value of the bit above, so
|
||||||
|
I'm guessing the bit above is a polarit bit
|
||||||
|
-->
|
||||||
|
<bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="SW_RESET_PLL_LOW" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="SW_RESET" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="SW_RESET_LOW" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x002dc" name="CEC_WR_RANGE"/>
|
||||||
|
<reg32 offset="0x002e0" name="CEC_RD_RANGE"/>
|
||||||
|
<reg32 offset="0x002e4" name="VERSION"/>
|
||||||
|
<reg32 offset="0x00360" name="CEC_COMPL_CTL"/>
|
||||||
|
<reg32 offset="0x00364" name="CEC_RD_START_RANGE"/>
|
||||||
|
<reg32 offset="0x00368" name="CEC_RD_TOTAL_RANGE"/>
|
||||||
|
<reg32 offset="0x0036c" name="CEC_RD_ERR_RESP_LO"/>
|
||||||
|
<reg32 offset="0x00370" name="CEC_WR_CHECK_CONFIG"/>
|
||||||
|
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="HDMI_8x60" width="32">
|
||||||
|
<reg32 offset="0x00000" name="PHY_REG0">
|
||||||
|
<bitfield name="DESER_DEL_CTRL" low="2" high="4" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00004" name="PHY_REG1">
|
||||||
|
<bitfield name="DTEST_MUX_SEL" low="4" high="7" type="uint"/>
|
||||||
|
<bitfield name="OUTVOL_SWING_CTRL" low="0" high="3" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00008" name="PHY_REG2">
|
||||||
|
<bitfield name="PD_DESER" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="PD_DRIVE_1" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="PD_DRIVE_2" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="PD_DRIVE_3" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="PD_DRIVE_4" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="PD_PLL" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="PD_PWRGEN" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="RCV_SENSE_EN" pos="7" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0000c" name="PHY_REG3">
|
||||||
|
<bitfield name="PLL_ENABLE" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00010" name="PHY_REG4"/>
|
||||||
|
<reg32 offset="0x00014" name="PHY_REG5"/>
|
||||||
|
<reg32 offset="0x00018" name="PHY_REG6"/>
|
||||||
|
<reg32 offset="0x0001c" name="PHY_REG7"/>
|
||||||
|
<reg32 offset="0x00020" name="PHY_REG8"/>
|
||||||
|
<reg32 offset="0x00024" name="PHY_REG9"/>
|
||||||
|
<reg32 offset="0x00028" name="PHY_REG10"/>
|
||||||
|
<reg32 offset="0x0002c" name="PHY_REG11"/>
|
||||||
|
<reg32 offset="0x00030" name="PHY_REG12">
|
||||||
|
<bitfield name="RETIMING_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="PLL_LOCK_DETECT_EN" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="FORCE_LOCK" pos="4" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="HDMI_8960" width="32">
|
||||||
|
<!--
|
||||||
|
some of the bitfields may be same as 8x60.. but no helpful comments
|
||||||
|
in msm_dss_io_8960.c
|
||||||
|
-->
|
||||||
|
<reg32 offset="0x00000" name="PHY_REG0"/>
|
||||||
|
<reg32 offset="0x00004" name="PHY_REG1"/>
|
||||||
|
<reg32 offset="0x00008" name="PHY_REG2"/>
|
||||||
|
<reg32 offset="0x0000c" name="PHY_REG3"/>
|
||||||
|
<reg32 offset="0x00010" name="PHY_REG4"/>
|
||||||
|
<reg32 offset="0x00014" name="PHY_REG5"/>
|
||||||
|
<reg32 offset="0x00018" name="PHY_REG6"/>
|
||||||
|
<reg32 offset="0x0001c" name="PHY_REG7"/>
|
||||||
|
<reg32 offset="0x00020" name="PHY_REG8"/>
|
||||||
|
<reg32 offset="0x00024" name="PHY_REG9"/>
|
||||||
|
<reg32 offset="0x00028" name="PHY_REG10"/>
|
||||||
|
<reg32 offset="0x0002c" name="PHY_REG11"/>
|
||||||
|
<reg32 offset="0x00030" name="PHY_REG12">
|
||||||
|
<bitfield name="SW_RESET" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="PWRDN_B" pos="7" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00034" name="PHY_REG_BIST_CFG"/>
|
||||||
|
<reg32 offset="0x00038" name="PHY_DEBUG_BUS_SEL"/>
|
||||||
|
<reg32 offset="0x0003c" name="PHY_REG_MISC0"/>
|
||||||
|
<reg32 offset="0x00040" name="PHY_REG13"/>
|
||||||
|
<reg32 offset="0x00044" name="PHY_REG14"/>
|
||||||
|
<reg32 offset="0x00048" name="PHY_REG15"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="HDMI_8960_PHY_PLL" width="32">
|
||||||
|
<reg32 offset="0x00000" name="REFCLK_CFG"/>
|
||||||
|
<reg32 offset="0x00004" name="CHRG_PUMP_CFG"/>
|
||||||
|
<reg32 offset="0x00008" name="LOOP_FLT_CFG0"/>
|
||||||
|
<reg32 offset="0x0000c" name="LOOP_FLT_CFG1"/>
|
||||||
|
<reg32 offset="0x00010" name="IDAC_ADJ_CFG"/>
|
||||||
|
<reg32 offset="0x00014" name="I_VI_KVCO_CFG"/>
|
||||||
|
<reg32 offset="0x00018" name="PWRDN_B">
|
||||||
|
<bitfield name="PD_PLL" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="PLL_PWRDN_B" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0001c" name="SDM_CFG0"/>
|
||||||
|
<reg32 offset="0x00020" name="SDM_CFG1"/>
|
||||||
|
<reg32 offset="0x00024" name="SDM_CFG2"/>
|
||||||
|
<reg32 offset="0x00028" name="SDM_CFG3"/>
|
||||||
|
<reg32 offset="0x0002c" name="SDM_CFG4"/>
|
||||||
|
<reg32 offset="0x00030" name="SSC_CFG0"/>
|
||||||
|
<reg32 offset="0x00034" name="SSC_CFG1"/>
|
||||||
|
<reg32 offset="0x00038" name="SSC_CFG2"/>
|
||||||
|
<reg32 offset="0x0003c" name="SSC_CFG3"/>
|
||||||
|
<reg32 offset="0x00040" name="LOCKDET_CFG0"/>
|
||||||
|
<reg32 offset="0x00044" name="LOCKDET_CFG1"/>
|
||||||
|
<reg32 offset="0x00048" name="LOCKDET_CFG2"/>
|
||||||
|
<reg32 offset="0x0004c" name="VCOCAL_CFG0"/>
|
||||||
|
<reg32 offset="0x00050" name="VCOCAL_CFG1"/>
|
||||||
|
<reg32 offset="0x00054" name="VCOCAL_CFG2"/>
|
||||||
|
<reg32 offset="0x00058" name="VCOCAL_CFG3"/>
|
||||||
|
<reg32 offset="0x0005c" name="VCOCAL_CFG4"/>
|
||||||
|
<reg32 offset="0x00060" name="VCOCAL_CFG5"/>
|
||||||
|
<reg32 offset="0x00064" name="VCOCAL_CFG6"/>
|
||||||
|
<reg32 offset="0x00068" name="VCOCAL_CFG7"/>
|
||||||
|
<reg32 offset="0x0006c" name="DEBUG_SEL"/>
|
||||||
|
<reg32 offset="0x00070" name="MISC0"/>
|
||||||
|
<reg32 offset="0x00074" name="MISC1"/>
|
||||||
|
<reg32 offset="0x00078" name="MISC2"/>
|
||||||
|
<reg32 offset="0x0007c" name="MISC3"/>
|
||||||
|
<reg32 offset="0x00080" name="MISC4"/>
|
||||||
|
<reg32 offset="0x00084" name="MISC5"/>
|
||||||
|
<reg32 offset="0x00088" name="MISC6"/>
|
||||||
|
<reg32 offset="0x0008c" name="DEBUG_BUS0"/>
|
||||||
|
<reg32 offset="0x00090" name="DEBUG_BUS1"/>
|
||||||
|
<reg32 offset="0x00094" name="DEBUG_BUS2"/>
|
||||||
|
<reg32 offset="0x00098" name="STATUS0">
|
||||||
|
<bitfield name="PLL_LOCK" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0009c" name="STATUS1"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="HDMI_8x74" width="32">
|
||||||
|
<!--
|
||||||
|
seems to be all mdp5+ have same?
|
||||||
|
-->
|
||||||
|
<reg32 offset="0x00000" name="ANA_CFG0"/>
|
||||||
|
<reg32 offset="0x00004" name="ANA_CFG1"/>
|
||||||
|
<reg32 offset="0x00010" name="PD_CTRL0"/>
|
||||||
|
<reg32 offset="0x00014" name="PD_CTRL1"/>
|
||||||
|
<reg32 offset="0x00034" name="BIST_CFG0"/>
|
||||||
|
<reg32 offset="0x0003c" name="BIST_PATN0"/>
|
||||||
|
<reg32 offset="0x00040" name="BIST_PATN1"/>
|
||||||
|
<reg32 offset="0x00044" name="BIST_PATN2"/>
|
||||||
|
<reg32 offset="0x00048" name="BIST_PATN3"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="HDMI_28nm_PHY_PLL" width="32">
|
||||||
|
<reg32 offset="0x00000" name="REFCLK_CFG"/>
|
||||||
|
<reg32 offset="0x00004" name="POSTDIV1_CFG"/>
|
||||||
|
<reg32 offset="0x00008" name="CHGPUMP_CFG"/>
|
||||||
|
<reg32 offset="0x0000C" name="VCOLPF_CFG"/>
|
||||||
|
<reg32 offset="0x00010" name="VREG_CFG"/>
|
||||||
|
<reg32 offset="0x00014" name="PWRGEN_CFG"/>
|
||||||
|
<reg32 offset="0x00018" name="DMUX_CFG"/>
|
||||||
|
<reg32 offset="0x0001C" name="AMUX_CFG"/>
|
||||||
|
<reg32 offset="0x00020" name="GLB_CFG">
|
||||||
|
<bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00024" name="POSTDIV2_CFG"/>
|
||||||
|
<reg32 offset="0x00028" name="POSTDIV3_CFG"/>
|
||||||
|
<reg32 offset="0x0002C" name="LPFR_CFG"/>
|
||||||
|
<reg32 offset="0x00030" name="LPFC1_CFG"/>
|
||||||
|
<reg32 offset="0x00034" name="LPFC2_CFG"/>
|
||||||
|
<reg32 offset="0x00038" name="SDM_CFG0"/>
|
||||||
|
<reg32 offset="0x0003C" name="SDM_CFG1"/>
|
||||||
|
<reg32 offset="0x00040" name="SDM_CFG2"/>
|
||||||
|
<reg32 offset="0x00044" name="SDM_CFG3"/>
|
||||||
|
<reg32 offset="0x00048" name="SDM_CFG4"/>
|
||||||
|
<reg32 offset="0x0004C" name="SSC_CFG0"/>
|
||||||
|
<reg32 offset="0x00050" name="SSC_CFG1"/>
|
||||||
|
<reg32 offset="0x00054" name="SSC_CFG2"/>
|
||||||
|
<reg32 offset="0x00058" name="SSC_CFG3"/>
|
||||||
|
<reg32 offset="0x0005C" name="LKDET_CFG0"/>
|
||||||
|
<reg32 offset="0x00060" name="LKDET_CFG1"/>
|
||||||
|
<reg32 offset="0x00064" name="LKDET_CFG2"/>
|
||||||
|
<reg32 offset="0x00068" name="TEST_CFG">
|
||||||
|
<bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0006C" name="CAL_CFG0"/>
|
||||||
|
<reg32 offset="0x00070" name="CAL_CFG1"/>
|
||||||
|
<reg32 offset="0x00074" name="CAL_CFG2"/>
|
||||||
|
<reg32 offset="0x00078" name="CAL_CFG3"/>
|
||||||
|
<reg32 offset="0x0007C" name="CAL_CFG4"/>
|
||||||
|
<reg32 offset="0x00080" name="CAL_CFG5"/>
|
||||||
|
<reg32 offset="0x00084" name="CAL_CFG6"/>
|
||||||
|
<reg32 offset="0x00088" name="CAL_CFG7"/>
|
||||||
|
<reg32 offset="0x0008C" name="CAL_CFG8"/>
|
||||||
|
<reg32 offset="0x00090" name="CAL_CFG9"/>
|
||||||
|
<reg32 offset="0x00094" name="CAL_CFG10"/>
|
||||||
|
<reg32 offset="0x00098" name="CAL_CFG11"/>
|
||||||
|
<reg32 offset="0x0009C" name="EFUSE_CFG"/>
|
||||||
|
<reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="HDMI_8996_PHY" width="32">
|
||||||
|
<reg32 offset="0x00000" name="CFG"/>
|
||||||
|
<reg32 offset="0x00004" name="PD_CTL"/>
|
||||||
|
<reg32 offset="0x00008" name="MODE"/>
|
||||||
|
<reg32 offset="0x0000C" name="MISR_CLEAR"/>
|
||||||
|
<reg32 offset="0x00010" name="TX0_TX1_BIST_CFG0"/>
|
||||||
|
<reg32 offset="0x00014" name="TX0_TX1_BIST_CFG1"/>
|
||||||
|
<reg32 offset="0x00018" name="TX0_TX1_PRBS_SEED_BYTE0"/>
|
||||||
|
<reg32 offset="0x0001C" name="TX0_TX1_PRBS_SEED_BYTE1"/>
|
||||||
|
<reg32 offset="0x00020" name="TX0_TX1_BIST_PATTERN0"/>
|
||||||
|
<reg32 offset="0x00024" name="TX0_TX1_BIST_PATTERN1"/>
|
||||||
|
<reg32 offset="0x00028" name="TX2_TX3_BIST_CFG0"/>
|
||||||
|
<reg32 offset="0x0002C" name="TX2_TX3_BIST_CFG1"/>
|
||||||
|
<reg32 offset="0x00030" name="TX2_TX3_PRBS_SEED_BYTE0"/>
|
||||||
|
<reg32 offset="0x00034" name="TX2_TX3_PRBS_SEED_BYTE1"/>
|
||||||
|
<reg32 offset="0x00038" name="TX2_TX3_BIST_PATTERN0"/>
|
||||||
|
<reg32 offset="0x0003C" name="TX2_TX3_BIST_PATTERN1"/>
|
||||||
|
<reg32 offset="0x00040" name="DEBUG_BUS_SEL"/>
|
||||||
|
<reg32 offset="0x00044" name="TXCAL_CFG0"/>
|
||||||
|
<reg32 offset="0x00048" name="TXCAL_CFG1"/>
|
||||||
|
<reg32 offset="0x0004C" name="TX0_TX1_LANE_CTL"/>
|
||||||
|
<reg32 offset="0x00050" name="TX2_TX3_LANE_CTL"/>
|
||||||
|
<reg32 offset="0x00054" name="LANE_BIST_CONFIG"/>
|
||||||
|
<reg32 offset="0x00058" name="CLOCK"/>
|
||||||
|
<reg32 offset="0x0005C" name="MISC1"/>
|
||||||
|
<reg32 offset="0x00060" name="MISC2"/>
|
||||||
|
<reg32 offset="0x00064" name="TX0_TX1_BIST_STATUS0"/>
|
||||||
|
<reg32 offset="0x00068" name="TX0_TX1_BIST_STATUS1"/>
|
||||||
|
<reg32 offset="0x0006C" name="TX0_TX1_BIST_STATUS2"/>
|
||||||
|
<reg32 offset="0x00070" name="TX2_TX3_BIST_STATUS0"/>
|
||||||
|
<reg32 offset="0x00074" name="TX2_TX3_BIST_STATUS1"/>
|
||||||
|
<reg32 offset="0x00078" name="TX2_TX3_BIST_STATUS2"/>
|
||||||
|
<reg32 offset="0x0007C" name="PRE_MISR_STATUS0"/>
|
||||||
|
<reg32 offset="0x00080" name="PRE_MISR_STATUS1"/>
|
||||||
|
<reg32 offset="0x00084" name="PRE_MISR_STATUS2"/>
|
||||||
|
<reg32 offset="0x00088" name="PRE_MISR_STATUS3"/>
|
||||||
|
<reg32 offset="0x0008C" name="POST_MISR_STATUS0"/>
|
||||||
|
<reg32 offset="0x00090" name="POST_MISR_STATUS1"/>
|
||||||
|
<reg32 offset="0x00094" name="POST_MISR_STATUS2"/>
|
||||||
|
<reg32 offset="0x00098" name="POST_MISR_STATUS3"/>
|
||||||
|
<reg32 offset="0x0009C" name="STATUS"/>
|
||||||
|
<reg32 offset="0x000A0" name="MISC3_STATUS"/>
|
||||||
|
<reg32 offset="0x000A4" name="MISC4_STATUS"/>
|
||||||
|
<reg32 offset="0x000A8" name="DEBUG_BUS0"/>
|
||||||
|
<reg32 offset="0x000AC" name="DEBUG_BUS1"/>
|
||||||
|
<reg32 offset="0x000B0" name="DEBUG_BUS2"/>
|
||||||
|
<reg32 offset="0x000B4" name="DEBUG_BUS3"/>
|
||||||
|
<reg32 offset="0x000B8" name="PHY_REVISION_ID0"/>
|
||||||
|
<reg32 offset="0x000BC" name="PHY_REVISION_ID1"/>
|
||||||
|
<reg32 offset="0x000C0" name="PHY_REVISION_ID2"/>
|
||||||
|
<reg32 offset="0x000C4" name="PHY_REVISION_ID3"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="HDMI_PHY_QSERDES_COM" width="32">
|
||||||
|
<reg32 offset="0x00000" name="ATB_SEL1"/>
|
||||||
|
<reg32 offset="0x00004" name="ATB_SEL2"/>
|
||||||
|
<reg32 offset="0x00008" name="FREQ_UPDATE"/>
|
||||||
|
<reg32 offset="0x0000C" name="BG_TIMER"/>
|
||||||
|
<reg32 offset="0x00010" name="SSC_EN_CENTER"/>
|
||||||
|
<reg32 offset="0x00014" name="SSC_ADJ_PER1"/>
|
||||||
|
<reg32 offset="0x00018" name="SSC_ADJ_PER2"/>
|
||||||
|
<reg32 offset="0x0001C" name="SSC_PER1"/>
|
||||||
|
<reg32 offset="0x00020" name="SSC_PER2"/>
|
||||||
|
<reg32 offset="0x00024" name="SSC_STEP_SIZE1"/>
|
||||||
|
<reg32 offset="0x00028" name="SSC_STEP_SIZE2"/>
|
||||||
|
<reg32 offset="0x0002C" name="POST_DIV"/>
|
||||||
|
<reg32 offset="0x00030" name="POST_DIV_MUX"/>
|
||||||
|
<reg32 offset="0x00034" name="BIAS_EN_CLKBUFLR_EN"/>
|
||||||
|
<reg32 offset="0x00038" name="CLK_ENABLE1"/>
|
||||||
|
<reg32 offset="0x0003C" name="SYS_CLK_CTRL"/>
|
||||||
|
<reg32 offset="0x00040" name="SYSCLK_BUF_ENABLE"/>
|
||||||
|
<reg32 offset="0x00044" name="PLL_EN"/>
|
||||||
|
<reg32 offset="0x00048" name="PLL_IVCO"/>
|
||||||
|
<reg32 offset="0x0004C" name="LOCK_CMP1_MODE0"/>
|
||||||
|
<reg32 offset="0x00050" name="LOCK_CMP2_MODE0"/>
|
||||||
|
<reg32 offset="0x00054" name="LOCK_CMP3_MODE0"/>
|
||||||
|
<reg32 offset="0x00058" name="LOCK_CMP1_MODE1"/>
|
||||||
|
<reg32 offset="0x0005C" name="LOCK_CMP2_MODE1"/>
|
||||||
|
<reg32 offset="0x00060" name="LOCK_CMP3_MODE1"/>
|
||||||
|
<reg32 offset="0x00064" name="LOCK_CMP1_MODE2"/>
|
||||||
|
<reg32 offset="0x00064" name="CMN_RSVD0"/>
|
||||||
|
<reg32 offset="0x00068" name="LOCK_CMP2_MODE2"/>
|
||||||
|
<reg32 offset="0x00068" name="EP_CLOCK_DETECT_CTRL"/>
|
||||||
|
<reg32 offset="0x0006C" name="LOCK_CMP3_MODE2"/>
|
||||||
|
<reg32 offset="0x0006C" name="SYSCLK_DET_COMP_STATUS"/>
|
||||||
|
<reg32 offset="0x00070" name="BG_TRIM"/>
|
||||||
|
<reg32 offset="0x00074" name="CLK_EP_DIV"/>
|
||||||
|
<reg32 offset="0x00078" name="CP_CTRL_MODE0"/>
|
||||||
|
<reg32 offset="0x0007C" name="CP_CTRL_MODE1"/>
|
||||||
|
<reg32 offset="0x00080" name="CP_CTRL_MODE2"/>
|
||||||
|
<reg32 offset="0x00080" name="CMN_RSVD1"/>
|
||||||
|
<reg32 offset="0x00084" name="PLL_RCTRL_MODE0"/>
|
||||||
|
<reg32 offset="0x00088" name="PLL_RCTRL_MODE1"/>
|
||||||
|
<reg32 offset="0x0008C" name="PLL_RCTRL_MODE2"/>
|
||||||
|
<reg32 offset="0x0008C" name="CMN_RSVD2"/>
|
||||||
|
<reg32 offset="0x00090" name="PLL_CCTRL_MODE0"/>
|
||||||
|
<reg32 offset="0x00094" name="PLL_CCTRL_MODE1"/>
|
||||||
|
<reg32 offset="0x00098" name="PLL_CCTRL_MODE2"/>
|
||||||
|
<reg32 offset="0x00098" name="CMN_RSVD3"/>
|
||||||
|
<reg32 offset="0x0009C" name="PLL_CNTRL"/>
|
||||||
|
<reg32 offset="0x000A0" name="PHASE_SEL_CTRL"/>
|
||||||
|
<reg32 offset="0x000A4" name="PHASE_SEL_DC"/>
|
||||||
|
<reg32 offset="0x000A8" name="CORE_CLK_IN_SYNC_SEL"/>
|
||||||
|
<reg32 offset="0x000A8" name="BIAS_EN_CTRL_BY_PSM"/>
|
||||||
|
<reg32 offset="0x000AC" name="SYSCLK_EN_SEL"/>
|
||||||
|
<reg32 offset="0x000B0" name="CML_SYSCLK_SEL"/>
|
||||||
|
<reg32 offset="0x000B4" name="RESETSM_CNTRL"/>
|
||||||
|
<reg32 offset="0x000B8" name="RESETSM_CNTRL2"/>
|
||||||
|
<reg32 offset="0x000BC" name="RESTRIM_CTRL"/>
|
||||||
|
<reg32 offset="0x000C0" name="RESTRIM_CTRL2"/>
|
||||||
|
<reg32 offset="0x000C4" name="RESCODE_DIV_NUM"/>
|
||||||
|
<reg32 offset="0x000C8" name="LOCK_CMP_EN"/>
|
||||||
|
<reg32 offset="0x000CC" name="LOCK_CMP_CFG"/>
|
||||||
|
<reg32 offset="0x000D0" name="DEC_START_MODE0"/>
|
||||||
|
<reg32 offset="0x000D4" name="DEC_START_MODE1"/>
|
||||||
|
<reg32 offset="0x000D8" name="DEC_START_MODE2"/>
|
||||||
|
<reg32 offset="0x000D8" name="VCOCAL_DEADMAN_CTRL"/>
|
||||||
|
<reg32 offset="0x000DC" name="DIV_FRAC_START1_MODE0"/>
|
||||||
|
<reg32 offset="0x000E0" name="DIV_FRAC_START2_MODE0"/>
|
||||||
|
<reg32 offset="0x000E4" name="DIV_FRAC_START3_MODE0"/>
|
||||||
|
<reg32 offset="0x000E8" name="DIV_FRAC_START1_MODE1"/>
|
||||||
|
<reg32 offset="0x000EC" name="DIV_FRAC_START2_MODE1"/>
|
||||||
|
<reg32 offset="0x000F0" name="DIV_FRAC_START3_MODE1"/>
|
||||||
|
<reg32 offset="0x000F4" name="DIV_FRAC_START1_MODE2"/>
|
||||||
|
<reg32 offset="0x000F4" name="VCO_TUNE_MINVAL1"/>
|
||||||
|
<reg32 offset="0x000F8" name="DIV_FRAC_START2_MODE2"/>
|
||||||
|
<reg32 offset="0x000F8" name="VCO_TUNE_MINVAL2"/>
|
||||||
|
<reg32 offset="0x000FC" name="DIV_FRAC_START3_MODE2"/>
|
||||||
|
<reg32 offset="0x000FC" name="CMN_RSVD4"/>
|
||||||
|
<reg32 offset="0x00100" name="INTEGLOOP_INITVAL"/>
|
||||||
|
<reg32 offset="0x00104" name="INTEGLOOP_EN"/>
|
||||||
|
<reg32 offset="0x00108" name="INTEGLOOP_GAIN0_MODE0"/>
|
||||||
|
<reg32 offset="0x0010C" name="INTEGLOOP_GAIN1_MODE0"/>
|
||||||
|
<reg32 offset="0x00110" name="INTEGLOOP_GAIN0_MODE1"/>
|
||||||
|
<reg32 offset="0x00114" name="INTEGLOOP_GAIN1_MODE1"/>
|
||||||
|
<reg32 offset="0x00118" name="INTEGLOOP_GAIN0_MODE2"/>
|
||||||
|
<reg32 offset="0x00118" name="VCO_TUNE_MAXVAL1"/>
|
||||||
|
<reg32 offset="0x0011C" name="INTEGLOOP_GAIN1_MODE2"/>
|
||||||
|
<reg32 offset="0x0011C" name="VCO_TUNE_MAXVAL2"/>
|
||||||
|
<reg32 offset="0x00120" name="RES_TRIM_CONTROL2"/>
|
||||||
|
<reg32 offset="0x00124" name="VCO_TUNE_CTRL"/>
|
||||||
|
<reg32 offset="0x00128" name="VCO_TUNE_MAP"/>
|
||||||
|
<reg32 offset="0x0012C" name="VCO_TUNE1_MODE0"/>
|
||||||
|
<reg32 offset="0x00130" name="VCO_TUNE2_MODE0"/>
|
||||||
|
<reg32 offset="0x00134" name="VCO_TUNE1_MODE1"/>
|
||||||
|
<reg32 offset="0x00138" name="VCO_TUNE2_MODE1"/>
|
||||||
|
<reg32 offset="0x0013C" name="VCO_TUNE1_MODE2"/>
|
||||||
|
<reg32 offset="0x0013C" name="VCO_TUNE_INITVAL1"/>
|
||||||
|
<reg32 offset="0x00140" name="VCO_TUNE2_MODE2"/>
|
||||||
|
<reg32 offset="0x00140" name="VCO_TUNE_INITVAL2"/>
|
||||||
|
<reg32 offset="0x00144" name="VCO_TUNE_TIMER1"/>
|
||||||
|
<reg32 offset="0x00148" name="VCO_TUNE_TIMER2"/>
|
||||||
|
<reg32 offset="0x0014C" name="SAR"/>
|
||||||
|
<reg32 offset="0x00150" name="SAR_CLK"/>
|
||||||
|
<reg32 offset="0x00154" name="SAR_CODE_OUT_STATUS"/>
|
||||||
|
<reg32 offset="0x00158" name="SAR_CODE_READY_STATUS"/>
|
||||||
|
<reg32 offset="0x0015C" name="CMN_STATUS"/>
|
||||||
|
<reg32 offset="0x00160" name="RESET_SM_STATUS"/>
|
||||||
|
<reg32 offset="0x00164" name="RESTRIM_CODE_STATUS"/>
|
||||||
|
<reg32 offset="0x00168" name="PLLCAL_CODE1_STATUS"/>
|
||||||
|
<reg32 offset="0x0016C" name="PLLCAL_CODE2_STATUS"/>
|
||||||
|
<reg32 offset="0x00170" name="BG_CTRL"/>
|
||||||
|
<reg32 offset="0x00174" name="CLK_SELECT"/>
|
||||||
|
<reg32 offset="0x00178" name="HSCLK_SEL"/>
|
||||||
|
<reg32 offset="0x0017C" name="INTEGLOOP_BINCODE_STATUS"/>
|
||||||
|
<reg32 offset="0x00180" name="PLL_ANALOG"/>
|
||||||
|
<reg32 offset="0x00184" name="CORECLK_DIV"/>
|
||||||
|
<reg32 offset="0x00188" name="SW_RESET"/>
|
||||||
|
<reg32 offset="0x0018C" name="CORE_CLK_EN"/>
|
||||||
|
<reg32 offset="0x00190" name="C_READY_STATUS"/>
|
||||||
|
<reg32 offset="0x00194" name="CMN_CONFIG"/>
|
||||||
|
<reg32 offset="0x00198" name="CMN_RATE_OVERRIDE"/>
|
||||||
|
<reg32 offset="0x0019C" name="SVS_MODE_CLK_SEL"/>
|
||||||
|
<reg32 offset="0x001A0" name="DEBUG_BUS0"/>
|
||||||
|
<reg32 offset="0x001A4" name="DEBUG_BUS1"/>
|
||||||
|
<reg32 offset="0x001A8" name="DEBUG_BUS2"/>
|
||||||
|
<reg32 offset="0x001AC" name="DEBUG_BUS3"/>
|
||||||
|
<reg32 offset="0x001B0" name="DEBUG_BUS_SEL"/>
|
||||||
|
<reg32 offset="0x001B4" name="CMN_MISC1"/>
|
||||||
|
<reg32 offset="0x001B8" name="CMN_MISC2"/>
|
||||||
|
<reg32 offset="0x001BC" name="CORECLK_DIV_MODE1"/>
|
||||||
|
<reg32 offset="0x001C0" name="CORECLK_DIV_MODE2"/>
|
||||||
|
<reg32 offset="0x001C4" name="CMN_RSVD5"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
|
||||||
|
<domain name="HDMI_PHY_QSERDES_TX_LX" width="32">
|
||||||
|
<reg32 offset="0x00000" name="BIST_MODE_LANENO"/>
|
||||||
|
<reg32 offset="0x00004" name="BIST_INVERT"/>
|
||||||
|
<reg32 offset="0x00008" name="CLKBUF_ENABLE"/>
|
||||||
|
<reg32 offset="0x0000C" name="CMN_CONTROL_ONE"/>
|
||||||
|
<reg32 offset="0x00010" name="CMN_CONTROL_TWO"/>
|
||||||
|
<reg32 offset="0x00014" name="CMN_CONTROL_THREE"/>
|
||||||
|
<reg32 offset="0x00018" name="TX_EMP_POST1_LVL"/>
|
||||||
|
<reg32 offset="0x0001C" name="TX_POST2_EMPH"/>
|
||||||
|
<reg32 offset="0x00020" name="TX_BOOST_LVL_UP_DN"/>
|
||||||
|
<reg32 offset="0x00024" name="HP_PD_ENABLES"/>
|
||||||
|
<reg32 offset="0x00028" name="TX_IDLE_LVL_LARGE_AMP"/>
|
||||||
|
<reg32 offset="0x0002C" name="TX_DRV_LVL"/>
|
||||||
|
<reg32 offset="0x00030" name="TX_DRV_LVL_OFFSET"/>
|
||||||
|
<reg32 offset="0x00034" name="RESET_TSYNC_EN"/>
|
||||||
|
<reg32 offset="0x00038" name="PRE_STALL_LDO_BOOST_EN"/>
|
||||||
|
<reg32 offset="0x0003C" name="TX_BAND"/>
|
||||||
|
<reg32 offset="0x00040" name="SLEW_CNTL"/>
|
||||||
|
<reg32 offset="0x00044" name="INTERFACE_SELECT"/>
|
||||||
|
<reg32 offset="0x00048" name="LPB_EN"/>
|
||||||
|
<reg32 offset="0x0004C" name="RES_CODE_LANE_TX"/>
|
||||||
|
<reg32 offset="0x00050" name="RES_CODE_LANE_RX"/>
|
||||||
|
<reg32 offset="0x00054" name="RES_CODE_LANE_OFFSET"/>
|
||||||
|
<reg32 offset="0x00058" name="PERL_LENGTH1"/>
|
||||||
|
<reg32 offset="0x0005C" name="PERL_LENGTH2"/>
|
||||||
|
<reg32 offset="0x00060" name="SERDES_BYP_EN_OUT"/>
|
||||||
|
<reg32 offset="0x00064" name="DEBUG_BUS_SEL"/>
|
||||||
|
<reg32 offset="0x00068" name="HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN"/>
|
||||||
|
<reg32 offset="0x0006C" name="TX_POL_INV"/>
|
||||||
|
<reg32 offset="0x00070" name="PARRATE_REC_DETECT_IDLE_EN"/>
|
||||||
|
<reg32 offset="0x00074" name="BIST_PATTERN1"/>
|
||||||
|
<reg32 offset="0x00078" name="BIST_PATTERN2"/>
|
||||||
|
<reg32 offset="0x0007C" name="BIST_PATTERN3"/>
|
||||||
|
<reg32 offset="0x00080" name="BIST_PATTERN4"/>
|
||||||
|
<reg32 offset="0x00084" name="BIST_PATTERN5"/>
|
||||||
|
<reg32 offset="0x00088" name="BIST_PATTERN6"/>
|
||||||
|
<reg32 offset="0x0008C" name="BIST_PATTERN7"/>
|
||||||
|
<reg32 offset="0x00090" name="BIST_PATTERN8"/>
|
||||||
|
<reg32 offset="0x00094" name="LANE_MODE"/>
|
||||||
|
<reg32 offset="0x00098" name="IDAC_CAL_LANE_MODE"/>
|
||||||
|
<reg32 offset="0x0009C" name="IDAC_CAL_LANE_MODE_CONFIGURATION"/>
|
||||||
|
<reg32 offset="0x000A0" name="ATB_SEL1"/>
|
||||||
|
<reg32 offset="0x000A4" name="ATB_SEL2"/>
|
||||||
|
<reg32 offset="0x000A8" name="RCV_DETECT_LVL"/>
|
||||||
|
<reg32 offset="0x000AC" name="RCV_DETECT_LVL_2"/>
|
||||||
|
<reg32 offset="0x000B0" name="PRBS_SEED1"/>
|
||||||
|
<reg32 offset="0x000B4" name="PRBS_SEED2"/>
|
||||||
|
<reg32 offset="0x000B8" name="PRBS_SEED3"/>
|
||||||
|
<reg32 offset="0x000BC" name="PRBS_SEED4"/>
|
||||||
|
<reg32 offset="0x000C0" name="RESET_GEN"/>
|
||||||
|
<reg32 offset="0x000C4" name="RESET_GEN_MUXES"/>
|
||||||
|
<reg32 offset="0x000C8" name="TRAN_DRVR_EMP_EN"/>
|
||||||
|
<reg32 offset="0x000CC" name="TX_INTERFACE_MODE"/>
|
||||||
|
<reg32 offset="0x000D0" name="PWM_CTRL"/>
|
||||||
|
<reg32 offset="0x000D4" name="PWM_ENCODED_OR_DATA"/>
|
||||||
|
<reg32 offset="0x000D8" name="PWM_GEAR_1_DIVIDER_BAND2"/>
|
||||||
|
<reg32 offset="0x000DC" name="PWM_GEAR_2_DIVIDER_BAND2"/>
|
||||||
|
<reg32 offset="0x000E0" name="PWM_GEAR_3_DIVIDER_BAND2"/>
|
||||||
|
<reg32 offset="0x000E4" name="PWM_GEAR_4_DIVIDER_BAND2"/>
|
||||||
|
<reg32 offset="0x000E8" name="PWM_GEAR_1_DIVIDER_BAND0_1"/>
|
||||||
|
<reg32 offset="0x000EC" name="PWM_GEAR_2_DIVIDER_BAND0_1"/>
|
||||||
|
<reg32 offset="0x000F0" name="PWM_GEAR_3_DIVIDER_BAND0_1"/>
|
||||||
|
<reg32 offset="0x000F4" name="PWM_GEAR_4_DIVIDER_BAND0_1"/>
|
||||||
|
<reg32 offset="0x000F8" name="VMODE_CTRL1"/>
|
||||||
|
<reg32 offset="0x000FC" name="VMODE_CTRL2"/>
|
||||||
|
<reg32 offset="0x00100" name="TX_ALOG_INTF_OBSV_CNTL"/>
|
||||||
|
<reg32 offset="0x00104" name="BIST_STATUS"/>
|
||||||
|
<reg32 offset="0x00108" name="BIST_ERROR_COUNT1"/>
|
||||||
|
<reg32 offset="0x0010C" name="BIST_ERROR_COUNT2"/>
|
||||||
|
<reg32 offset="0x00110" name="TX_ALOG_INTF_OBSV"/>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,18 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
|
||||||
|
<domain name="QFPROM" width="32">
|
||||||
|
<doc>
|
||||||
|
seems to be something external to display block, for finding
|
||||||
|
what features are enabled/supported?
|
||||||
|
</doc>
|
||||||
|
<reg32 offset="0x0238" name="CONFIG_ROW0_LSB">
|
||||||
|
<bitfield name="HDMI_DISABLE" pos="21" type="boolean"/>
|
||||||
|
<bitfield name="HDCP_DISABLE" pos="22" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,480 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
<import file="mdp/mdp_common.xml"/>
|
||||||
|
|
||||||
|
<domain name="MDP4" width="32">
|
||||||
|
<enum name="mdp4_pipe">
|
||||||
|
<brief>pipe names, index into PIPE[]</brief>
|
||||||
|
<value name="VG1" value="0"/>
|
||||||
|
<value name="VG2" value="1"/>
|
||||||
|
<value name="RGB1" value="2"/>
|
||||||
|
<value name="RGB2" value="3"/>
|
||||||
|
<value name="RGB3" value="4"/>
|
||||||
|
<value name="VG3" value="5"/>
|
||||||
|
<value name="VG4" value="6"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp4_mixer">
|
||||||
|
<value name="MIXER0" value="0"/>
|
||||||
|
<value name="MIXER1" value="1"/>
|
||||||
|
<value name="MIXER2" value="2"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp4_intf">
|
||||||
|
<!--
|
||||||
|
A bit confusing the enums for interface selection:
|
||||||
|
enum {
|
||||||
|
LCDC_RGB_INTF, /* 0 */
|
||||||
|
DTV_INTF = LCDC_RGB_INTF, /* 0 */
|
||||||
|
MDDI_LCDC_INTF, /* 1 */
|
||||||
|
MDDI_INTF, /* 2 */
|
||||||
|
EBI2_INTF, /* 3 */
|
||||||
|
TV_INTF = EBI2_INTF, /* 3 */
|
||||||
|
DSI_VIDEO_INTF,
|
||||||
|
DSI_CMD_INTF
|
||||||
|
};
|
||||||
|
there is some overlap, and not all the values end up getting
|
||||||
|
written to hw (mdp4_display_intf_sel() remaps the last two
|
||||||
|
values to MDDI_LCDC_INTF/MDDI_INTF with extra bits set).. so
|
||||||
|
taking some liberties in guessing the actual meanings/names:
|
||||||
|
-->
|
||||||
|
<value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) -->
|
||||||
|
<value name="INTF_DSI_VIDEO" value="1"/>
|
||||||
|
<value name="INTF_DSI_CMD" value="2"/>
|
||||||
|
<value name="INTF_EBI2_TV" value="3"/> <!-- EBI2 or TV (external) -->
|
||||||
|
</enum>
|
||||||
|
<enum name="mdp4_cursor_format">
|
||||||
|
<value name="CURSOR_ARGB" value="1"/>
|
||||||
|
<value name="CURSOR_XRGB" value="2"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="mdp4_frame_format">
|
||||||
|
<value name="FRAME_LINEAR" value="0"/>
|
||||||
|
<value name="FRAME_TILE_ARGB_4X4" value="1"/>
|
||||||
|
<value name="FRAME_TILE_YCBCR_420" value="2"/>
|
||||||
|
</enum>
|
||||||
|
<enum name="mdp4_scale_unit">
|
||||||
|
<value name="SCALE_FIR" value="0"/>
|
||||||
|
<value name="SCALE_MN_PHASE" value="1"/>
|
||||||
|
<value name="SCALE_PIXEL_RPT" value="2"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<bitset name="mdp4_layermixer_in_cfg" inline="yes">
|
||||||
|
<brief>appears to map pipe to mixer stage</brief>
|
||||||
|
<bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="PIPE0_MIXER1" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="PIPE1" low="4" high="6" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="PIPE1_MIXER1" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="PIPE2" low="8" high="10" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="PIPE2_MIXER1" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="PIPE3" low="12" high="14" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="PIPE3_MIXER1" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="PIPE4" low="16" high="18" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="PIPE4_MIXER1" pos="19" type="boolean"/>
|
||||||
|
<bitfield name="PIPE5" low="20" high="22" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="PIPE5_MIXER1" pos="23" type="boolean"/>
|
||||||
|
<bitfield name="PIPE6" low="24" high="26" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="PIPE6_MIXER1" pos="27" type="boolean"/>
|
||||||
|
<bitfield name="PIPE7" low="28" high="30" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="PIPE7_MIXER1" pos="31" type="boolean"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="MDP4_IRQ">
|
||||||
|
<bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="OVERLAY1_DONE" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="DMA_S_DONE" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="DMA_E_DONE" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="DMA_P_DONE" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="VG1_HISTOGRAM" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="VG2_HISTOGRAM" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="PRIMARY_VSYNC" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="PRIMARY_INTF_UDERRUN" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="EXTERNAL_VSYNC" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="EXTERNAL_INTF_UDERRUN" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="PRIMARY_RDPTR" pos="11" type="boolean"/> <!-- read pointer -->
|
||||||
|
<bitfield name="DMA_P_HISTOGRAM" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="DMA_S_HISTOGRAM" pos="26" type="boolean"/>
|
||||||
|
<bitfield name="OVERLAY2_DONE" pos="30" type="boolean"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<group name="mdp4_csc">
|
||||||
|
<array offset="0x400" name="MV" length="9" stride="4">
|
||||||
|
<reg32 offset="0" name="VAL"/>
|
||||||
|
</array>
|
||||||
|
<array offset="0x500" name="PRE_BV" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="VAL"/>
|
||||||
|
</array>
|
||||||
|
<array offset="0x580" name="POST_BV" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="VAL"/>
|
||||||
|
</array>
|
||||||
|
<array offset="0x600" name="PRE_LV" length="6" stride="4">
|
||||||
|
<reg32 offset="0" name="VAL"/>
|
||||||
|
</array>
|
||||||
|
<array offset="0x680" name="POST_LV" length="6" stride="4">
|
||||||
|
<reg32 offset="0" name="VAL"/>
|
||||||
|
</array>
|
||||||
|
</group>
|
||||||
|
|
||||||
|
<reg32 offset="0x00000" name="VERSION">
|
||||||
|
<!--
|
||||||
|
from mdp_probe() we can see minor rev starts at 16.. assume
|
||||||
|
major is above that.. not sure the rest of bits but doesn't
|
||||||
|
really seem to matter
|
||||||
|
-->
|
||||||
|
<bitfield name="MINOR" low="16" high="23" type="uint"/>
|
||||||
|
<bitfield name="MAJOR" low="24" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00004" name="OVLP0_KICK"/>
|
||||||
|
<reg32 offset="0x00008" name="OVLP1_KICK"/>
|
||||||
|
<reg32 offset="0x000d0" name="OVLP2_KICK"/>
|
||||||
|
<reg32 offset="0x0000c" name="DMA_P_KICK"/>
|
||||||
|
<reg32 offset="0x00010" name="DMA_S_KICK"/>
|
||||||
|
<reg32 offset="0x00014" name="DMA_E_KICK"/>
|
||||||
|
<reg32 offset="0x00018" name="DISP_STATUS"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x00038" name="DISP_INTF_SEL">
|
||||||
|
<bitfield name="PRIM" low="0" high="1" type="mdp4_intf"/>
|
||||||
|
<bitfield name="SEC" low="2" high="3" type="mdp4_intf"/>
|
||||||
|
<bitfield name="EXT" low="4" high="5" type="mdp4_intf"/>
|
||||||
|
<bitfield name="DSI_VIDEO" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="DSI_CMD" pos="7" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0003c" name="RESET_STATUS"/> <!-- only mdp4 >v2.1 -->
|
||||||
|
<reg32 offset="0x0004c" name="READ_CNFG"/> <!-- something about # of pending requests.. -->
|
||||||
|
<reg32 offset="0x00050" name="INTR_ENABLE" type="MDP4_IRQ"/>
|
||||||
|
<reg32 offset="0x00054" name="INTR_STATUS" type="MDP4_IRQ"/>
|
||||||
|
<reg32 offset="0x00058" name="INTR_CLEAR" type="MDP4_IRQ"/>
|
||||||
|
<reg32 offset="0x00060" name="EBI2_LCD0"/>
|
||||||
|
<reg32 offset="0x00064" name="EBI2_LCD1"/>
|
||||||
|
<reg32 offset="0x00070" name="PORTMAP_MODE"/>
|
||||||
|
|
||||||
|
<!-- mdp chip-select controller: -->
|
||||||
|
<reg32 offset="0x000c0" name="CS_CONTROLLER0"/>
|
||||||
|
<reg32 offset="0x000c4" name="CS_CONTROLLER1"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x100f0" name="LAYERMIXER2_IN_CFG" type="mdp4_layermixer_in_cfg"/>
|
||||||
|
<reg32 offset="0x100fc" name="LAYERMIXER_IN_CFG_UPDATE_METHOD"/>
|
||||||
|
<reg32 offset="0x10100" name="LAYERMIXER_IN_CFG" type="mdp4_layermixer_in_cfg"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x30050" name="VG2_SRC_FORMAT"/>
|
||||||
|
<reg32 offset="0x31008" name="VG2_CONST_COLOR"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x18000" name="OVERLAY_FLUSH">
|
||||||
|
<bitfield name="OVLP0" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="OVLP1" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="VG1" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="VG2" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="RGB1" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="RGB2" pos="5" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<array offsets="0x10000,0x18000,0x88000" name="OVLP" length="3" stride="0x8000">
|
||||||
|
<reg32 offset="0x0004" name="CFG"/>
|
||||||
|
<reg32 offset="0x0008" name="SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x000c" name="BASE"/>
|
||||||
|
<reg32 offset="0x0010" name="STRIDE" type="uint"/>
|
||||||
|
<reg32 offset="0x0014" name="OPMODE"/>
|
||||||
|
|
||||||
|
<array offsets="0x0104,0x0124,0x0144,0x0160" name="STAGE" length="4" stride="0x1c">
|
||||||
|
<reg32 offset="0x00" name="OP">
|
||||||
|
<bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
|
||||||
|
<bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="BG_ALPHA" low="4" high="5" type="mdp_alpha_type"/>
|
||||||
|
<bitfield name="BG_INV_ALPHA" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="BG_MOD_ALPHA" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="FG_TRANSP" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="BG_TRANSP" pos="9" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x04" name="FG_ALPHA"/>
|
||||||
|
<reg32 offset="0x08" name="BG_ALPHA"/>
|
||||||
|
<reg32 offset="0x0c" name="TRANSP_LOW0"/>
|
||||||
|
<reg32 offset="0x10" name="TRANSP_LOW1"/>
|
||||||
|
<reg32 offset="0x14" name="TRANSP_HIGH0"/>
|
||||||
|
<reg32 offset="0x18" name="TRANSP_HIGH1"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<array offsets="0x1004,0x1404,0x1804,0x1b84" name="STAGE_CO3" length="4" stride="4">
|
||||||
|
<reg32 offset="0" name="SEL">
|
||||||
|
<bitfield name="FG_ALPHA" pos="0" type="boolean"/> <!-- otherwise bg alpha -->
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<reg32 offset="0x0180" name="TRANSP_LOW0"/>
|
||||||
|
<reg32 offset="0x0184" name="TRANSP_LOW1"/>
|
||||||
|
<reg32 offset="0x0188" name="TRANSP_HIGH0"/>
|
||||||
|
<reg32 offset="0x018c" name="TRANSP_HIGH1"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x0200" name="CSC_CONFIG"/>
|
||||||
|
|
||||||
|
<array offset="0x2000" name="CSC" length="1" stride="0x700">
|
||||||
|
<use-group name="mdp4_csc"/>
|
||||||
|
</array>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<enum name="mdp4_dma">
|
||||||
|
<value name="DMA_P" value="0"/>
|
||||||
|
<value name="DMA_S" value="1"/>
|
||||||
|
<value name="DMA_E" value="2"/>
|
||||||
|
</enum>
|
||||||
|
<reg32 offset="0x90070" name="DMA_P_OP_MODE"/>
|
||||||
|
<array offset="0x94800" name="LUTN" length="2" stride="0x400">
|
||||||
|
<array offset="0" name="LUT" length="0x100" stride="4">
|
||||||
|
<reg32 offset="0" name="VAL"/>
|
||||||
|
</array>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0xa0028" name="DMA_S_OP_MODE"/>
|
||||||
|
<!-- I guess if DMA_S has an OP_MODE, it must have a LUT too.. -->
|
||||||
|
<reg32 offset="0xb0070" name="DMA_E_QUANT" length="3" stride="4"/>
|
||||||
|
<array offsets="0x90000,0xa0000,0xb0000" name="DMA" length="3" stride="0x10000" index="mdp4_dma">
|
||||||
|
<reg32 offset="0x0000" name="CONFIG">
|
||||||
|
<bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
|
||||||
|
<bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
|
||||||
|
<bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
|
||||||
|
<bitfield name="PACK_ALIGN_MSB" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="PACK" low="8" high="15"/>
|
||||||
|
<!-- bit 24 is DITHER_EN on DMA_P, DEFLKR_EN on DMA_E -->
|
||||||
|
<bitfield name="DEFLKR_EN" pos="24" type="boolean"/>
|
||||||
|
<bitfield name="DITHER_EN" pos="24" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0004" name="SRC_SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x0008" name="SRC_BASE"/>
|
||||||
|
<reg32 offset="0x000c" name="SRC_STRIDE" type="uint"/>
|
||||||
|
<reg32 offset="0x0010" name="DST_SIZE" type="reg_wh"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x0044" name="CURSOR_SIZE">
|
||||||
|
<!-- seems the limit is 64x64: -->
|
||||||
|
<bitfield name="WIDTH" low="0" high="6" type="uint"/>
|
||||||
|
<bitfield name="HEIGHT" low="16" high="22" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0048" name="CURSOR_BASE"/>
|
||||||
|
<reg32 offset="0x004c" name="CURSOR_POS">
|
||||||
|
<bitfield name="X" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="Y" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0060" name="CURSOR_BLEND_CONFIG">
|
||||||
|
<bitfield name="CURSOR_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="FORMAT" low="1" high="2" type="mdp4_cursor_format"/>
|
||||||
|
<bitfield name="TRANSP_EN" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0064" name="CURSOR_BLEND_PARAM"/>
|
||||||
|
<reg32 offset="0x0068" name="BLEND_TRANS_LOW"/>
|
||||||
|
<reg32 offset="0x006c" name="BLEND_TRANS_HIGH"/>
|
||||||
|
|
||||||
|
<reg32 offset="0x1004" name="FETCH_CONFIG"/>
|
||||||
|
<array offset="0x3000" name="CSC" length="1" stride="0x700">
|
||||||
|
<use-group name="mdp4_csc"/>
|
||||||
|
</array>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<!--
|
||||||
|
TODO length should be 7, but that would collide w/ OVLP2..!?!
|
||||||
|
this register map is a bit strange..
|
||||||
|
-->
|
||||||
|
<array offset="0x20000" name="PIPE" length="6" stride="0x10000" index="mdp4_pipe">
|
||||||
|
<reg32 offset="0x0000" name="SRC_SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x0004" name="SRC_XY" type="reg_xy"/>
|
||||||
|
<reg32 offset="0x0008" name="DST_SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x000c" name="DST_XY" type="reg_xy"/>
|
||||||
|
<reg32 offset="0x0010" name="SRCP0_BASE"/>
|
||||||
|
<reg32 offset="0x0014" name="SRCP1_BASE"/>
|
||||||
|
<reg32 offset="0x0018" name="SRCP2_BASE"/>
|
||||||
|
<reg32 offset="0x001c" name="SRCP3_BASE"/>
|
||||||
|
<reg32 offset="0x0040" name="SRC_STRIDE_A">
|
||||||
|
<bitfield name="P0" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="P1" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0044" name="SRC_STRIDE_B">
|
||||||
|
<bitfield name="P2" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="P3" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0048" name="SSTILE_FRAME_SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x0050" name="SRC_FORMAT">
|
||||||
|
<bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
|
||||||
|
<bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
|
||||||
|
<bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
|
||||||
|
<bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
|
||||||
|
<bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="CPP" low="9" high="10" type="uint">
|
||||||
|
<brief>8bit characters per pixel minus 1</brief>
|
||||||
|
</bitfield>
|
||||||
|
<bitfield name="ROTATED_90" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="UNPACK_COUNT" low="13" high="14" type="uint"/>
|
||||||
|
<bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="FETCH_PLANES" low="19" high="20" type="uint"/>
|
||||||
|
<bitfield name="SOLID_FILL" pos="22" type="boolean"/>
|
||||||
|
<bitfield name="CHROMA_SAMP" low="26" high="27" type="mdp_chroma_samp_type"/>
|
||||||
|
<bitfield name="FRAME_FORMAT" low="29" high="30" type="mdp4_frame_format"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0054" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
|
||||||
|
<reg32 offset="0x0058" name="OP_MODE">
|
||||||
|
<bitfield name="SCALEX_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="SCALEY_EN" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="SCALEX_UNIT_SEL" low="2" high="3" type="mdp4_scale_unit"/>
|
||||||
|
<bitfield name="SCALEY_UNIT_SEL" low="4" high="5" type="mdp4_scale_unit"/>
|
||||||
|
<bitfield name="SRC_YCBCR" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="DST_YCBCR" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="CSC_EN" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="FLIP_LR" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="FLIP_UD" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="DITHER_EN" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="IGC_LUT_EN" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="DEINT_EN" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="DEINT_ODD_REF" pos="19" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x005c" name="PHASEX_STEP"/>
|
||||||
|
<reg32 offset="0x0060" name="PHASEY_STEP"/>
|
||||||
|
<reg32 offset="0x1004" name="FETCH_CONFIG"/>
|
||||||
|
<reg32 offset="0x1008" name="SOLID_COLOR"/>
|
||||||
|
|
||||||
|
<array offset="0x4000" name="CSC" length="1" stride="0x700">
|
||||||
|
<use-group name="mdp4_csc"/>
|
||||||
|
</array>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<!--
|
||||||
|
ENCODERS
|
||||||
|
LCDC and DSI seem the same, DTV is just slightly different..
|
||||||
|
-->
|
||||||
|
|
||||||
|
<bitset name="mdp4_ctrl_polarity" inline="yes">
|
||||||
|
<!-- not entirely sure if these bits mean hi or low.. -->
|
||||||
|
<bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="mdp4_active_hctl" inline="yes">
|
||||||
|
<bitfield name="START" low="0" high="14" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="30" type="uint"/>
|
||||||
|
<bitfield name="ACTIVE_START_X" pos="31" type="boolean"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="mdp4_display_hctl" inline="yes">
|
||||||
|
<bitfield name="START" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="31" type="uint"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="mdp4_hsync_ctrl" inline="yes">
|
||||||
|
<bitfield name="PULSEW" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="PERIOD" low="16" high="31" type="uint"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="mdp4_underflow_clr" inline="yes">
|
||||||
|
<bitfield name="COLOR" low="0" high="23"/>
|
||||||
|
<bitfield name="ENABLE_RECOVERY" pos="31" type="boolean"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<!-- offset is 0xe0000 on !mdp4.. -->
|
||||||
|
<array offset="0xc0000" name="LCDC" length="1" stride="0x1000">
|
||||||
|
<reg32 offset="0x0000" name="ENABLE"/>
|
||||||
|
<reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
|
||||||
|
<reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
|
||||||
|
<reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
|
||||||
|
<reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
|
||||||
|
<reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
|
||||||
|
<reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
|
||||||
|
<reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
|
||||||
|
<reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
|
||||||
|
<reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
|
||||||
|
<reg32 offset="0x0028" name="BORDER_CLR"/>
|
||||||
|
<reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
|
||||||
|
<reg32 offset="0x0030" name="HSYNC_SKEW"/>
|
||||||
|
<reg32 offset="0x0034" name="TEST_CNTL"/>
|
||||||
|
<reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<reg32 offset="0xc2000" name="LCDC_LVDS_INTF_CTL">
|
||||||
|
<bitfield name="MODE_SEL" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="RGB_OUT" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="CH_SWAP" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="CH1_RES_BIT" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="CH2_RES_BIT" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="ENABLE" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="CH1_DATA_LANE0_EN" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="CH1_DATA_LANE1_EN" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="CH1_DATA_LANE2_EN" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="CH1_DATA_LANE3_EN" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="CH2_DATA_LANE0_EN" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="CH2_DATA_LANE1_EN" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="CH2_DATA_LANE2_EN" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="CH2_DATA_LANE3_EN" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="CH1_CLK_LANE_EN" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="CH2_CLK_LANE_EN" pos="17" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<array offset="0xc2014" name="LCDC_LVDS_MUX_CTL" length="4" stride="0x8">
|
||||||
|
<reg32 offset="0x0" name="3_TO_0">
|
||||||
|
<bitfield name="BIT0" low="0" high="7"/>
|
||||||
|
<bitfield name="BIT1" low="8" high="15"/>
|
||||||
|
<bitfield name="BIT2" low="16" high="23"/>
|
||||||
|
<bitfield name="BIT3" low="24" high="31"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x4" name="6_TO_4">
|
||||||
|
<bitfield name="BIT4" low="0" high="7"/>
|
||||||
|
<bitfield name="BIT5" low="8" high="15"/>
|
||||||
|
<bitfield name="BIT6" low="16" high="23"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<reg32 offset="0xc2034" name="LCDC_LVDS_PHY_RESET"/>
|
||||||
|
|
||||||
|
<reg32 offset="0xc3000" name="LVDS_PHY_PLL_CTRL_0"/>
|
||||||
|
<reg32 offset="0xc3004" name="LVDS_PHY_PLL_CTRL_1"/>
|
||||||
|
<reg32 offset="0xc3008" name="LVDS_PHY_PLL_CTRL_2"/>
|
||||||
|
<reg32 offset="0xc300c" name="LVDS_PHY_PLL_CTRL_3"/>
|
||||||
|
<reg32 offset="0xc3014" name="LVDS_PHY_PLL_CTRL_5"/>
|
||||||
|
<reg32 offset="0xc3018" name="LVDS_PHY_PLL_CTRL_6"/>
|
||||||
|
<reg32 offset="0xc301c" name="LVDS_PHY_PLL_CTRL_7"/>
|
||||||
|
<reg32 offset="0xc3020" name="LVDS_PHY_PLL_CTRL_8"/>
|
||||||
|
<reg32 offset="0xc3024" name="LVDS_PHY_PLL_CTRL_9"/>
|
||||||
|
<reg32 offset="0xc3080" name="LVDS_PHY_PLL_LOCKED"/>
|
||||||
|
<reg32 offset="0xc3108" name="LVDS_PHY_CFG2"/>
|
||||||
|
|
||||||
|
<reg32 offset="0xc3100" name="LVDS_PHY_CFG0">
|
||||||
|
<bitfield name="SERIALIZATION_ENBLE" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="CHANNEL0" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="CHANNEL1" pos="7" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<array offset="0xd0000" name="DTV" length="1" stride="0x1000">
|
||||||
|
<reg32 offset="0x0000" name="ENABLE"/>
|
||||||
|
<reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
|
||||||
|
<reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
|
||||||
|
<reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
|
||||||
|
<reg32 offset="0x0018" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
|
||||||
|
<reg32 offset="0x001c" name="DISPLAY_VSTART" type="uint"/>
|
||||||
|
<reg32 offset="0x0020" name="DISPLAY_VEND" type="uint"/>
|
||||||
|
<reg32 offset="0x002c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
|
||||||
|
<reg32 offset="0x0030" name="ACTIVE_VSTART" type="uint"/>
|
||||||
|
<reg32 offset="0x0038" name="ACTIVE_VEND" type="uint"/>
|
||||||
|
<reg32 offset="0x0040" name="BORDER_CLR"/>
|
||||||
|
<reg32 offset="0x0044" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
|
||||||
|
<reg32 offset="0x0048" name="HSYNC_SKEW"/>
|
||||||
|
<reg32 offset="0x004c" name="TEST_CNTL"/>
|
||||||
|
<reg32 offset="0x0050" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<array offset="0xe0000" name="DSI" length="1" stride="0x1000">
|
||||||
|
<reg32 offset="0x0000" name="ENABLE"/>
|
||||||
|
<reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
|
||||||
|
<reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
|
||||||
|
<reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
|
||||||
|
<reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
|
||||||
|
<reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
|
||||||
|
<reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
|
||||||
|
<reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
|
||||||
|
<reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
|
||||||
|
<reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
|
||||||
|
<reg32 offset="0x0028" name="BORDER_CLR"/>
|
||||||
|
<reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
|
||||||
|
<reg32 offset="0x0030" name="HSYNC_SKEW"/>
|
||||||
|
<reg32 offset="0x0034" name="TEST_CNTL"/>
|
||||||
|
<reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
|
||||||
|
</array>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,804 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
<import file="mdp/mdp_common.xml"/>
|
||||||
|
|
||||||
|
<!-- where does this belong? -->
|
||||||
|
<domain name="VBIF" width="32">
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="MDSS" width="32">
|
||||||
|
<reg32 offset="0x00000" name="HW_VERSION">
|
||||||
|
<bitfield name="STEP" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="MINOR" low="16" high="27" type="uint"/>
|
||||||
|
<bitfield name="MAJOR" low="28" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00010" name="HW_INTR_STATUS">
|
||||||
|
<bitfield name="INTR_MDP" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="INTR_DSI0" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="INTR_DSI1" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="INTR_HDMI" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="INTR_EDP" pos="12" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
<domain name="MDP5" width="32">
|
||||||
|
|
||||||
|
<enum name="mdp5_intf_type">
|
||||||
|
<value name="INTF_DISABLED" value="0x0"/>
|
||||||
|
<value name="INTF_DSI" value="0x1"/>
|
||||||
|
<value name="INTF_HDMI" value="0x3"/>
|
||||||
|
<value name="INTF_LCDC" value="0x5"/>
|
||||||
|
<value name="INTF_eDP" value="0x9"/>
|
||||||
|
<value name="INTF_VIRTUAL" value="0x64"/>
|
||||||
|
<!-- non-display interfaces are listed below: -->
|
||||||
|
<value name="INTF_WB" value="0x65"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_intfnum">
|
||||||
|
<value name="NO_INTF" value="0"/>
|
||||||
|
<value name="INTF0" value="1"/>
|
||||||
|
<value name="INTF1" value="2"/>
|
||||||
|
<value name="INTF2" value="3"/>
|
||||||
|
<value name="INTF3" value="4"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_pipe">
|
||||||
|
<value name="SSPP_NONE" value="0"/>
|
||||||
|
<value name="SSPP_VIG0" value="1"/>
|
||||||
|
<value name="SSPP_VIG1" value="2"/>
|
||||||
|
<value name="SSPP_VIG2" value="3"/>
|
||||||
|
<value name="SSPP_RGB0" value="4"/>
|
||||||
|
<value name="SSPP_RGB1" value="5"/>
|
||||||
|
<value name="SSPP_RGB2" value="6"/>
|
||||||
|
<value name="SSPP_DMA0" value="7"/>
|
||||||
|
<value name="SSPP_DMA1" value="8"/>
|
||||||
|
<value name="SSPP_VIG3" value="9"/>
|
||||||
|
<value name="SSPP_RGB3" value="10"/>
|
||||||
|
<value name="SSPP_CURSOR0" value="11"/>
|
||||||
|
<value name="SSPP_CURSOR1" value="12"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_format">
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_ctl_mode">
|
||||||
|
<value name="MODE_NONE" value="0"/>
|
||||||
|
<value name="MODE_WB_0_BLOCK" value="1"/>
|
||||||
|
<value name="MODE_WB_1_BLOCK" value="2"/>
|
||||||
|
<value name="MODE_WB_0_LINE" value="3"/>
|
||||||
|
<value name="MODE_WB_1_LINE" value="4"/>
|
||||||
|
<value name="MODE_WB_2_LINE" value="5"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_pack_3d">
|
||||||
|
<value name="PACK_3D_FRAME_INT" value="0"/>
|
||||||
|
<value name="PACK_3D_H_ROW_INT" value="1"/>
|
||||||
|
<value name="PACK_3D_V_ROW_INT" value="2"/>
|
||||||
|
<value name="PACK_3D_COL_INT" value="3"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_scale_filter">
|
||||||
|
<value name="SCALE_FILTER_NEAREST" value="0"/>
|
||||||
|
<value name="SCALE_FILTER_BIL" value="1"/>
|
||||||
|
<value name="SCALE_FILTER_PCMN" value="2"/>
|
||||||
|
<value name="SCALE_FILTER_CA" value="3"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_pipe_bwc">
|
||||||
|
<value name="BWC_LOSSLESS" value="0"/>
|
||||||
|
<value name="BWC_Q_HIGH" value="1"/>
|
||||||
|
<value name="BWC_Q_MED" value="2"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_cursor_format">
|
||||||
|
<value name="CURSOR_FMT_ARGB8888" value="0"/>
|
||||||
|
<value name="CURSOR_FMT_ARGB1555" value="2"/>
|
||||||
|
<value name="CURSOR_FMT_ARGB4444" value="4"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_cursor_alpha">
|
||||||
|
<value name="CURSOR_ALPHA_CONST" value="0"/>
|
||||||
|
<value name="CURSOR_ALPHA_PER_PIXEL" value="2"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<bitset name="MDP5_IRQ">
|
||||||
|
<bitfield name="WB_0_DONE" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="WB_1_DONE" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="WB_2_DONE" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_0_DONE" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_1_DONE" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_2_DONE" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_3_DONE" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_0_RD_PTR" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_1_RD_PTR" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_2_RD_PTR" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_3_RD_PTR" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_0_WR_PTR" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_1_WR_PTR" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_2_WR_PTR" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_3_WR_PTR" pos="19" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_0_AUTO_REF" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_1_AUTO_REF" pos="21" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_2_AUTO_REF" pos="22" type="boolean"/>
|
||||||
|
<bitfield name="PING_PONG_3_AUTO_REF" pos="23" type="boolean"/>
|
||||||
|
<bitfield name="INTF0_UNDER_RUN" pos="24" type="boolean"/>
|
||||||
|
<bitfield name="INTF0_VSYNC" pos="25" type="boolean"/>
|
||||||
|
<bitfield name="INTF1_UNDER_RUN" pos="26" type="boolean"/>
|
||||||
|
<bitfield name="INTF1_VSYNC" pos="27" type="boolean"/>
|
||||||
|
<bitfield name="INTF2_UNDER_RUN" pos="28" type="boolean"/>
|
||||||
|
<bitfield name="INTF2_VSYNC" pos="29" type="boolean"/>
|
||||||
|
<bitfield name="INTF3_UNDER_RUN" pos="30" type="boolean"/>
|
||||||
|
<bitfield name="INTF3_VSYNC" pos="31" type="boolean"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="mdp5_smp_alloc" inline="yes">
|
||||||
|
<!-- Use "mdp5_cfg->mdp.smp.clients[enum mdp5_pipe]" instead -->
|
||||||
|
<bitfield name="CLIENT0" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="CLIENT1" low="8" high="15" type="uint"/>
|
||||||
|
<bitfield name="CLIENT2" low="16" high="23" type="uint"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<reg32 offset="0x00000" name="HW_VERSION">
|
||||||
|
<bitfield name="STEP" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="MINOR" low="16" high="27" type="uint"/>
|
||||||
|
<bitfield name="MAJOR" low="28" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x00004" name="DISP_INTF_SEL">
|
||||||
|
<bitfield name="INTF0" low="0" high="7" type="mdp5_intf_type"/>
|
||||||
|
<bitfield name="INTF1" low="8" high="15" type="mdp5_intf_type"/>
|
||||||
|
<bitfield name="INTF2" low="16" high="23" type="mdp5_intf_type"/>
|
||||||
|
<bitfield name="INTF3" low="24" high="31" type="mdp5_intf_type"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00010" name="INTR_EN" type="MDP5_IRQ"/>
|
||||||
|
<reg32 offset="0x00014" name="INTR_STATUS" type="MDP5_IRQ"/>
|
||||||
|
<reg32 offset="0x00018" name="INTR_CLEAR" type="MDP5_IRQ"/>
|
||||||
|
<reg32 offset="0x0001C" name="HIST_INTR_EN"/>
|
||||||
|
<reg32 offset="0x00020" name="HIST_INTR_STATUS"/>
|
||||||
|
<reg32 offset="0x00024" name="HIST_INTR_CLEAR"/>
|
||||||
|
<reg32 offset="0x00028" name="SPARE_0">
|
||||||
|
<bitfield name="SPLIT_DPL_SINGLE_FLUSH_EN" pos="0"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<array offset="0x00080" name="SMP_ALLOC_W" length="8" stride="4">
|
||||||
|
<reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
|
||||||
|
</array>
|
||||||
|
<array offset="0x00130" name="SMP_ALLOC_R" length="8" stride="4">
|
||||||
|
<reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<enum name="mdp5_igc_type">
|
||||||
|
<value name="IGC_VIG" value="0"/> <!-- 0x200 -->
|
||||||
|
<value name="IGC_RGB" value="1"/> <!-- 0x210 -->
|
||||||
|
<value name="IGC_DMA" value="2"/> <!-- 0x220 -->
|
||||||
|
<value name="IGC_DSPP" value="3"/> <!-- 0x300 -->
|
||||||
|
</enum>
|
||||||
|
<array offsets="0x00200,0x00210,0x00220,0x00300" name="IGC" length="3" stride="0x10" index="mdp5_igc_type">
|
||||||
|
<array offset="0x00" name="LUT" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="VAL" low="0" high="11"/>
|
||||||
|
<bitfield name="INDEX_UPDATE" pos="25" type="boolean"/>
|
||||||
|
<!--
|
||||||
|
not sure about these:
|
||||||
|
/* INDEX_UPDATE */
|
||||||
|
data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
|
||||||
|
MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
|
||||||
|
-->
|
||||||
|
<bitfield name="DISABLE_PIPE_0" pos="28" type="boolean"/>
|
||||||
|
<bitfield name="DISABLE_PIPE_1" pos="29" type="boolean"/>
|
||||||
|
<bitfield name="DISABLE_PIPE_2" pos="30" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
|
||||||
|
<reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
|
||||||
|
<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
|
||||||
|
<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<!-- check length/index.. -->
|
||||||
|
<array doffsets="mdp5_cfg->ctl.base[0],mdp5_cfg->ctl.base[1],mdp5_cfg->ctl.base[2],mdp5_cfg->ctl.base[3],mdp5_cfg->ctl.base[4]" name="CTL" length="5" stride="0x400">
|
||||||
|
<array offsets="0x000,0x004,0x008,0x00C,0x010,0x024" name="LAYER" length="6" stride="4">
|
||||||
|
<!--
|
||||||
|
NOTE: for backwards compat (from when there were fewer stages),
|
||||||
|
this register has the low three bits of mdp_mixer_stage_id, with
|
||||||
|
the high bit coming from LAYER_EXT
|
||||||
|
-->
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="VIG0" low="0" high="2" type="uint"/>
|
||||||
|
<bitfield name="VIG1" low="3" high="5" type="uint"/>
|
||||||
|
<bitfield name="VIG2" low="6" high="8" type="uint"/>
|
||||||
|
<bitfield name="RGB0" low="9" high="11" type="uint"/>
|
||||||
|
<bitfield name="RGB1" low="12" high="14" type="uint"/>
|
||||||
|
<bitfield name="RGB2" low="15" high="17" type="uint"/>
|
||||||
|
<bitfield name="DMA0" low="18" high="20" type="uint"/>
|
||||||
|
<bitfield name="DMA1" low="21" high="23" type="uint"/>
|
||||||
|
<bitfield name="BORDER_COLOR" pos="24" type="boolean"/>
|
||||||
|
<bitfield name="CURSOR_OUT" pos="25" type="boolean"/>
|
||||||
|
<bitfield name="VIG3" low="26" high="28" type="uint"/>
|
||||||
|
<bitfield name="RGB3" low="29" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x014" name="OP">
|
||||||
|
<bitfield name="MODE" low="0" high="3" type="mdp5_ctl_mode"/>
|
||||||
|
<bitfield name="INTF_NUM" low="4" high="6" type="mdp5_intfnum"/>
|
||||||
|
<bitfield name="CMD_MODE" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="PACK_3D_ENABLE" pos="19" type="boolean"/>
|
||||||
|
<bitfield name="PACK_3D" low="20" high="21" type="mdp5_pack_3d"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x018" name="FLUSH">
|
||||||
|
<bitfield name="VIG0" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="VIG1" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="VIG2" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="RGB0" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="RGB1" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="RGB2" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="LM0" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="LM1" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="LM2" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="LM3" pos="9" type="boolean"/>
|
||||||
|
<bitfield name="LM4" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="DMA0" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="DMA1" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="DSPP0" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="DSPP1" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="DSPP2" pos="15" type="boolean"/>
|
||||||
|
<bitfield name="WB" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="CTL" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="VIG3" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="RGB3" pos="19" type="boolean"/>
|
||||||
|
<bitfield name="LM5" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="DSPP3" pos="21" type="boolean"/>
|
||||||
|
<bitfield name="CURSOR_0" pos="22" type="boolean"/>
|
||||||
|
<bitfield name="CURSOR_1" pos="23" type="boolean"/>
|
||||||
|
<bitfield name="CHROMADOWN_0" pos="26" type="boolean"/>
|
||||||
|
<bitfield name="TIMING_3" pos="28" type="boolean"/>
|
||||||
|
<bitfield name="TIMING_2" pos="29" type="boolean"/>
|
||||||
|
<bitfield name="TIMING_1" pos="30" type="boolean"/>
|
||||||
|
<bitfield name="TIMING_0" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x01C" name="START"/>
|
||||||
|
<reg32 offset="0x020" name="PACK_3D"/>
|
||||||
|
<array offsets="0x040,0x044,0x048,0x04C,0x050,0x054" name="LAYER_EXT" length="6" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="VIG0_BIT3" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="VIG1_BIT3" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="VIG2_BIT3" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="VIG3_BIT3" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="RGB0_BIT3" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="RGB1_BIT3" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="RGB2_BIT3" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="RGB3_BIT3" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="DMA0_BIT3" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="DMA1_BIT3" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="CURSOR0" low="20" high="23" type="mdp_mixer_stage_id"/>
|
||||||
|
<bitfield name="CURSOR1" low="26" high="29" type="mdp_mixer_stage_id"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<enum name="mdp5_data_format">
|
||||||
|
<value name="DATA_FORMAT_RGB" value="0"/>
|
||||||
|
<value name="DATA_FORMAT_YUV" value="1"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<array doffsets="INVALID_IDX(idx),mdp5_cfg->pipe_vig.base[0],mdp5_cfg->pipe_vig.base[1],mdp5_cfg->pipe_vig.base[2],mdp5_cfg->pipe_rgb.base[0],mdp5_cfg->pipe_rgb.base[1],mdp5_cfg->pipe_rgb.base[2],mdp5_cfg->pipe_dma.base[0],mdp5_cfg->pipe_dma.base[1],mdp5_cfg->pipe_vig.base[3],mdp5_cfg->pipe_rgb.base[3],mdp5_cfg->pipe_cursor.base[0],mdp5_cfg->pipe_cursor.base[1]" name="PIPE" length="10" stride="0x400" index="mdp5_pipe">
|
||||||
|
<reg32 offset="0x200" name="OP_MODE">
|
||||||
|
<bitfield name="CSC_DST_DATA_FORMAT" pos="19" type="mdp5_data_format"/>
|
||||||
|
<bitfield name="CSC_SRC_DATA_FORMAT" pos="18" type="mdp5_data_format"/>
|
||||||
|
<bitfield name="CSC_1_EN" pos="17" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x2C4" name="HIST_CTL_BASE"/>
|
||||||
|
<reg32 offset="0x2F0" name="HIST_LUT_BASE"/>
|
||||||
|
<reg32 offset="0x300" name="HIST_LUT_SWAP"/>
|
||||||
|
<reg32 offset="0x320" name="CSC_1_MATRIX_COEFF_0">
|
||||||
|
<bitfield name="COEFF_11" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="COEFF_12" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x324" name="CSC_1_MATRIX_COEFF_1">
|
||||||
|
<bitfield name="COEFF_13" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="COEFF_21" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x328" name="CSC_1_MATRIX_COEFF_2">
|
||||||
|
<bitfield name="COEFF_22" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="COEFF_23" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x32c" name="CSC_1_MATRIX_COEFF_3">
|
||||||
|
<bitfield name="COEFF_31" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="COEFF_32" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x330" name="CSC_1_MATRIX_COEFF_4">
|
||||||
|
<bitfield name="COEFF_33" low="0" high="12" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<array offset="0x334" name="CSC_1_PRE_CLAMP" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="HIGH" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="LOW" low="8" high="15" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<array offset="0x340" name="CSC_1_POST_CLAMP" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="HIGH" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="LOW" low="8" high="15" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<array offset="0x34c" name="CSC_1_PRE_BIAS" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="VALUE" low="0" high="8" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<array offset="0x358" name="CSC_1_POST_BIAS" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="VALUE" low="0" high="8" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<!-- SSPP: -->
|
||||||
|
<reg32 offset="0x000" name="SRC_SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x004" name="SRC_IMG_SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x008" name="SRC_XY" type="reg_xy"/>
|
||||||
|
<reg32 offset="0x00C" name="OUT_SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x010" name="OUT_XY" type="reg_xy"/>
|
||||||
|
<reg32 offset="0x014" name="SRC0_ADDR"/>
|
||||||
|
<reg32 offset="0x018" name="SRC1_ADDR"/>
|
||||||
|
<reg32 offset="0x01C" name="SRC2_ADDR"/>
|
||||||
|
<reg32 offset="0x020" name="SRC3_ADDR"/>
|
||||||
|
<reg32 offset="0x024" name="SRC_STRIDE_A">
|
||||||
|
<bitfield name="P0" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="P1" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x028" name="SRC_STRIDE_B">
|
||||||
|
<bitfield name="P2" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="P3" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x02C" name="STILE_FRAME_SIZE"/>
|
||||||
|
<reg32 offset="0x030" name="SRC_FORMAT">
|
||||||
|
<bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
|
||||||
|
<bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
|
||||||
|
<bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
|
||||||
|
<bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
|
||||||
|
<bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="CPP" low="9" high="10" type="uint">
|
||||||
|
<brief>8bit characters per pixel minus 1</brief>
|
||||||
|
</bitfield>
|
||||||
|
<bitfield name="ROT90" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="UNPACK_COUNT" low="12" high="13" type="uint"/>
|
||||||
|
<bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="FETCH_TYPE" low="19" high="20" type="mdp_fetch_type"/>
|
||||||
|
<bitfield name="CHROMA_SAMP" low="23" high="24" type="mdp_chroma_samp_type"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x034" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
|
||||||
|
<reg32 offset="0x038" name="SRC_OP_MODE">
|
||||||
|
<bitfield name="BWC_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="BWC" low="1" high="2" type="mdp5_pipe_bwc"/>
|
||||||
|
<bitfield name="FLIP_LR" pos="13" type="boolean"/>
|
||||||
|
<bitfield name="FLIP_UD" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="IGC_EN" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="IGC_ROM_0" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="IGC_ROM_1" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="DEINTERLACE" pos="22" type="boolean"/>
|
||||||
|
<bitfield name="DEINTERLACE_ODD" pos="23" type="boolean"/>
|
||||||
|
<bitfield name="SW_PIX_EXT_OVERRIDE" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x03c" name="SRC_CONSTANT_COLOR"/>
|
||||||
|
<reg32 offset="0x048" name="FETCH_CONFIG"/>
|
||||||
|
<reg32 offset="0x04c" name="VC1_RANGE"/>
|
||||||
|
<reg32 offset="0x050" name="REQPRIO_FIFO_WM_0"/>
|
||||||
|
<reg32 offset="0x054" name="REQPRIO_FIFO_WM_1"/>
|
||||||
|
<reg32 offset="0x058" name="REQPRIO_FIFO_WM_2"/>
|
||||||
|
<reg32 offset="0x070" name="SRC_ADDR_SW_STATUS"/>
|
||||||
|
<reg32 offset="0x0a4" name="CURRENT_SRC0_ADDR"/>
|
||||||
|
<reg32 offset="0x0a8" name="CURRENT_SRC1_ADDR"/>
|
||||||
|
<reg32 offset="0x0ac" name="CURRENT_SRC2_ADDR"/>
|
||||||
|
<reg32 offset="0x0b0" name="CURRENT_SRC3_ADDR"/>
|
||||||
|
<reg32 offset="0x0b4" name="DECIMATION">
|
||||||
|
<bitfield name="VERT" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="HORZ" low="8" high="15" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<array offsets="0x100,0x110,0x120" name="SW_PIX_EXT" length="3" stride="0x10" index="mdp_component_type">
|
||||||
|
<!--
|
||||||
|
Notes:
|
||||||
|
o These value only take effect if SW_PIX_EXT_OVERRIDE is set in SRC_OP_MODE register
|
||||||
|
o For signed values (int): + indicates overfetch, - indicates line drop
|
||||||
|
-->
|
||||||
|
<reg32 offset="0x00" name="LR">
|
||||||
|
<bitfield name="LEFT_RPT" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="LEFT_OVF" low="8" high="15" type="int"/>
|
||||||
|
<bitfield name="RIGHT_RPT" low="16" high="23" type="uint"/>
|
||||||
|
<bitfield name="RIGHT_OVF" low="24" high="31" type="int"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x04" name="TB">
|
||||||
|
<bitfield name="TOP_RPT" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="TOP_OVF" low="8" high="15" type="int"/>
|
||||||
|
<bitfield name="BOTTOM_RPT" low="16" high="23" type="uint"/>
|
||||||
|
<bitfield name="BOTTOM_OVF" low="24" high="31" type="int"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x08" name="REQ_PIXELS">
|
||||||
|
<bitfield name="LEFT_RIGHT" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="TOP_BOTTOM" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x204" name="SCALE_CONFIG">
|
||||||
|
<bitfield name="SCALEX_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="SCALEY_EN" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="SCALEX_FILTER_COMP_0" low="8" high="9" type="mdp5_scale_filter"/>
|
||||||
|
<bitfield name="SCALEY_FILTER_COMP_0" low="10" high="11" type="mdp5_scale_filter"/>
|
||||||
|
<bitfield name="SCALEX_FILTER_COMP_1_2" low="12" high="13" type="mdp5_scale_filter"/>
|
||||||
|
<bitfield name="SCALEY_FILTER_COMP_1_2" low="14" high="15" type="mdp5_scale_filter"/>
|
||||||
|
<bitfield name="SCALEX_FILTER_COMP_3" low="16" high="17" type="mdp5_scale_filter"/>
|
||||||
|
<bitfield name="SCALEY_FILTER_COMP_3" low="18" high="19" type="mdp5_scale_filter"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x210" name="SCALE_PHASE_STEP_X"/>
|
||||||
|
<reg32 offset="0x214" name="SCALE_PHASE_STEP_Y"/>
|
||||||
|
<reg32 offset="0x218" name="SCALE_CR_PHASE_STEP_X"/>
|
||||||
|
<reg32 offset="0x21c" name="SCALE_CR_PHASE_STEP_Y"/>
|
||||||
|
<reg32 offset="0x220" name="SCALE_INIT_PHASE_X"/>
|
||||||
|
<reg32 offset="0x224" name="SCALE_INIT_PHASE_Y"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<array doffsets="mdp5_cfg->lm.base[0],mdp5_cfg->lm.base[1],mdp5_cfg->lm.base[2],mdp5_cfg->lm.base[3],mdp5_cfg->lm.base[4],mdp5_cfg->lm.base[5]" name="LM" length="6" stride="0x400">
|
||||||
|
<reg32 offset="0x000" name="BLEND_COLOR_OUT">
|
||||||
|
<bitfield name="STAGE0_FG_ALPHA" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="STAGE1_FG_ALPHA" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="STAGE2_FG_ALPHA" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="STAGE3_FG_ALPHA" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="STAGE4_FG_ALPHA" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="STAGE5_FG_ALPHA" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="STAGE6_FG_ALPHA" pos="7" type="boolean"/>
|
||||||
|
<bitfield name="SPLIT_LEFT_RIGHT" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x004" name="OUT_SIZE" type="reg_wh"/>
|
||||||
|
<reg32 offset="0x008" name="BORDER_COLOR_0"/>
|
||||||
|
<reg32 offset="0x010" name="BORDER_COLOR_1"/>
|
||||||
|
<array offsets="0x020,0x050,0x080,0x0B0,0x230,0x260,0x290" name="BLEND" length="7" stride="0x30">
|
||||||
|
<reg32 offset="0x00" name="OP_MODE">
|
||||||
|
<bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
|
||||||
|
<bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
|
||||||
|
<bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
|
||||||
|
<bitfield name="FG_INV_MOD_ALPHA" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="FG_TRANSP_EN" pos="5" type="boolean"/>
|
||||||
|
<bitfield name="BG_ALPHA" low="8" high="9" type="mdp_alpha_type"/>
|
||||||
|
<bitfield name="BG_INV_ALPHA" pos="10" type="boolean"/>
|
||||||
|
<bitfield name="BG_MOD_ALPHA" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="BG_INV_MOD_ALPHA" pos="12" type="boolean"/>
|
||||||
|
<bitfield name="BG_TRANSP_EN" pos="13" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x04" name="FG_ALPHA"/>
|
||||||
|
<reg32 offset="0x08" name="BG_ALPHA"/>
|
||||||
|
<reg32 offset="0x0c" name="FG_TRANSP_LOW0"/>
|
||||||
|
<reg32 offset="0x10" name="FG_TRANSP_LOW1"/>
|
||||||
|
<reg32 offset="0x14" name="FG_TRANSP_HIGH0"/>
|
||||||
|
<reg32 offset="0x18" name="FG_TRANSP_HIGH1"/>
|
||||||
|
<reg32 offset="0x1c" name="BG_TRANSP_LOW0"/>
|
||||||
|
<reg32 offset="0x20" name="BG_TRANSP_LOW1"/>
|
||||||
|
<reg32 offset="0x24" name="BG_TRANSP_HIGH0"/>
|
||||||
|
<reg32 offset="0x28" name="BG_TRANSP_HIGH1"/>
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x0e0" name="CURSOR_IMG_SIZE">
|
||||||
|
<bitfield name="SRC_W" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="SRC_H" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0e4" name="CURSOR_SIZE">
|
||||||
|
<bitfield name="ROI_W" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="ROI_H" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0e8" name="CURSOR_XY">
|
||||||
|
<bitfield name="SRC_X" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="SRC_Y" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0dc" name="CURSOR_STRIDE">
|
||||||
|
<bitfield name="STRIDE" low="0" high="15" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0ec" name="CURSOR_FORMAT">
|
||||||
|
<bitfield name="FORMAT" low="0" high="2" type="mdp5_cursor_format"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0f0" name="CURSOR_BASE_ADDR"/>
|
||||||
|
<reg32 offset="0x0f4" name="CURSOR_START_XY">
|
||||||
|
<bitfield name="X_START" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="Y_START" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0f8" name="CURSOR_BLEND_CONFIG">
|
||||||
|
<bitfield name="BLEND_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="BLEND_ALPHA_SEL" low="1" high="2" type="mdp5_cursor_alpha"/>
|
||||||
|
<bitfield name="BLEND_TRANSP_EN" pos="3" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x0fc" name="CURSOR_BLEND_PARAM"/>
|
||||||
|
<reg32 offset="0x100" name="CURSOR_BLEND_TRANSP_LOW0"/>
|
||||||
|
<reg32 offset="0x104" name="CURSOR_BLEND_TRANSP_LOW1"/>
|
||||||
|
<reg32 offset="0x108" name="CURSOR_BLEND_TRANSP_HIGH0"/>
|
||||||
|
<reg32 offset="0x10c" name="CURSOR_BLEND_TRANSP_HIGH1"/>
|
||||||
|
<reg32 offset="0x110" name="GC_LUT_BASE"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<array doffsets="mdp5_cfg->dspp.base[0],mdp5_cfg->dspp.base[1],mdp5_cfg->dspp.base[2],mdp5_cfg->dspp.base[3]" name="DSPP" length="4" stride="0x400">
|
||||||
|
<reg32 offset="0x000" name="OP_MODE">
|
||||||
|
<bitfield name="IGC_LUT_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="IGC_TBL_IDX" low="1" high="3" type="uint"/>
|
||||||
|
<bitfield name="PCC_EN" pos="4" type="boolean"/>
|
||||||
|
<bitfield name="DITHER_EN" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="HIST_EN" pos="16" type="boolean"/>
|
||||||
|
<bitfield name="AUTO_CLEAR" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="HIST_LUT_EN" pos="19" type="boolean"/>
|
||||||
|
<bitfield name="PA_EN" pos="20" type="boolean"/>
|
||||||
|
<bitfield name="GAMUT_EN" pos="23" type="boolean"/>
|
||||||
|
<bitfield name="GAMUT_ORDER" pos="24" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x030" name="PCC_BASE"/>
|
||||||
|
<reg32 offset="0x150" name="DITHER_DEPTH"/>
|
||||||
|
<reg32 offset="0x210" name="HIST_CTL_BASE"/>
|
||||||
|
<reg32 offset="0x230" name="HIST_LUT_BASE"/>
|
||||||
|
<reg32 offset="0x234" name="HIST_LUT_SWAP"/>
|
||||||
|
<reg32 offset="0x238" name="PA_BASE"/>
|
||||||
|
<reg32 offset="0x2dc" name="GAMUT_BASE"/>
|
||||||
|
<reg32 offset="0x2b0" name="GC_BASE"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<array doffsets="mdp5_cfg->pp.base[0],mdp5_cfg->pp.base[1],mdp5_cfg->pp.base[2],mdp5_cfg->pp.base[3]" name="PP" length="4" stride="0x100">
|
||||||
|
<reg32 offset="0x000" name="TEAR_CHECK_EN"/>
|
||||||
|
<reg32 offset="0x004" name="SYNC_CONFIG_VSYNC">
|
||||||
|
<bitfield name="COUNT" low="0" high="18" type="uint"/>
|
||||||
|
<bitfield name="COUNTER_EN" pos="19" type="boolean"/>
|
||||||
|
<bitfield name="IN_EN" pos="20" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x008" name="SYNC_CONFIG_HEIGHT"/>
|
||||||
|
<reg32 offset="0x00c" name="SYNC_WRCOUNT">
|
||||||
|
<bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x010" name="VSYNC_INIT_VAL"/>
|
||||||
|
<reg32 offset="0x014" name="INT_COUNT_VAL">
|
||||||
|
<bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x018" name="SYNC_THRESH">
|
||||||
|
<bitfield name="START" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="CONTINUE" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x01c" name="START_POS"/>
|
||||||
|
<reg32 offset="0x020" name="RD_PTR_IRQ"/>
|
||||||
|
<reg32 offset="0x024" name="WR_PTR_IRQ"/>
|
||||||
|
<reg32 offset="0x028" name="OUT_LINE_COUNT"/>
|
||||||
|
<reg32 offset="0x02c" name="PP_LINE_COUNT"/>
|
||||||
|
<reg32 offset="0x030" name="AUTOREFRESH_CONFIG"/>
|
||||||
|
<reg32 offset="0x034" name="FBC_MODE"/>
|
||||||
|
<reg32 offset="0x038" name="FBC_BUDGET_CTL"/>
|
||||||
|
<reg32 offset="0x03c" name="FBC_LOSSY_MODE"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<enum name="mdp5_block_size">
|
||||||
|
<value name="BLOCK_SIZE_64" value="0"/>
|
||||||
|
<value name="BLOCK_SIZE_128" value="1"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_rotate_mode">
|
||||||
|
<value name="ROTATE_0" value="0"/>
|
||||||
|
<value name="ROTATE_90" value="1"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp5_chroma_downsample_method">
|
||||||
|
<value name="DS_MTHD_NO_PIXEL_DROP" value="0"/>
|
||||||
|
<value name="DS_MTHD_PIXEL_DROP" value="1"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<array doffsets="mdp5_cfg->wb.base[0],mdp5_cfg->wb.base[1],mdp5_cfg->wb.base[2],mdp5_cfg->wb.base[3],,mdp5_cfg->wb.base[4]" name="WB" length="5" stride="0x400">
|
||||||
|
<reg32 offset="0x000" name="DST_FORMAT">
|
||||||
|
<bitfield name="DSTC0_OUT" low="0" high="1" type="uint"/>
|
||||||
|
<bitfield name="DSTC1_OUT" low="2" high="3" type="uint"/>
|
||||||
|
<bitfield name="DSTC2_OUT" low="4" high="5" type="uint"/>
|
||||||
|
<bitfield name="DSTC3_OUT" low="6" high="7" type="uint"/>
|
||||||
|
<bitfield name="DSTC3_EN" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="DST_BPP" low="9" high="10" type="uint"/>
|
||||||
|
<bitfield name="PACK_COUNT" low="12" high="13" type="uint"/>
|
||||||
|
<bitfield name="DST_ALPHA_X" pos="14" type="boolean"/>
|
||||||
|
<bitfield name="PACK_TIGHT" pos="17" type="boolean"/>
|
||||||
|
<bitfield name="PACK_ALIGN_MSB" pos="18" type="boolean"/>
|
||||||
|
<bitfield name="WRITE_PLANES" low="19" high="20" type="uint"/>
|
||||||
|
<bitfield name="DST_DITHER_EN" pos="22" type="boolean"/>
|
||||||
|
<bitfield name="DST_CHROMA_SAMP" low="23" high="25" type="uint"/>
|
||||||
|
<bitfield name="DST_CHROMA_SITE" low="26" high="29" type="uint"/>
|
||||||
|
<bitfield name="FRAME_FORMAT" low="30" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x004" name="DST_OP_MODE">
|
||||||
|
<bitfield name="BWC_ENC_EN" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="BWC_ENC_OP" low="1" high="2" type="uint"/>
|
||||||
|
<bitfield name="BLOCK_SIZE" low="4" high="4" type="uint"/>
|
||||||
|
<bitfield name="ROT_MODE" low="5" high="5" type="uint"/>
|
||||||
|
<bitfield name="ROT_EN" pos="6" type="boolean"/>
|
||||||
|
<bitfield name="CSC_EN" pos="8" type="boolean"/>
|
||||||
|
<bitfield name="CSC_SRC_DATA_FORMAT" low="9" high="9" type="uint"/>
|
||||||
|
<bitfield name="CSC_DST_DATA_FORMAT" low="10" high="10" type="uint"/>
|
||||||
|
<bitfield name="CHROMA_DWN_SAMPLE_EN" pos="11" type="boolean"/>
|
||||||
|
<bitfield name="CHROMA_DWN_SAMPLE_FORMAT" low="12" high="12" type="uint"/>
|
||||||
|
<bitfield name="CHROMA_DWN_SAMPLE_H_MTHD" low="13" high="13" type="uint"/>
|
||||||
|
<bitfield name="CHROMA_DWN_SAMPLE_V_MTHD" low="14" high="14" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x008" name="DST_PACK_PATTERN">
|
||||||
|
<bitfield name="ELEMENT0" low="0" high="1" type="uint"/>
|
||||||
|
<bitfield name="ELEMENT1" low="8" high="9" type="uint"/>
|
||||||
|
<bitfield name="ELEMENT2" low="16" high="17" type="uint"/>
|
||||||
|
<bitfield name="ELEMENT3" low="24" high="25" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00c" name="DST0_ADDR"/>
|
||||||
|
<reg32 offset="0x010" name="DST1_ADDR"/>
|
||||||
|
<reg32 offset="0x014" name="DST2_ADDR"/>
|
||||||
|
<reg32 offset="0x018" name="DST3_ADDR"/>
|
||||||
|
<reg32 offset="0x01c" name="DST_YSTRIDE0">
|
||||||
|
<bitfield name="DST0_YSTRIDE" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="DST1_YSTRIDE" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x020" name="DST_YSTRIDE1">
|
||||||
|
<bitfield name="DST2_YSTRIDE" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="DST3_YSTRIDE" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x024" name="DST_DITHER_BITDEPTH"/>
|
||||||
|
<reg32 offset="0x030" name="DITHER_MATRIX_ROW0"/>
|
||||||
|
<reg32 offset="0x034" name="DITHER_MATRIX_ROW1"/>
|
||||||
|
<reg32 offset="0x038" name="DITHER_MATRIX_ROW2"/>
|
||||||
|
<reg32 offset="0x03c" name="DITHER_MATRIX_ROW3"/>
|
||||||
|
<reg32 offset="0x048" name="DST_WRITE_CONFIG"/>
|
||||||
|
<reg32 offset="0x050" name="ROTATION_DNSCALER"/>
|
||||||
|
<reg32 offset="0x060" name="N16_INIT_PHASE_X_0_3"/>
|
||||||
|
<reg32 offset="0x064" name="N16_INIT_PHASE_X_1_2"/>
|
||||||
|
<reg32 offset="0x068" name="N16_INIT_PHASE_Y_0_3"/>
|
||||||
|
<reg32 offset="0x06c" name="N16_INIT_PHASE_Y_1_2"/>
|
||||||
|
<reg32 offset="0x074" name="OUT_SIZE">
|
||||||
|
<bitfield name="DST_W" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="DST_H" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x078" name="ALPHA_X_VALUE"/>
|
||||||
|
<reg32 offset="0x260" name="CSC_MATRIX_COEFF_0">
|
||||||
|
<bitfield name="COEFF_11" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="COEFF_12" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x264" name="CSC_MATRIX_COEFF_1">
|
||||||
|
<bitfield name="COEFF_13" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="COEFF_21" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x268" name="CSC_MATRIX_COEFF_2">
|
||||||
|
<bitfield name="COEFF_22" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="COEFF_23" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x26c" name="CSC_MATRIX_COEFF_3">
|
||||||
|
<bitfield name="COEFF_31" low="0" high="12" type="uint"/>
|
||||||
|
<bitfield name="COEFF_32" low="16" high="28" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x270" name="CSC_MATRIX_COEFF_4">
|
||||||
|
<bitfield name="COEFF_33" low="0" high="12" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<array offset="0x274" name="CSC_COMP_PRECLAMP" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="HIGH" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="LOW" low="8" high="15" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<array offset="0x280" name="CSC_COMP_POSTCLAMP" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="HIGH" low="0" high="7" type="uint"/>
|
||||||
|
<bitfield name="LOW" low="8" high="15" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<array offset="0x28c" name="CSC_COMP_PREBIAS" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="VALUE" low="0" high="8" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
<array offset="0x298" name="CSC_COMP_POSTBIAS" length="3" stride="4">
|
||||||
|
<reg32 offset="0" name="REG">
|
||||||
|
<bitfield name="VALUE" low="0" high="8" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
</array>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<array doffsets="mdp5_cfg->intf.base[0],mdp5_cfg->intf.base[1],mdp5_cfg->intf.base[2],mdp5_cfg->intf.base[3],mdp5_cfg->intf.base[4]" name="INTF" length="5" stride="0x200">
|
||||||
|
<reg32 offset="0x000" name="TIMING_ENGINE_EN"/>
|
||||||
|
<reg32 offset="0x004" name="CONFIG"/>
|
||||||
|
<reg32 offset="0x008" name="HSYNC_CTL">
|
||||||
|
<bitfield name="PULSEW" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="PERIOD" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x00c" name="VSYNC_PERIOD_F0" type="uint"/>
|
||||||
|
<reg32 offset="0x010" name="VSYNC_PERIOD_F1" type="uint"/>
|
||||||
|
<reg32 offset="0x014" name="VSYNC_LEN_F0" type="uint"/>
|
||||||
|
<reg32 offset="0x018" name="VSYNC_LEN_F1" type="uint"/>
|
||||||
|
<reg32 offset="0x01c" name="DISPLAY_VSTART_F0" type="uint"/>
|
||||||
|
<reg32 offset="0x020" name="DISPLAY_VSTART_F1" type="uint"/>
|
||||||
|
<reg32 offset="0x024" name="DISPLAY_VEND_F0" type="uint"/>
|
||||||
|
<reg32 offset="0x028" name="DISPLAY_VEND_F1" type="uint"/>
|
||||||
|
<reg32 offset="0x02c" name="ACTIVE_VSTART_F0">
|
||||||
|
<bitfield name="VAL" low="0" high="30" type="uint"/>
|
||||||
|
<bitfield name="ACTIVE_V_ENABLE" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x030" name="ACTIVE_VSTART_F1">
|
||||||
|
<bitfield name="VAL" low="0" high="30" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x034" name="ACTIVE_VEND_F0" type="uint"/>
|
||||||
|
<reg32 offset="0x038" name="ACTIVE_VEND_F1" type="uint"/>
|
||||||
|
<reg32 offset="0x03c" name="DISPLAY_HCTL">
|
||||||
|
<bitfield name="START" low="0" high="15" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="31" type="uint"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x040" name="ACTIVE_HCTL">
|
||||||
|
<bitfield name="START" low="0" high="14" type="uint"/>
|
||||||
|
<bitfield name="END" low="16" high="30" type="uint"/>
|
||||||
|
<bitfield name="ACTIVE_H_ENABLE" pos="31" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x044" name="BORDER_COLOR"/>
|
||||||
|
<reg32 offset="0x048" name="UNDERFLOW_COLOR"/>
|
||||||
|
<reg32 offset="0x04c" name="HSYNC_SKEW"/>
|
||||||
|
<reg32 offset="0x050" name="POLARITY_CTL">
|
||||||
|
<bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
|
||||||
|
<bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
|
||||||
|
<bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
|
||||||
|
</reg32>
|
||||||
|
<reg32 offset="0x054" name="TEST_CTL"/>
|
||||||
|
<reg32 offset="0x058" name="TP_COLOR0"/>
|
||||||
|
<reg32 offset="0x05c" name="TP_COLOR1"/>
|
||||||
|
<reg32 offset="0x084" name="DSI_CMD_MODE_TRIGGER_EN"/>
|
||||||
|
<reg32 offset="0x090" name="PANEL_FORMAT" type="mdp5_format"/>
|
||||||
|
<reg32 offset="0x0a8" name="FRAME_LINE_COUNT_EN"/>
|
||||||
|
<reg32 offset="0x0ac" name="FRAME_COUNT"/>
|
||||||
|
<reg32 offset="0x0b0" name="LINE_COUNT"/>
|
||||||
|
<reg32 offset="0x0f0" name="DEFLICKER_CONFIG"/>
|
||||||
|
<reg32 offset="0x0f4" name="DEFLICKER_STRNG_COEFF"/>
|
||||||
|
<reg32 offset="0x0f8" name="DEFLICKER_WEAK_COEFF"/>
|
||||||
|
<reg32 offset="0x100" name="TPG_ENABLE"/>
|
||||||
|
<reg32 offset="0x104" name="TPG_MAIN_CONTROL"/>
|
||||||
|
<reg32 offset="0x108" name="TPG_VIDEO_CONFIG"/>
|
||||||
|
<reg32 offset="0x10c" name="TPG_COMPONENT_LIMITS"/>
|
||||||
|
<reg32 offset="0x110" name="TPG_RECTANGLE"/>
|
||||||
|
<reg32 offset="0x114" name="TPG_INITIAL_VALUE"/>
|
||||||
|
<reg32 offset="0x118" name="TPG_BLK_WHITE_PATTERN_FRAME"/>
|
||||||
|
<reg32 offset="0x11c" name="TPG_RGB_MAPPING"/>
|
||||||
|
</array>
|
||||||
|
|
||||||
|
<array doffsets="mdp5_cfg->ad.base[0],mdp5_cfg->ad.base[1]" name="AD" length="2" stride="0x200">
|
||||||
|
<reg32 offset="0x000" name="BYPASS"/>
|
||||||
|
<reg32 offset="0x004" name="CTRL_0"/>
|
||||||
|
<reg32 offset="0x008" name="CTRL_1"/>
|
||||||
|
<reg32 offset="0x00c" name="FRAME_SIZE"/>
|
||||||
|
<reg32 offset="0x010" name="CON_CTRL_0"/>
|
||||||
|
<reg32 offset="0x014" name="CON_CTRL_1"/>
|
||||||
|
<reg32 offset="0x018" name="STR_MAN"/>
|
||||||
|
<reg32 offset="0x01c" name="VAR"/>
|
||||||
|
<reg32 offset="0x020" name="DITH"/>
|
||||||
|
<reg32 offset="0x024" name="DITH_CTRL"/>
|
||||||
|
<reg32 offset="0x028" name="AMP_LIM"/>
|
||||||
|
<reg32 offset="0x02c" name="SLOPE"/>
|
||||||
|
<reg32 offset="0x030" name="BW_LVL"/>
|
||||||
|
<reg32 offset="0x034" name="LOGO_POS"/>
|
||||||
|
<reg32 offset="0x038" name="LUT_FI"/>
|
||||||
|
<reg32 offset="0x07c" name="LUT_CC"/>
|
||||||
|
<reg32 offset="0x0c8" name="STR_LIM"/>
|
||||||
|
<reg32 offset="0x0cc" name="CALIB_AB"/>
|
||||||
|
<reg32 offset="0x0d0" name="CALIB_CD"/>
|
||||||
|
<reg32 offset="0x0d4" name="MODE_SEL"/>
|
||||||
|
<reg32 offset="0x0d8" name="TFILT_CTRL"/>
|
||||||
|
<reg32 offset="0x0dc" name="BL_MINMAX"/>
|
||||||
|
<reg32 offset="0x0e0" name="BL"/>
|
||||||
|
<reg32 offset="0x0e8" name="BL_MAX"/>
|
||||||
|
<reg32 offset="0x0ec" name="AL"/>
|
||||||
|
<reg32 offset="0x0f0" name="AL_MIN"/>
|
||||||
|
<reg32 offset="0x0f4" name="AL_FILT"/>
|
||||||
|
<reg32 offset="0x0f8" name="CFG_BUF"/>
|
||||||
|
<reg32 offset="0x100" name="LUT_AL"/>
|
||||||
|
<reg32 offset="0x144" name="TARG_STR"/>
|
||||||
|
<reg32 offset="0x148" name="START_CALC"/>
|
||||||
|
<reg32 offset="0x14c" name="STR_OUT"/>
|
||||||
|
<reg32 offset="0x154" name="BL_OUT"/>
|
||||||
|
<reg32 offset="0x158" name="CALC_DONE"/>
|
||||||
|
</array>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,83 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
|
||||||
|
|
||||||
|
<!-- random bits that seem same between mdp4 and mdp5 (ie. not much) -->
|
||||||
|
|
||||||
|
<enum name="mdp_chroma_samp_type">
|
||||||
|
<value name="CHROMA_FULL" value="0"/>
|
||||||
|
<value name="CHROMA_H2V1" value="1"/>
|
||||||
|
<value name="CHROMA_H1V2" value="2"/>
|
||||||
|
<value name="CHROMA_420" value="3"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp_fetch_type">
|
||||||
|
<value name="MDP_PLANE_INTERLEAVED" value="0"/>
|
||||||
|
<value name="MDP_PLANE_PLANAR" value="1"/>
|
||||||
|
<value name="MDP_PLANE_PSEUDO_PLANAR" value="2"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp_mixer_stage_id">
|
||||||
|
<value name="STAGE_UNUSED" value="0"/>
|
||||||
|
<value name="STAGE_BASE" value="1"/>
|
||||||
|
<value name="STAGE0" value="2"/> <!-- zorder 0 -->
|
||||||
|
<value name="STAGE1" value="3"/> <!-- zorder 1 -->
|
||||||
|
<value name="STAGE2" value="4"/> <!-- zorder 2 -->
|
||||||
|
<value name="STAGE3" value="5"/> <!-- zorder 3 -->
|
||||||
|
<value name="STAGE4" value="6"/> <!-- zorder 4 -->
|
||||||
|
<value name="STAGE5" value="7"/> <!-- zorder 5 -->
|
||||||
|
<value name="STAGE6" value="8"/> <!-- zorder 6 -->
|
||||||
|
<value name="STAGE_MAX" value="8"/> <!-- maximum zorder -->
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp_alpha_type">
|
||||||
|
<value name="FG_CONST" value="0"/>
|
||||||
|
<value name="BG_CONST" value="1"/>
|
||||||
|
<value name="FG_PIXEL" value="2"/>
|
||||||
|
<value name="BG_PIXEL" value="3"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp_component_type">
|
||||||
|
<value name="COMP_0" value="0"/> <!-- Y component -->
|
||||||
|
<value name="COMP_1_2" value="1"/> <!-- Cb/Cr comp. -->
|
||||||
|
<value name="COMP_3" value="2"/> <!-- Trans comp. -->
|
||||||
|
<value name="COMP_MAX" value="3"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp_bpc">
|
||||||
|
<brief>bits per component (non-alpha channel)</brief>
|
||||||
|
<value name="BPC1" value="0"/> <!-- 1 bit -->
|
||||||
|
<value name="BPC5" value="1"/> <!-- 2 bits -->
|
||||||
|
<value name="BPC6" value="2"/> <!-- 6 bits -->
|
||||||
|
<value name="BPC8" value="3"/> <!-- 8 bits -->
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="mdp_bpc_alpha">
|
||||||
|
<brief>bits per component (alpha channel)</brief>
|
||||||
|
<value name="BPC1A" value="0"/> <!-- 1 bit -->
|
||||||
|
<value name="BPC4A" value="1"/> <!-- 2 bits -->
|
||||||
|
<value name="BPC6A" value="2"/> <!-- 6 bits -->
|
||||||
|
<value name="BPC8A" value="3"/> <!-- 8 bits -->
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<bitset name="reg_wh" inline="yes">
|
||||||
|
<bitfield name="HEIGHT" low="16" high="31" type="uint"/>
|
||||||
|
<bitfield name="WIDTH" low="0" high="15" type="uint"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="reg_xy" inline="yes">
|
||||||
|
<bitfield name="Y" low="16" high="31" type="uint"/>
|
||||||
|
<bitfield name="X" low="0" high="15" type="uint"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="mdp_unpack_pattern" inline="yes">
|
||||||
|
<bitfield name="ELEM0" low="0" high="7"/>
|
||||||
|
<bitfield name="ELEM1" low="8" high="15"/>
|
||||||
|
<bitfield name="ELEM2" low="16" high="23"/>
|
||||||
|
<bitfield name="ELEM3" low="24" high="31"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
</database>
|
||||||
|
|
|
@ -33,7 +33,7 @@ foreach f : xml_files
|
||||||
_name = f + '.h'
|
_name = f + '.h'
|
||||||
freedreno_xml_header_files += custom_target(
|
freedreno_xml_header_files += custom_target(
|
||||||
_name,
|
_name,
|
||||||
input : ['gen_header.py', f],
|
input : ['gen_header.py', 'adreno/' + f],
|
||||||
output : _name,
|
output : _name,
|
||||||
command : [prog_python, '@INPUT@'],
|
command : [prog_python, '@INPUT@'],
|
||||||
capture : true,
|
capture : true,
|
||||||
|
@ -42,14 +42,14 @@ endforeach
|
||||||
|
|
||||||
freedreno_xml_header_files += custom_target(
|
freedreno_xml_header_files += custom_target(
|
||||||
'a6xx-pack.xml.h',
|
'a6xx-pack.xml.h',
|
||||||
input : ['gen_header.py', 'a6xx.xml'],
|
input : ['gen_header.py', 'adreno/a6xx.xml'],
|
||||||
output : 'a6xx-pack.xml.h',
|
output : 'a6xx-pack.xml.h',
|
||||||
command : [prog_python, '@INPUT@', '--pack-structs'],
|
command : [prog_python, '@INPUT@', '--pack-structs'],
|
||||||
capture : true,
|
capture : true,
|
||||||
)
|
)
|
||||||
freedreno_xml_header_files += custom_target(
|
freedreno_xml_header_files += custom_target(
|
||||||
'adreno-pm4-pack.xml.h',
|
'adreno-pm4-pack.xml.h',
|
||||||
input : ['gen_header.py', 'adreno_pm4.xml'],
|
input : ['gen_header.py', 'adreno/adreno_pm4.xml'],
|
||||||
output : 'adreno-pm4-pack.xml.h',
|
output : 'adreno-pm4-pack.xml.h',
|
||||||
command : [prog_python, '@INPUT@', '--pack-structs'],
|
command : [prog_python, '@INPUT@', '--pack-structs'],
|
||||||
capture : true,
|
capture : true,
|
||||||
|
|
|
@ -0,0 +1,26 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<database xmlns="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
||||||
|
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
|
||||||
|
<import file="freedreno_copyright.xml"/>
|
||||||
|
|
||||||
|
<doc>
|
||||||
|
Register definitions for the display related hw blocks on
|
||||||
|
msm/snapdragon
|
||||||
|
</doc>
|
||||||
|
|
||||||
|
<enum name="chipset">
|
||||||
|
<value name="MDP40"/>
|
||||||
|
<value name="MDP50"/>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<import file="mdp/mdp4.xml"/>
|
||||||
|
<import file="mdp/mdp5.xml"/>
|
||||||
|
<import file="dsi/dsi.xml"/>
|
||||||
|
<import file="dsi/sfpb.xml"/>
|
||||||
|
<import file="dsi/mmss_cc.xml"/>
|
||||||
|
<import file="hdmi/qfprom.xml"/>
|
||||||
|
<import file="hdmi/hdmi.xml"/>
|
||||||
|
<import file="edp/edp.xml"/>
|
||||||
|
|
||||||
|
</database>
|
|
@ -0,0 +1,703 @@
|
||||||
|
1. Introduction
|
||||||
|
|
||||||
|
rules-ng is a package consisting of a database of nvidia GPU registers in XML
|
||||||
|
format, and tools made to parse this database and do useful work with it. It
|
||||||
|
is in mostly usable state, but there are some annoyances that prevent its
|
||||||
|
adoption as the home of all nouveau documentation.
|
||||||
|
|
||||||
|
Note that this document and rules-ng understands "register" quite liberally as
|
||||||
|
"anything that has an address and can have a value in it, written to it, or
|
||||||
|
read to it". This includes conventional MMIO registers, as well as fields of
|
||||||
|
memory structures and grobj methods.
|
||||||
|
|
||||||
|
Its parsable XML format is supposed to solve three problems:
|
||||||
|
|
||||||
|
- serve as actual documentation for the known registers: supports attaching
|
||||||
|
arbitrary text in <doc> tags and generating HTML for easy reading.
|
||||||
|
- name -> hex translation: supports generating C headers that #define all
|
||||||
|
known registers, bitfields and enum values as C constants.
|
||||||
|
- hex -> name translation: you tell it the address or address+value of a
|
||||||
|
register, and it decodes the address to its symbolic name, and the value to
|
||||||
|
its constituting bitfields, if any. Useful for decoding mmio-traces /
|
||||||
|
renouveau dumps, as well as standalone use.
|
||||||
|
|
||||||
|
What's non-trivial about all this [ie. why rules-ng is not a long series of
|
||||||
|
plain address - name - documentation tuples]:
|
||||||
|
|
||||||
|
- The registers may be split into bitfields, each with a different purpose
|
||||||
|
and name [and separate documentation].
|
||||||
|
- The registers/bitfields may accept values from a predefined set [enum],
|
||||||
|
each with a different meaning. Each value also has a name and
|
||||||
|
documentation.
|
||||||
|
- The registers may come in multiple copies, forming arrays. They can also
|
||||||
|
form logical groups. And these groups can also come in multiple copies,
|
||||||
|
forming larger arrays... and you get a hierarchical structure.
|
||||||
|
- There are multiple different GPU chipsets. The available register set
|
||||||
|
changed between these chipsets - sometimes only a few registers, sometimes
|
||||||
|
half the card was remade from scratch. More annoyingly, sometimes some
|
||||||
|
registers move from one place to another, but are otherwise unchanged.
|
||||||
|
Also [nvidia-specific], new grobj classes are sometimes really just new
|
||||||
|
revisions of a base class with a few methods changed. In both of these
|
||||||
|
cases, we want to avoid duplication as much as possible.
|
||||||
|
|
||||||
|
2. Proposed new XML format
|
||||||
|
|
||||||
|
2.1. General tags
|
||||||
|
|
||||||
|
Root tag is <database>. There is one per the whole file and it should contain
|
||||||
|
everything else.
|
||||||
|
|
||||||
|
<brief> and <doc> are tags that can appear inside any other tag, and document
|
||||||
|
whatever it defines. <brief> is supposed to be a short one-line description
|
||||||
|
giving a rough idea what a given item is for if no sufficiently descriptive
|
||||||
|
name was used. <doc> can be of any length, can contain some html and html-like
|
||||||
|
tags, and is supposed to describe a given item in as much detail as needed.
|
||||||
|
There should be at most one <doc> and at most one <brief> tag for any parent.
|
||||||
|
|
||||||
|
Tags that define top-level entities include:
|
||||||
|
|
||||||
|
<domain>: Declares an addressing space containing registers
|
||||||
|
<group>: Declares a block of registers, expected to be included by one or
|
||||||
|
more <domain>s
|
||||||
|
<bitset>: Declares a list of applicable bitfields for some register
|
||||||
|
<enum>: Declares a list of related symbolic values. Can describe params to
|
||||||
|
a register/bitfield, or discriminate between card variants.
|
||||||
|
|
||||||
|
Each of these has an associated global name used to refer to them from other
|
||||||
|
parts of database. As a convenience, and to allow related stuff to be kept
|
||||||
|
together, the top-level entities are allowed to occur pretty much anywhere
|
||||||
|
inside the XML file except inside <doc> tags. This implies no scoping,
|
||||||
|
however: the effect is the same as putting the entity right below <database>.
|
||||||
|
If two top-level elements of the same type and name are defined, they'll be
|
||||||
|
merged into a single one, as if contents of one were written right after
|
||||||
|
contents of the other. All attributes of the merged tags need to match.
|
||||||
|
|
||||||
|
Another top-level tag that can be used anywhere is the <import> tag. It's used
|
||||||
|
like <import file="foo.xml"/> and makes all of foo.xml's definitions available
|
||||||
|
to the containing file. If a single file is <import>ed more than one time, all
|
||||||
|
<import>s other than the first are ignored.
|
||||||
|
|
||||||
|
2.2. Domains
|
||||||
|
|
||||||
|
All register definitions ultimately belong to a <domain>. <domain> is
|
||||||
|
basically just a single address space. So we'll have a domain for the MMIO
|
||||||
|
BAR, one for each type of memory structure we need to describe, a domain for
|
||||||
|
the grobj/FIFO methods, and a domain for each indirect index-data pair used to
|
||||||
|
access something useful. <domain> can have the following attributes:
|
||||||
|
|
||||||
|
- name [required]: The name of the domain.
|
||||||
|
- width [optional]: the size, in bits, of a single addressable unit. This is
|
||||||
|
8 by default for usual byte-addressable memory, but 32 can be useful
|
||||||
|
occasionally for indexed spaces of 32-bit cells. Values sane enough to
|
||||||
|
support for now include 8, 16, 32, 64.
|
||||||
|
- size [optional]: total number of addressable units it spans. Can be
|
||||||
|
undefined if you don't know it or it doesn't make sense. As a special
|
||||||
|
exception to the merging rules, size attribute need not be specified on all
|
||||||
|
tags that will result in a merged domain: tags with size can be merged with
|
||||||
|
tags without size, resulting in merged domain that has size. Error only
|
||||||
|
happens when the merged domains both have sizes, and the sizes differ.
|
||||||
|
- bare [optional]: if set to "no", all children items will have the domain
|
||||||
|
name prepended to their names. If set to "yes", such prefixing doesn't
|
||||||
|
happen. Default is "no".
|
||||||
|
- prefix [optional]: selects the string that should be prepended to name
|
||||||
|
of every child item. The special value "none" means no prefix, and is the
|
||||||
|
default. All other values are looked up as <enum> names and, for each child
|
||||||
|
item, its name is prefixed with name of the earliest variant in the given
|
||||||
|
enum that supports given item.
|
||||||
|
|
||||||
|
<domain name="NV_MMIO" size="0x1000000" prefix="chipset" bare="yes">
|
||||||
|
<reg32 offset="0" name="PMC_BOOT_0" />
|
||||||
|
<reg32 offset="4" name="PMC_BOOT_1" varset="chipset" variants="NV10-" />
|
||||||
|
<reg32 offset="0x100" name="PMC_INTR" />
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
Describes a space with 0x1000000 of 8-bit addressable cells. Cells 0-3 belong
|
||||||
|
to NV04_PMC_BOOT_0 register, 4-7 belong to NV10_PMC_BOOT_1 register,
|
||||||
|
0x100-0x103 belong to NV04_PMC_INTR register, and remaining cells are either
|
||||||
|
unused or unknown. The generated .h definitions are:
|
||||||
|
|
||||||
|
#define NV_MMIO__SIZE 0x1000000
|
||||||
|
#define NV04_PMC_BOOT_0 0
|
||||||
|
#define NV10_PMC_BOOT_1 4
|
||||||
|
#define NV04_PMC_INTR 0x100
|
||||||
|
|
||||||
|
<domain name="NV50_PFB_VM_TRAP" width="32" size="6">
|
||||||
|
<reg32 offset="0" name="STATUS" />
|
||||||
|
<reg32 offset="1" name="CHANNEL" />
|
||||||
|
<reg32 offset="2" name="UNK2" />
|
||||||
|
<reg32 offset="3" name="ADDRLOW" />
|
||||||
|
<reg32 offset="4" name="ADDRMID" />
|
||||||
|
<reg32 offset="5" name="ADDRHIGH" />
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
Defines a 6-cell address space with each cell 32 bits in size and
|
||||||
|
corresponding to a single register. Definitions are:
|
||||||
|
|
||||||
|
#define NV50_PFB_VM_TRAP__SIZE 6
|
||||||
|
#define NV50_PFB_VM_TRAP_STATUS 0
|
||||||
|
#define NV50_PFB_VM_TRAP_CHANNEL 1
|
||||||
|
#define NV50_PFB_VM_TRAP_UNK2 2
|
||||||
|
#define NV50_PFB_VM_TRAP_ADDRLOW 3
|
||||||
|
#define NV50_PFB_VM_TRAP_ADDRMID 4
|
||||||
|
#define NV50_PFB_VM_TRAP_ADDRHIGH 5
|
||||||
|
|
||||||
|
2.3. Registers
|
||||||
|
|
||||||
|
What we really want all the time is defining registers. This is done with
|
||||||
|
<reg8>, <reg16>, <reg32> or <reg64> tags. The register of course takes
|
||||||
|
reg_width / domain_width cells in the domain. It's an error to define a
|
||||||
|
register with smaller width than the domain it's in. The <reg*> attributes
|
||||||
|
are:
|
||||||
|
|
||||||
|
- name [required]: the name of the register
|
||||||
|
- offset [required]: the offset of the register
|
||||||
|
- access [optional]: "rw" [default], "r", or "w" to mark the register as
|
||||||
|
read-write, read-only, or write-only. Only makes sense for real MMIO
|
||||||
|
domains.
|
||||||
|
- varset [optional]: the <enum> to choose from by the variant attribute.
|
||||||
|
Defaults to first <enum> used in currently active prefix.
|
||||||
|
- variants [optional]: space-separated list of and variant ranges that this
|
||||||
|
register is present on. The items of this list can be:
|
||||||
|
- var1: a single variant
|
||||||
|
- var1-var2: all variants starting with var1 up to and including var2
|
||||||
|
- var1:var2: all variants starting with var1 up to, but not including var2
|
||||||
|
- :var1: all variants before var1
|
||||||
|
- -var1: all variants up to and including var1
|
||||||
|
- var1-: all variants starting from var1
|
||||||
|
- type [optional]: How to interpret the contents of this register.
|
||||||
|
- "uint": unsigned decimal integer
|
||||||
|
- "int": signed decimal integer
|
||||||
|
- "hex": unsigned hexadecimal integer
|
||||||
|
- "float" IEEE 16-bit, 32-bit or 64-bit floating point format, depending
|
||||||
|
on register/bitfield size
|
||||||
|
- "boolean": a boolean value: 0 is false, 1 is true
|
||||||
|
- any defined enum name: value from that anum
|
||||||
|
- "enum": value from the inline <value> tags in this <reg*>
|
||||||
|
- any defined bitset name: value decoded further according to that bitset
|
||||||
|
- "bitset": value decoded further according to the inline <bitfield>
|
||||||
|
tags
|
||||||
|
- any defined domain name: value decoded as an offset in that domain
|
||||||
|
The default is "bitset" if there are inline <bitfield> tags present,
|
||||||
|
otherwise "enum" if there are inline <value> tags present, otherwise
|
||||||
|
"boolean" if this is a bitfield with width 1, otherwise "hex".
|
||||||
|
- shr [optional]: the value in this register is the real value shifted right
|
||||||
|
by this many bits. Ie. for register with shr="12", register value 0x1234
|
||||||
|
should be interpreted as 0x1234000. May sound too specific, but happens
|
||||||
|
quite often in nvidia hardware.
|
||||||
|
- length [optional]: if specified to be other than 1, the register is treated
|
||||||
|
as if it was enclosed in an anonymous <stripe> with corresponding length
|
||||||
|
and stride attributes, except the __ESIZE and __LEN stripe defines are
|
||||||
|
emitted with the register's name. If not specified, defaults to 1.
|
||||||
|
- stride [optional]: the stride value to use if length is non-1. Defaults to
|
||||||
|
the register's size in cells.
|
||||||
|
|
||||||
|
The definitions emitted for a non-stripe register include only its offset and
|
||||||
|
shr value. Other informations are generally expected to be a part of code
|
||||||
|
logic anyway:
|
||||||
|
|
||||||
|
<reg32 offset="0x400784" name="PGRAPH_CTXCTL_SWAP" shr="12" />
|
||||||
|
|
||||||
|
results in
|
||||||
|
|
||||||
|
#define PGRAPH_CTXCTL_SWAP 0x400784
|
||||||
|
#define PGRAPH_CTXCTL_SWAP__SHR 12
|
||||||
|
|
||||||
|
For striped registers, __LEN and __ESIZE definitions like <stripe> are emitted
|
||||||
|
too:
|
||||||
|
|
||||||
|
<!-- in a 8-bit domain -->
|
||||||
|
<reg32 offset="0x0600" name="NV50_COMPUTE_USER_PARAM" length="64" />
|
||||||
|
|
||||||
|
results in
|
||||||
|
|
||||||
|
#define NV50_COMPUTE_USER_PARAM(i) (0x600 + (i)*4)
|
||||||
|
#define NV50_COMPUTE_USER_PARAM__LEN 64
|
||||||
|
#define NV50_COMPUTE_USER_PARAM__ESIZE 4
|
||||||
|
|
||||||
|
The <reg*> tags can also contain either bitfield definitions, or enum value
|
||||||
|
definitions.
|
||||||
|
|
||||||
|
2.4. Enums and variants
|
||||||
|
|
||||||
|
Enum is, basically, a set of values. They're defined by <enum> tag with the
|
||||||
|
following attributes:
|
||||||
|
|
||||||
|
- name [required]: an identifying name.
|
||||||
|
- inline [optional]: "yes" or "no", with "no" being the default. Selects if
|
||||||
|
this enum should emit its own definitions in .h file, or be inlined into
|
||||||
|
any <reg*> / <bitfield> definitions that reference it.
|
||||||
|
- bare [optional]: only for no-inline enums, behaves like bare attribute
|
||||||
|
to <domain>
|
||||||
|
- prefix [optional]: only for no-inline enums, behaves like prefix attribute
|
||||||
|
to <domain>.
|
||||||
|
|
||||||
|
The <enum> tag contains <value> tags with the following attributes:
|
||||||
|
|
||||||
|
- name [required]: the name of the value
|
||||||
|
- value [optional]: the value
|
||||||
|
- varset [optional]: like in <reg*>
|
||||||
|
- variants [optional]: like in <reg*>
|
||||||
|
|
||||||
|
The <enum>s are referenced from inside <reg*> and <bitfield> tags by setting
|
||||||
|
the type attribute to the name of the enum. For single-use enums, the <value>
|
||||||
|
tags can also be written directly inside <reg*> tag.
|
||||||
|
|
||||||
|
<enum name="SURFACE_FORMAT" prefix="chipset">
|
||||||
|
<value value="6" name="A8R8G8B8" />
|
||||||
|
<value value="0x12" name="A8R8G8B8_RECT" variants="NV10-" />
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<enum name="gl_shade_model" inline="yes">
|
||||||
|
<value value="0x1d00" name="FLAT" />
|
||||||
|
<value value="0x1d01" name="SMOOTH" />
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<reg32 offset="0x1234" name="TEXTURE_FORMAT" type="SURFACE_FORMAT" />
|
||||||
|
<reg32 offset="0x1238" name="SHADE_MODEL" type="gl_shade_model" />
|
||||||
|
<reg32 offset="0x123c" name="PATTERN_SELECT">
|
||||||
|
<value value="1" name="MONO" />
|
||||||
|
<value value="2" name="COLOR" />
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
Result:
|
||||||
|
|
||||||
|
#define NV04_SURFACE_FORMAT_A8R8G8B8 6
|
||||||
|
#define NV04_SURFACE_FORMAT_A8R8G8B8_RECT 0x12
|
||||||
|
#define TEXTURE_FORMAT 0x1234
|
||||||
|
#define SHADE_MODEL 0x1238
|
||||||
|
#define SHADE_MODEL_FLAT 0x1d00
|
||||||
|
#define SHADE_MODEL_SMOOTH 0x1d01
|
||||||
|
#define PATTERN_SELECT 0x123c
|
||||||
|
#define PATTERN_SELECT_MONO 1
|
||||||
|
#define PATTERN_SELECT_COLOR 2
|
||||||
|
|
||||||
|
Another use for enums is describing variants: slightly different versions of
|
||||||
|
cards, objects, etc. The varset and variant attributes of most tags allow
|
||||||
|
defining items that are only present when you're dealing with something of the
|
||||||
|
matching variant. The variant space is "multidimensional" - so you can have
|
||||||
|
a variant "dimension" representing what GPU chipset you're using at the
|
||||||
|
moment, and another dimension representing what grobj class you're dealing
|
||||||
|
with [taken from another enum]. Both of these can be independent.
|
||||||
|
|
||||||
|
<enum name="chipset">
|
||||||
|
<brief>The chipset of the card</brief>
|
||||||
|
<value name="NV04">
|
||||||
|
<brief>RIVA TNT</brief>
|
||||||
|
</value>
|
||||||
|
<value name="NV05">
|
||||||
|
<brief>RIVA TNT2</brief>
|
||||||
|
</value>
|
||||||
|
<value name="NV10">
|
||||||
|
<brief>GeForce 256</brief>
|
||||||
|
</value>
|
||||||
|
<value name="NV50">
|
||||||
|
<brief>G80: GeForce 8800 GTX, Tesla *870, ...</brief>
|
||||||
|
</value>
|
||||||
|
<value name="NV84">
|
||||||
|
<brief>G84: GeForce 8600 GT, ...</brief>
|
||||||
|
</value>
|
||||||
|
<value name="NVA0">
|
||||||
|
<brief>G200: GeForce 260 GTX, Tesla C1060, ...</brief>
|
||||||
|
</value>
|
||||||
|
<value name="NVA5">
|
||||||
|
<brief>GT216: GeForce GT 220</brief>
|
||||||
|
</value>
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
If enabled for a given domain, the name of the earliest variant to support
|
||||||
|
a given register / bitfield / value / whatever will be automatically prepended
|
||||||
|
to its name. For this purpose, "earliest" is defined as "comes first in the
|
||||||
|
XML file".
|
||||||
|
|
||||||
|
<enum>s used for this purpose can still be used as normal enums. And can even
|
||||||
|
have variant-specific values referencing another <enum>. Example:
|
||||||
|
|
||||||
|
<enum name="grobj-class" bare="yes" prefix="chipset">
|
||||||
|
<value name="MEMORY_TO_MEMORY_FORMAT" value="0x0039" variants=":NV50" />
|
||||||
|
<value name="MEMORY_TO_MEMORY_FORMAT" value="0x5039" variants="NV50-" />
|
||||||
|
<value name="2D" value="0x502d" variants="NV50-" />
|
||||||
|
<value name="TCL" value="0x5097" variants="NV50:NVA0" />
|
||||||
|
<value name="TCL" value="0x8297" variants="NV84" />
|
||||||
|
<value name="COMPUTE" value="0x50c0" variants="NV50-" />
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
In generated .h file, this will result in:
|
||||||
|
|
||||||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT 0x0039
|
||||||
|
#define NV50_MEMORY_TO_MEMORY_FORMAT 0x5039
|
||||||
|
#define NV50_2D 0x502d
|
||||||
|
#define NV50_TCL 0x5097
|
||||||
|
#define NV84_TCL 0x8297
|
||||||
|
#define NV50_COMPUTE 0x50c0
|
||||||
|
|
||||||
|
2.5. Bitfields
|
||||||
|
|
||||||
|
Often, registers store not a single full-width value, but are split into
|
||||||
|
bitfields. Like values can be grouped in enums, bitfields can be called in
|
||||||
|
bitsets. The <bitset> tag has the same set of attributes as <enum> tag, and
|
||||||
|
contains <bitfield> tags with the following attributes:
|
||||||
|
|
||||||
|
- name [required]: name of the bitfield
|
||||||
|
- low [required]: index of the lowest bit belonging to this bitfield. bits
|
||||||
|
are counted from 0, LSB-first.
|
||||||
|
- high [required]: index of the highest bit belonging to this bitfield.
|
||||||
|
- varset [optional]: like in <reg*>
|
||||||
|
- variants [optional]: like in <reg*>
|
||||||
|
- type [optional]: like in <reg*>
|
||||||
|
- shr [optional]: like in <reg*>
|
||||||
|
|
||||||
|
Like <value>s, <bitfield>s are also allowed to be written directly inside
|
||||||
|
<reg*> tags.
|
||||||
|
|
||||||
|
<bitfield>s themselves can contain <value>s. The defines generated for
|
||||||
|
<bitfield>s include "name__MASK" equal to the bitmask corresponding to given
|
||||||
|
bitfield, "name__SHIFT" equal to the low attribute, "name__SHR" equal to
|
||||||
|
the shr attribute [if defined]. Single-bit bitfields with type "boolean" are
|
||||||
|
treated specially, and get "name" defined to the bitmask instead. If the
|
||||||
|
bitfield contains any <value>s, <bitfield>s, or references an inlined
|
||||||
|
enum/bitset, defines for them are also generated, pre-shifted to the correct
|
||||||
|
position. Example:
|
||||||
|
|
||||||
|
<enum name="nv03_operation" inline="yes">
|
||||||
|
<value value="0" name="SRCCOPY_AND" />
|
||||||
|
<value value="1" name="ROP_AND" />
|
||||||
|
<value value="2" name="BLEND_AND" />
|
||||||
|
<value value="3" name="SRCCOPY" />
|
||||||
|
<value value="4" name="SRCCOPY_PRE" />
|
||||||
|
<value value="5" name="BLEND_PRE" />
|
||||||
|
</enum>
|
||||||
|
|
||||||
|
<bitset name="NV04_GROBJ_1">
|
||||||
|
<bitfield high="7" low="0" name="GRCLASS" />
|
||||||
|
<bitfield high="12" low="12" name="CHROMA_KEY" />
|
||||||
|
<bitfield high="13" low="13" name="USER_CLIP" />
|
||||||
|
<bitfield high="14" low="14" name="SWIZZLE" />
|
||||||
|
<bitfield high="17" low="15" name="PATCH_CONFIG" type="nv03_operation" />
|
||||||
|
<!-- ... -->
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="xy16" inline="yes">
|
||||||
|
<bitfield high="15" low="0" name="X" />
|
||||||
|
<bitfield high="31" low="16" name="Y" />
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<bitset name="nv50_vic" inline="yes">
|
||||||
|
<bitfield high="0" low="0" name="X"/>
|
||||||
|
<bitfield high="1" low="1" name="Y"/>
|
||||||
|
<bitfield high="2" low="2" name="Z"/>
|
||||||
|
<bitfield high="3" low="3" name="W"/>
|
||||||
|
</bitset>
|
||||||
|
|
||||||
|
<reg32 offset="0x40014c" name="PGRAPH_CTX_SWITCH_1" type="NV04_GROBJ_1" />
|
||||||
|
|
||||||
|
<reg32 offset="0x0404" name="FORMAT">
|
||||||
|
<bitfield high="15" low="0" name="PITCH" />
|
||||||
|
<bitfield high="23" low="16" name="ORIGIN" />
|
||||||
|
<bitfield high="31" low="24" name="FILTER" />
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
<reg32 offset="0x040c" name="POINT" type="xy16" />
|
||||||
|
|
||||||
|
<reg32 offset="0x1988" name="FP_INTERPOLANT_CTRL">
|
||||||
|
<bitfield name="UMASK" high="31" low="24" type="nv50_vic"/>
|
||||||
|
<bitfield name="COUNT_NONFLAT" high="23" low="16" type="int"/>
|
||||||
|
<bitfield name="OFFSET" high="15" low="8" type="int"/>
|
||||||
|
<bitfield name="COUNT" high="7" low="0" type="int"/>
|
||||||
|
</reg32>
|
||||||
|
|
||||||
|
Result:
|
||||||
|
|
||||||
|
#define NV04_GROBJ_1_GRCLASS__MASK 0x000000ff
|
||||||
|
#define NV04_GROBJ_1_GRCLASS__SHIFT 0
|
||||||
|
#define NV04_GROBJ_1_CHROMA_KEY 0x00001000
|
||||||
|
#define NV04_GROBJ_1_USER_CLIP 0x00002000
|
||||||
|
#define NV04_GROBJ_1_SWIZZLE 0x00004000
|
||||||
|
#define NV04_GROBJ_1_PATCH_CONFIG__MASK 0x00038000
|
||||||
|
#define NV04_GROBJ_1_PATCH_CONFIG__SHIFT 15
|
||||||
|
#define NV04_GROBJ_1_PATCH_CONFIG_SRCCOPY_AND 0x00000000
|
||||||
|
#define NV04_GROBJ_1_PATCH_CONFIG_ROP_AND 0x00008000
|
||||||
|
#define NV04_GROBJ_1_PATCH_CONFIG_BLEND_AND 0x00010000
|
||||||
|
#define NV04_GROBJ_1_PATCH_CONFIG_SRCCOPY 0x00018000
|
||||||
|
#define NV04_GROBJ_1_PATCH_CONFIG_SRCCOPY_PRE 0x00020000
|
||||||
|
#define NV04_GROBJ_1_PATCH_CONFIG_BLEND_PRE 0x00028000
|
||||||
|
|
||||||
|
#define PGRAPH_CTX_SWITCH_1 0x40014c
|
||||||
|
|
||||||
|
#define FORMAT 0x0404
|
||||||
|
#define FORMAT_PITCH__MASK 0x0000ffff
|
||||||
|
#define FORMAT_PITCH__SHIFT 0
|
||||||
|
#define FORMAT_ORIGIN__MASM 0x00ff0000
|
||||||
|
#define FORMAT_ORIGIN__SHIFT 16
|
||||||
|
#define FORMAT_FILTER__MASK 0xff000000
|
||||||
|
#define FORMAT_FILTER__SHIFT 24
|
||||||
|
|
||||||
|
#define POINT 0x040c
|
||||||
|
#define POINT_X 0x0000ffff
|
||||||
|
#define POINT_X__SHIFT 0
|
||||||
|
#define POINT_Y 0xffff0000
|
||||||
|
#define POINT_Y__SHIFT 16
|
||||||
|
|
||||||
|
#define FP_INTERPOLANT_CTRL 0x00001988
|
||||||
|
#define FP_INTERPOLANT_CTRL_UMASK__MASK 0xff000000
|
||||||
|
#define FP_INTERPOLANT_CTRL_UMASK__SHIFT 24
|
||||||
|
#define FP_INTERPOLANT_CTRL_UMASK_X 0x01000000
|
||||||
|
#define FP_INTERPOLANT_CTRL_UMASK_Y 0x02000000
|
||||||
|
#define FP_INTERPOLANT_CTRL_UMASK_Z 0x04000000
|
||||||
|
#define FP_INTERPOLANT_CTRL_UMASK_W 0x08000000
|
||||||
|
#define FP_INTERPOLANT_CTRL_COUNT_NONFLAT__MASK 0x00ff0000
|
||||||
|
#define FP_INTERPOLANT_CTRL_COUNT_NONFLAT__SHIFT 16
|
||||||
|
#define FP_INTERPOLANT_CTRL_OFFSET__MASK 0x0000ff00
|
||||||
|
#define FP_INTERPOLANT_CTRL_OFFSET__SHIFT 8
|
||||||
|
#define FP_INTERPOLANT_CTRL_COUNT__MASK 0x000000ff
|
||||||
|
#define FP_INTERPOLANT_CTRL_COUNT__SHIFT 0
|
||||||
|
|
||||||
|
2.6. Arrays and stripes.
|
||||||
|
|
||||||
|
Sometimes you have multiple copies of a register. Sometimes you actually have
|
||||||
|
multiple copies of a whole set of registers. And sometimes this set itself
|
||||||
|
contains multiple copies of something. This is what <array>s are for. The
|
||||||
|
<array> represents "length" units, each of size "stride" packed next to each
|
||||||
|
other starting at "offset". Offsets of everything inside the array are
|
||||||
|
relative to start of an element of the array. The <array> attributes include:
|
||||||
|
|
||||||
|
- name [required]: name of the array, also used as prefix for all items
|
||||||
|
inside it
|
||||||
|
- offset [required]: starting offset of the array.
|
||||||
|
- stride [required]: size of a single element of the array, as well as the
|
||||||
|
difference between offsets of two neighboring elements
|
||||||
|
- length [required]: Number of elements in the array
|
||||||
|
- varset [optional]: As in <reg*>
|
||||||
|
- variants [optional]: As in <reg*>
|
||||||
|
|
||||||
|
The definitions emitted for an array include:
|
||||||
|
- name(i) defined to be the starting offset of element i, if length > 1
|
||||||
|
- name defined to be the starting offset of arrayi, if length == 1
|
||||||
|
- name__LEN defined to be the length of array
|
||||||
|
- name__ESIZE defined to be the stride of array
|
||||||
|
|
||||||
|
Also, if length is not 1, definitions for all items inside the array that
|
||||||
|
involve offsets become parameter-taking C macros that calculate the offset
|
||||||
|
based on array index. For nested arrays, this macro takes as many arguments
|
||||||
|
as there are indices involved.
|
||||||
|
|
||||||
|
It's an error if an item inside an array doesn't fit inside the array element.
|
||||||
|
|
||||||
|
<array offset="0x408000" name="PGRAPH_TP" stride="0x1000" length="8">
|
||||||
|
<array offset="0x200" name="MP" stride="0x80" length="2">
|
||||||
|
<!-- ... -->
|
||||||
|
<reg64 offset="0x70" name="TRAPPED_OPCODE" />
|
||||||
|
<!-- ... -->
|
||||||
|
</array>
|
||||||
|
<reg32 offset="0x314" name="MP_TRAP />
|
||||||
|
<!-- ... -->
|
||||||
|
</array>
|
||||||
|
|
||||||
|
#define PGRAPH_TP(i) (0x408000+(i)*0x1000)
|
||||||
|
#define PGRAPH_TP__LEN 8
|
||||||
|
#define PGRAPH_TP__ESIZE 0x1000
|
||||||
|
#define PGRAPH_TP_MP(i,j) (0x408200+(i)*0x1000+(j)*0x80)
|
||||||
|
#define PGRAPH_TP__LEN 2
|
||||||
|
#define PGRAPH_TP__ESIZE 0x80
|
||||||
|
#define PGRAPH_TP_MP_TRAPPED_OPCODE(i,j) (0x408270+(i)*0x1000+(j)*0x80)
|
||||||
|
|
||||||
|
<stripe>s are somewhat similar to arrays, but don't reserve space, merely say
|
||||||
|
that all items inside come in "length" copies "stride" cells apart. As opposed
|
||||||
|
to <array>s, items can have offsets larger than stride, and offsets aren't
|
||||||
|
automatically assumed to be a part of <stripe> unless a <reg*> explicitely
|
||||||
|
hits that particular offset for some index. Also, <stripe>s of length 1 and
|
||||||
|
stride 0 can be used as generic container, for example to apply a variant set
|
||||||
|
or a prefix to a bigger set of elements. Attributes:
|
||||||
|
|
||||||
|
- name [optional]: like in <array>. If not given, no prefixing happens, and
|
||||||
|
the defines for <stripe> itself aren't emitted.
|
||||||
|
- offset [optional]: like <array>. Defaults to 0 if unspecified.
|
||||||
|
- stride [optional]: the difference between offsets of items with indices i
|
||||||
|
and i+1. Or size of the <stripe> if it makes sense in that particular
|
||||||
|
context. Defaults to 0.
|
||||||
|
- length [optional]: like in array. Defaults to 1.
|
||||||
|
- varset [optional]: as in <reg*>
|
||||||
|
- variants [optional]: as in <reg*>
|
||||||
|
- prefix [optional]: as in <domain>, overrides parent's prefix option.
|
||||||
|
|
||||||
|
Definitions are emitted like for arrays, but:
|
||||||
|
- if no name is given, the definitions for stripe itself won't be emitted
|
||||||
|
- if length is 0, the length is assumed to be unknown or undefined. No __LEN
|
||||||
|
is emitted in this case.
|
||||||
|
- if stride is 0, __ESIZE is not emitted
|
||||||
|
- it's an error to have stride 0 with length different than 1
|
||||||
|
|
||||||
|
|
||||||
|
Examples:
|
||||||
|
|
||||||
|
<stripe name="PGRAPH" offset="0x400000" variants="NV04-NV05">
|
||||||
|
<reg32 offset="0x100" name="INTR" />
|
||||||
|
<reg32 offset="0x140" name="INTR_EN" />
|
||||||
|
</stripe>
|
||||||
|
|
||||||
|
<stripe name="PGRAPH" offset="0x400000" variants="NV50-">
|
||||||
|
<reg32 offset="0x100" name="INTR" />
|
||||||
|
<reg32 offset="0x108" name="TRAP" />
|
||||||
|
<reg32 offset="0x138" name="TRAP_EN" />
|
||||||
|
<reg32 offset="0x13c" name="INTR_EN" />
|
||||||
|
</stripe>
|
||||||
|
|
||||||
|
Results in:
|
||||||
|
|
||||||
|
#define NV04_PGRAPH 0x400000
|
||||||
|
#define NV04_PGRAPH_INTR 0x400100
|
||||||
|
#define NV04_PGRAPH_INTR_EN 0x400140
|
||||||
|
#define NV50_PGRAPH 0x400000
|
||||||
|
#define NV50_PGRAPH_INTR 0x400100
|
||||||
|
#define NV50_PGRAPH_TRAP 0x400108
|
||||||
|
#define NV50_PGRAPH_TRAP_EN 0x400138
|
||||||
|
#define NV50_PGRAPH_INTR_EN 0x40013c
|
||||||
|
|
||||||
|
<stripe name="PVIDEO" offset="0x8000">
|
||||||
|
<stripe offset="0x900" stride="4" length="2">
|
||||||
|
<reg32 offset="0" name="BASE" />
|
||||||
|
<reg32 offset="8" name="LIMIT" />
|
||||||
|
<reg32 offset="0x10" name="LUMINANCE" />
|
||||||
|
<reg32 offset="0x18" name="CHROMINANCE" />
|
||||||
|
<!-- ... -->
|
||||||
|
</stripe>
|
||||||
|
</stripe>
|
||||||
|
|
||||||
|
Results in:
|
||||||
|
|
||||||
|
#define PVIDEO_BASE (0x8900+(i)*4)
|
||||||
|
#define PVIDEO_LIMIT (0x8908+(i)*4)
|
||||||
|
#define PVIDEO_LUMINANCE (0x8910+(i)*4)
|
||||||
|
#define PVIDEO_CHROMINANCE (0x8918+(i)*4)
|
||||||
|
|
||||||
|
<domain name="NV_OBJECT" bare="yes">
|
||||||
|
<stripe name="OBJECT" prefix="chipset">
|
||||||
|
<reg32 offset="0x00" name="NAME" />
|
||||||
|
<reg32 offset="0x10" name="FENCE_ADDRESS_HIGH" variants="NV50-" />
|
||||||
|
<!-- more PFIFO methods -->
|
||||||
|
</stripe>
|
||||||
|
<stripe prefix="grobj-class">
|
||||||
|
<stripe variants="NV04_MEMORY_TO_MEMORY_FORMAT-NV05_MEMORY_TO_MEMORY_FORMAT">
|
||||||
|
<reg32 offset="0x200" name="LINEAR_IN" variants="NV50_MEMORY_TO_MEMORY_FORMAT" />
|
||||||
|
<reg32 offset="0x328" name="BUFFER_NOTIFY" />
|
||||||
|
<!-- more m2mf methods -->
|
||||||
|
</stripe>
|
||||||
|
<stripe variants="NV50_COMPUTE">
|
||||||
|
<reg32 offset="0x368" name="LAUNCH" />
|
||||||
|
<stripe name="GLOBAL" offset="0x400" stride="0x20" length="16">
|
||||||
|
<reg32 offset="0" name="ADDRESS_HIGH" />
|
||||||
|
<reg32 offset="4" name="ADDRESS_LOW" />
|
||||||
|
<reg32 offset="8" name="PITCH" />
|
||||||
|
<reg32 offset="0xc" name="LIMIT" />
|
||||||
|
<reg32 offset="0x10" name="MODE" />
|
||||||
|
</stripe>
|
||||||
|
<!-- more NV50_COMPUTE methods -->
|
||||||
|
<reg32 offset="0x0600" name="USER_PARAM" length="64" />
|
||||||
|
</stripe>
|
||||||
|
</stripe>
|
||||||
|
</domain>
|
||||||
|
|
||||||
|
Results in:
|
||||||
|
|
||||||
|
#define NV01_OBJECT_NAME 0x00
|
||||||
|
#define NV50_OBJECT_FENCE_ADDRESS_HIGH 0x10
|
||||||
|
#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN 0x200
|
||||||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT_BUFFER_NOTIFY 0x328
|
||||||
|
#define NV50_COMPUTE_LAUNCH 0x368
|
||||||
|
#define NV50_COMPUTE_GLOBAL 0x400
|
||||||
|
#define NV50_COMPUTE_GLOBAL__LEN 16
|
||||||
|
#define NV50_COMPUTE_GLOBAL__ESIZE 0x20
|
||||||
|
#define NV50_COMPUTE_GLOBAL_ADDRESS_HIGH (0x400 + (i)*0x20)
|
||||||
|
#define NV50_COMPUTE_GLOBAL_ADDRESS_LOW (0x404 + (i)*0x20)
|
||||||
|
#define NV50_COMPUTE_GLOBAL_PITCH (0x408 + (i)*0x20)
|
||||||
|
#define NV50_COMPUTE_GLOBAL_LIMIT (0x40c + (i)*0x20)
|
||||||
|
#define NV50_COMPUTE_GLOBAL_MODE (0x410 + (i)*0x20)
|
||||||
|
#define NV50_COMPUTE_USER_PARAM(i) (0x600 + (i)*4)
|
||||||
|
#define NV50_COMPUTE_USER_PARAM__LEN 64
|
||||||
|
#define NV50_COMPUTE_USER_PARAM__ESIZE 4
|
||||||
|
|
||||||
|
2.7. Groups
|
||||||
|
|
||||||
|
Groups are just sets of registers and/or arrays that can be copied-and-pasted
|
||||||
|
together, when they're duplicated in several places in the same <domain>,
|
||||||
|
two different <domain>s, or have different offsets for different variants.
|
||||||
|
<group> and <use-group> only have the name attribute. <use-group> can appear
|
||||||
|
wherever <reg*> can, including inside a <group>.
|
||||||
|
|
||||||
|
<group name="nv50_mp">
|
||||||
|
<!-- ... -->
|
||||||
|
<reg64 offset="0x70" name="TRAPPED_OPCODE" />
|
||||||
|
<!-- ... -->
|
||||||
|
</group>
|
||||||
|
|
||||||
|
<array offset="0x408000" name="PGRAPH_TP" stride="0x1000" length="8" variants="NV50:NVA0">
|
||||||
|
<array offset="0x200" name="MP" stride="0x80" length="2">
|
||||||
|
<use-group name="nv50_mp" />
|
||||||
|
</array>
|
||||||
|
<!-- ... -->
|
||||||
|
</array>
|
||||||
|
<array offset="0x408000" name="PGRAPH_TP" stride="0x800" length="10" variants="NVA0-">
|
||||||
|
<array offset="0x100" name="MP" stride="0x80" length="4">
|
||||||
|
<use-group name="nv50_mp" />
|
||||||
|
</array>
|
||||||
|
<!-- ... -->
|
||||||
|
</array>
|
||||||
|
|
||||||
|
Will get you:
|
||||||
|
|
||||||
|
#define NV50_PGRAPH_TP_MP_TRAPPED_OPCODE(i, j) (0x408270 + (i)*0x1000 + (j)*0x80)
|
||||||
|
#define NVA0_PGRAPH_TP_MP_TRAPPED_OPCODE(i, j) (0x408170 + (i)*0x800 + (j)*0x80)
|
||||||
|
|
||||||
|
3. The utilities.
|
||||||
|
|
||||||
|
The header generation utility will take a set of XML files and generate .h
|
||||||
|
file with all of their definitions, as defined above.
|
||||||
|
|
||||||
|
The HTML generation utilty will take an XML file and generate HTML
|
||||||
|
documentation out of it. The documentation will include the <brief> and <doc>
|
||||||
|
tags in some way, as well as information from all the attributes, in some easy
|
||||||
|
to read format. Some naming scheme for the HTML files should be decided, so
|
||||||
|
that cross-refs to HTML documentation generated for <import>ed files will work
|
||||||
|
correctly if the generator is run in both.
|
||||||
|
|
||||||
|
The lookup utility will perform database lookups of the following types:
|
||||||
|
|
||||||
|
- domain name, offset, access type, variant type[s] -> register name + array
|
||||||
|
indices if applicable
|
||||||
|
- the above + register value -> same as above + decoded value. For registers
|
||||||
|
with bitfields, print all bitfields, and indicate if any bits not covered
|
||||||
|
by the bitfields are set to 1. For registers/bitfields with enum values,
|
||||||
|
print the matching one if any. For remaining registers/bitfields, print
|
||||||
|
according to type attribute.
|
||||||
|
- bitset name + value -> decoded value, as above
|
||||||
|
- enum name + value -> decoded value, as above
|
||||||
|
|
||||||
|
The mmio-parse utility will parse a mmio-trace file and apply the second kind
|
||||||
|
of database lookups to all memory accesses matching a given range. Some
|
||||||
|
nv-specific hacks will be in order to automate the parsing: extract the
|
||||||
|
chipset from PMC_BOOT_0, figure out the mmio base from PCI config, etc.
|
||||||
|
|
||||||
|
The renouveau-parse utility will take contents of a PFIFO pushbuffer and
|
||||||
|
decode them. The splitting to method,data pair will be done by nv-specific
|
||||||
|
code, then the pair will be handed over to generic rules-ng lookup.
|
||||||
|
|
||||||
|
4. Issues
|
||||||
|
|
||||||
|
- Random typing-saving feature for bitfields: make high default to same value
|
||||||
|
as low, to have one less attribute for single-bit bitfields?
|
||||||
|
|
||||||
|
- What about allowing nameless registers and/or bitfields? These are
|
||||||
|
supported by renouveau.xml and are used commonly to signify an unknown
|
||||||
|
register.
|
||||||
|
|
||||||
|
- How about cross-ref links in <doc> tags?
|
||||||
|
|
||||||
|
- <translation>: do we need them? Sounds awesome and useful, but as defined
|
||||||
|
by the old spec, they're quite limited. The only examples of straight
|
||||||
|
translations that I know of are the legacy VGA registers and
|
||||||
|
NV50_PFB_VM_TRAP. And NV01_PDAC, but I doubt anybody gives a damn about it.
|
||||||
|
This list is small enough to be just handled by nv-specific hacks in
|
||||||
|
mmio-trace parser if really needed.
|
||||||
|
|
||||||
|
- Another thing that renouveau.xml does is disassembling NV20-NV40 shaders.
|
||||||
|
Do we want that in rules-ng? IMO we'd be better off hacking nv50dis to
|
||||||
|
support it...
|
|
@ -0,0 +1,388 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<schema xmlns="http://www.w3.org/2001/XMLSchema"
|
||||||
|
targetNamespace="http://nouveau.freedesktop.org/"
|
||||||
|
xmlns:rng="http://nouveau.freedesktop.org/"
|
||||||
|
elementFormDefault="qualified">
|
||||||
|
|
||||||
|
<annotation>
|
||||||
|
<documentation>
|
||||||
|
An updated version of the old rules.xml file from the
|
||||||
|
RivaTV project. Specifications by Pekka Paalanen,
|
||||||
|
preliminary attempt by KoalaBR,
|
||||||
|
first working version by Jakob Bornecrantz.
|
||||||
|
For specifications, see the file rules-ng-format.txt
|
||||||
|
in Nouveau CVS module 'rules-ng'.
|
||||||
|
</documentation>
|
||||||
|
<documentation>Version 0.1</documentation>
|
||||||
|
</annotation>
|
||||||
|
|
||||||
|
|
||||||
|
<!-- Elements -->
|
||||||
|
|
||||||
|
<element name="database" type="rng:databaseType" />
|
||||||
|
<element name="import" type="rng:importType" />
|
||||||
|
<element name="domain" type="rng:domainType" />
|
||||||
|
<element name="group" type="rng:groupType" />
|
||||||
|
<element name="use-group" type="rng:refType" />
|
||||||
|
<element name="array" type="rng:arrayType" />
|
||||||
|
<element name="stripe" type="rng:stripeType" />
|
||||||
|
<element name="reg64" type="rng:registerType" />
|
||||||
|
<element name="reg32" type="rng:registerType" />
|
||||||
|
<element name="reg16" type="rng:registerType" />
|
||||||
|
<element name="reg8" type="rng:registerType" />
|
||||||
|
<element name="bitset" type="rng:bitsetType" />
|
||||||
|
<element name="bitfield" type="rng:bitfieldType" />
|
||||||
|
<element name="enum" type="rng:enumType" />
|
||||||
|
<element name="value" type="rng:valueType" />
|
||||||
|
|
||||||
|
<!-- Documentation elements -->
|
||||||
|
|
||||||
|
<!-- FIXME: allowed only one per parent element -->
|
||||||
|
<element name="brief" type="rng:briefType" />
|
||||||
|
|
||||||
|
<element name="doc" type="rng:docType" />
|
||||||
|
<element name="b" type="rng:textformatType" />
|
||||||
|
<element name="i" type="rng:textformatType" />
|
||||||
|
<element name="u" type="rng:textformatType" />
|
||||||
|
<element name="code" type="rng:textcodeType" />
|
||||||
|
<element name="ul" type="rng:listType" />
|
||||||
|
<element name="ol" type="rng:listType" />
|
||||||
|
<element name="li" type="rng:listitemType" />
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
<!-- Database element types -->
|
||||||
|
|
||||||
|
<complexType name="databaseType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>databaseType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
</choice>
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="importType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>importType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<attribute name="file" type="string" use="required" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="domainType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>domainType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
<group ref="rng:regarrayGroup" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="required" />
|
||||||
|
<attribute name="bare" type="boolean" use="optional" />
|
||||||
|
<attribute name="prefix" type="NMTOKENS" use="optional" />
|
||||||
|
<attribute name="width" type="rng:DomainWidth" use="optional" />
|
||||||
|
<attribute name="size" type="rng:Hexadecimal" use="optional" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="groupType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>groupType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
<group ref="rng:regarrayGroup" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="required" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="arrayType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>arrayType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
<group ref="rng:regarrayGroup" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="required" />
|
||||||
|
<attribute name="offset" type="rng:Hexadecimal" use="required" />
|
||||||
|
<attribute name="stride" type="rng:HexOrNumber" use="required" />
|
||||||
|
<attribute name="length" type="rng:HexOrNumber" use="required" />
|
||||||
|
<attribute name="varset" type="NMTOKEN" use="optional" />
|
||||||
|
<attribute name="variants" type="string" use="optional" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="stripeType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>stripeType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
<group ref="rng:regarrayGroup" minOccurs="0" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="optional" />
|
||||||
|
<attribute name="offset" type="rng:Hexadecimal" use="optional" />
|
||||||
|
<attribute name="stride" type="rng:HexOrNumber" use="optional" />
|
||||||
|
<attribute name="length" type="rng:HexOrNumber" use="optional" />
|
||||||
|
<attribute name="varset" type="NMTOKEN" use="optional" />
|
||||||
|
<attribute name="variants" type="string" use="optional" />
|
||||||
|
<attribute name="prefix" type="NMTOKENS" use="optional" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="registerType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>
|
||||||
|
registerType used by reg8, reg16, reg32, reg64
|
||||||
|
</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
<element ref="rng:value" />
|
||||||
|
<element ref="rng:bitfield" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="required" />
|
||||||
|
<attribute name="offset" type="rng:Hexadecimal" use="required" />
|
||||||
|
<attribute name="access" type="rng:Access" default="rw" use="optional" />
|
||||||
|
<attribute name="type" type="NMTOKENS" use="optional" />
|
||||||
|
<attribute name="shr" type="nonNegativeInteger" use="optional" />
|
||||||
|
<attribute name="varset" type="NMTOKEN" use="optional" />
|
||||||
|
<attribute name="variants" type="string" use="optional" />
|
||||||
|
<attribute name="stride" type="rng:HexOrNumber" use="optional" />
|
||||||
|
<attribute name="length" type="rng:HexOrNumber" use="optional" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="bitsetType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>bitsetType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice maxOccurs="unbounded">
|
||||||
|
<element ref="rng:bitfield" />
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="required" />
|
||||||
|
<attribute name="inline" type="boolean" use="optional" />
|
||||||
|
<attribute name="bare" type="boolean" use="optional" />
|
||||||
|
<attribute name="prefix" type="NMTOKENS" use="optional" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="bitfieldType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>bitfieldType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<element ref="rng:value" maxOccurs="unbounded" />
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="required" />
|
||||||
|
<attribute name="high" type="nonNegativeInteger" use="required" />
|
||||||
|
<attribute name="low" type="nonNegativeInteger" use="required" />
|
||||||
|
<attribute name="type" type="NMTOKENS" use="optional" />
|
||||||
|
<attribute name="varset" type="NMTOKEN" use="optional" />
|
||||||
|
<attribute name="variants" type="string" use="optional" />
|
||||||
|
<attribute name="shr" type="nonNegativeInteger" use="optional" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="enumType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>enumType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice maxOccurs="unbounded">
|
||||||
|
<element ref="rng:value" />
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="required" />
|
||||||
|
<attribute name="inline" type="boolean" use="optional" />
|
||||||
|
<attribute name="bare" type="boolean" use="optional" />
|
||||||
|
<attribute name="prefix" type="NMTOKENS" use="optional" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="valueType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>valueType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:docGroup" />
|
||||||
|
<group ref="rng:topGroup" />
|
||||||
|
</choice>
|
||||||
|
<attribute name="name" type="NMTOKEN" use="required" />
|
||||||
|
<attribute name="value" type="string" use="optional" />
|
||||||
|
<attribute name="varset" type="NMTOKEN" use="optional" />
|
||||||
|
<attribute name="variants" type="string" use="optional" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="refType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>refType</documentation>
|
||||||
|
</annotation>
|
||||||
|
<attribute name="ref" type="NMTOKEN" use="required" />
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
|
||||||
|
<!-- Documentation element types -->
|
||||||
|
|
||||||
|
<complexType name="briefType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>
|
||||||
|
brief documentation, no markup
|
||||||
|
</documentation>
|
||||||
|
</annotation>
|
||||||
|
<simpleContent>
|
||||||
|
<extension base="string" />
|
||||||
|
</simpleContent>
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="docType" mixed="true">
|
||||||
|
<annotation>
|
||||||
|
<documentation>
|
||||||
|
root element of documentation sub-tree
|
||||||
|
</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:textformatGroup" />
|
||||||
|
<group ref="rng:listGroup" />
|
||||||
|
<element ref="rng:code" />
|
||||||
|
</choice>
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="textformatType" mixed="true">
|
||||||
|
<annotation>
|
||||||
|
<documentation>
|
||||||
|
for bold, underline, italics
|
||||||
|
</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:textformatGroup" />
|
||||||
|
</choice>
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="textcodeType">
|
||||||
|
<simpleContent>
|
||||||
|
<extension base="string">
|
||||||
|
<attribute name="title" type="string" />
|
||||||
|
</extension>
|
||||||
|
</simpleContent>
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="listType">
|
||||||
|
<annotation>
|
||||||
|
<documentation>
|
||||||
|
definition of a list, ordered or unordered
|
||||||
|
</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<element ref="rng:li" />
|
||||||
|
</choice>
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
<complexType name="listitemType" mixed="true">
|
||||||
|
<annotation>
|
||||||
|
<documentation>
|
||||||
|
items of a list
|
||||||
|
</documentation>
|
||||||
|
</annotation>
|
||||||
|
<choice minOccurs="0" maxOccurs="unbounded">
|
||||||
|
<group ref="rng:textformatGroup" />
|
||||||
|
<group ref="rng:listGroup" />
|
||||||
|
<element ref="rng:code" />
|
||||||
|
</choice>
|
||||||
|
</complexType>
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
<!-- Attribute value types -->
|
||||||
|
|
||||||
|
<simpleType name="Hexadecimal">
|
||||||
|
<restriction base="string">
|
||||||
|
<pattern value="0x[0-9a-f]+" />
|
||||||
|
<pattern value="0x[0-9A-F]+" />
|
||||||
|
<pattern value="[0-9]" />
|
||||||
|
</restriction>
|
||||||
|
</simpleType>
|
||||||
|
|
||||||
|
<simpleType name="HexOrNumber">
|
||||||
|
<annotation>
|
||||||
|
<documentation>HexOrNumber</documentation>
|
||||||
|
</annotation>
|
||||||
|
<union memberTypes="rng:Hexadecimal nonNegativeInteger" />
|
||||||
|
</simpleType>
|
||||||
|
|
||||||
|
<simpleType name="Access">
|
||||||
|
<annotation>
|
||||||
|
<documentation>Access</documentation>
|
||||||
|
</annotation>
|
||||||
|
<restriction base="string">
|
||||||
|
<enumeration value="r" />
|
||||||
|
<enumeration value="w" />
|
||||||
|
<enumeration value="rw" />
|
||||||
|
</restriction>
|
||||||
|
</simpleType>
|
||||||
|
|
||||||
|
<simpleType name="DomainWidth">
|
||||||
|
<annotation>
|
||||||
|
<documentation>DomainWidth</documentation>
|
||||||
|
</annotation>
|
||||||
|
<restriction base="string">
|
||||||
|
<enumeration value="8" />
|
||||||
|
<enumeration value="16" />
|
||||||
|
<enumeration value="32" />
|
||||||
|
<enumeration value="64" />
|
||||||
|
</restriction>
|
||||||
|
</simpleType>
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
<!-- Element groups -->
|
||||||
|
|
||||||
|
<group name="topGroup">
|
||||||
|
<choice>
|
||||||
|
<element ref="rng:domain" />
|
||||||
|
<element ref="rng:enum" />
|
||||||
|
<element ref="rng:group" />
|
||||||
|
<element ref="rng:bitset" />
|
||||||
|
<element ref="rng:import" />
|
||||||
|
</choice>
|
||||||
|
</group>
|
||||||
|
|
||||||
|
<group name="regarrayGroup">
|
||||||
|
<choice>
|
||||||
|
<element ref="rng:reg64" />
|
||||||
|
<element ref="rng:reg32" />
|
||||||
|
<element ref="rng:reg16" />
|
||||||
|
<element ref="rng:reg8" />
|
||||||
|
<element ref="rng:array" />
|
||||||
|
<element ref="rng:stripe" />
|
||||||
|
<element ref="rng:use-group" />
|
||||||
|
</choice>
|
||||||
|
</group>
|
||||||
|
|
||||||
|
<group name="docGroup">
|
||||||
|
<choice>
|
||||||
|
<element ref="rng:brief" />
|
||||||
|
<element ref="rng:doc" />
|
||||||
|
</choice>
|
||||||
|
</group>
|
||||||
|
|
||||||
|
<group name="textformatGroup">
|
||||||
|
<choice>
|
||||||
|
<element ref="rng:b" />
|
||||||
|
<element ref="rng:i" />
|
||||||
|
<element ref="rng:u" />
|
||||||
|
</choice>
|
||||||
|
</group>
|
||||||
|
|
||||||
|
<group name="listGroup">
|
||||||
|
<choice>
|
||||||
|
<element ref="rng:ul" />
|
||||||
|
<element ref="rng:ol" />
|
||||||
|
</choice>
|
||||||
|
</group>
|
||||||
|
|
||||||
|
</schema>
|
|
@ -0,0 +1,101 @@
|
||||||
|
1. Introduction to rules-ng-ng text format
|
||||||
|
|
||||||
|
This-specification defines a text format that can be converted to and from rules-ng-ng XML.
|
||||||
|
It is intended to allow to create rules-ng-ng files with much less typing and with a more readable text.
|
||||||
|
xml2text can convert rules-ng-ng XML to this text format
|
||||||
|
text2xml can convert this text format to rules-ng-ng XML
|
||||||
|
|
||||||
|
This specification is an addendum to the rules-ng-ng specification and assumes familiarity with it.
|
||||||
|
|
||||||
|
2. Format
|
||||||
|
|
||||||
|
2.1. Line format
|
||||||
|
|
||||||
|
The initial indentation of a line is divided by 8 and the result determines the position in the document structure (similar to the Python language).
|
||||||
|
A "//" anywhere in the line causes the rest to be converted to an XML comment (like C++)
|
||||||
|
A line starting with ":" creates a <doc> tag with the rest of the line (excluding anything starting with //).
|
||||||
|
The content of multiple lines starting with ":" is merged in a single <doc> tag.
|
||||||
|
|
||||||
|
2.2. Tokenization
|
||||||
|
|
||||||
|
The line is then tokenized.
|
||||||
|
Token are generally continuous strings on non-whitespace characters, with some exceptions
|
||||||
|
Some characters (such as ":", "=" and "-") form a single-character token.
|
||||||
|
Text within double quotes generates a <brief> tag.
|
||||||
|
Any token formatted as ATTR(VALUE) generates an ATTR="VALUE" attribute. No whitespace allowed between ATTR and the '(' character.
|
||||||
|
Any token formatted as (VALUE) generates a variants="VALUE" attribute.
|
||||||
|
Any token formatted as (VARSET=VALUE) generates a varset="VARSET" variants="VALUE" attribute.
|
||||||
|
|
||||||
|
2.3. Special token sequences
|
||||||
|
|
||||||
|
These sequences are recognized and extracted before matching the line format:
|
||||||
|
|
||||||
|
: NUM
|
||||||
|
set REGLIKE to regNUM
|
||||||
|
you must specify a type if the reg is anonymous
|
||||||
|
the : is recognized only if it is the third or successive token (and not the last) to avoid ambiguity with bitfields and generic tags
|
||||||
|
|
||||||
|
{ STRIDE }
|
||||||
|
stride="STRIDE" attribute
|
||||||
|
|
||||||
|
[ LENGTH ]
|
||||||
|
length="LENGTH" attribute
|
||||||
|
|
||||||
|
!FLAGS
|
||||||
|
access="FLAGS"
|
||||||
|
no whitespace allowed after '!'
|
||||||
|
|
||||||
|
:=
|
||||||
|
at the end of the line
|
||||||
|
set REGLIKE to "stripe"
|
||||||
|
|
||||||
|
=
|
||||||
|
at the end of the line
|
||||||
|
set REGLIKE to "array"
|
||||||
|
|
||||||
|
inline
|
||||||
|
at the beginning of the line
|
||||||
|
inline="yes" attribute
|
||||||
|
|
||||||
|
2.4. Line patterns
|
||||||
|
|
||||||
|
The following line patterns are understood.
|
||||||
|
Only word tokens are used to match lines.
|
||||||
|
All tokens with special meaning are treated separately as described above.
|
||||||
|
[FOO] means that FOO is optional
|
||||||
|
|
||||||
|
#import "FILE"
|
||||||
|
<import file="FILE"/>
|
||||||
|
|
||||||
|
#pragma regNUM
|
||||||
|
REGLIKE is now set by default to regNUM instead of reg32
|
||||||
|
|
||||||
|
@TAG [NAME]
|
||||||
|
<TAG name="NAME"/>
|
||||||
|
use this if there are no children
|
||||||
|
|
||||||
|
TAG [NAME] :
|
||||||
|
<TAG name="NAME">
|
||||||
|
use this if there are children
|
||||||
|
|
||||||
|
TOKEN
|
||||||
|
<value value="TOKEN" /> if inside a reg or enum and TOKEN starts with a digit
|
||||||
|
<value name="TOKEN" /> if inside a reg or enum and TOKEN does not start with a digit
|
||||||
|
<REGLIKE offset="TOKEN" /> otherwise
|
||||||
|
|
||||||
|
POS NAME
|
||||||
|
<bitfield low="POS" high="POS" name="NAME"/> if inside a reg or bitset
|
||||||
|
<REGLIKE offset="POS" name="NAME"> otherwise
|
||||||
|
|
||||||
|
LOW - HIGH NAME [TYPE]
|
||||||
|
<bitfield low="LOW" high="HIGH" name="NAME" type="TYPE"/>
|
||||||
|
|
||||||
|
VALUE = NAME
|
||||||
|
<value value="VALUE" name="NAME"/>
|
||||||
|
|
||||||
|
use WHAT NAME
|
||||||
|
<use-WHAT name="NAME" />
|
||||||
|
|
||||||
|
OFFSET NAME [TYPE]
|
||||||
|
<REGLIKE offset="OFFSET" name="NAME" type="TYPE">
|
||||||
|
|
|
@ -1,14 +0,0 @@
|
||||||
#!/bin/sh
|
|
||||||
|
|
||||||
d=$(dirname $0)
|
|
||||||
|
|
||||||
rnndb=$1
|
|
||||||
|
|
||||||
if [ ! -f $rnndb/rnndb/adreno/adreno_common.xml ]; then
|
|
||||||
echo directory does not look like envytools: $rnndb
|
|
||||||
exit 1
|
|
||||||
fi
|
|
||||||
|
|
||||||
for f in $d/*.xml.h; do
|
|
||||||
cp -v $rnndb/rnndb/adreno/$(basename $f) $d
|
|
||||||
done
|
|
Loading…
Reference in New Issue