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gallium: remove structure u_resource 

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10659>
This commit is contained in:
Marek Olšák 2021-05-05 16:21:56 -04:00 committed by Marge Bot
parent 2670efa1f7
commit b6d47f482c
34 changed files with 329 additions and 339 deletions
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6
src/gallium/auxiliary/util/u_transfer.c
View File

@ -91,9 +91,3 @@ void u_default_transfer_flush_region(UNUSED struct pipe_context *pipe,
/* This is a no-op implementation, nothing to do.
*/
}
static inline struct u_resource *
u_resource( struct pipe_resource *res )
{
return (struct u_resource *)res;
}

4
src/gallium/auxiliary/util/u_transfer.h
View File

@ -29,10 +29,6 @@ void u_default_transfer_flush_region( struct pipe_context *pipe,
struct pipe_transfer *transfer,
const struct pipe_box *box);
struct u_resource {
struct pipe_resource b;
};
#ifdef __cplusplus
} // extern "C" {
#endif

12
src/gallium/drivers/i915/i915_clear.c
View File

@ -64,7 +64,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
cbuf_tex = i915_texture(cbuf->texture);
util_pack_color(color->f, cbuf->format, &u_color);
if (util_format_get_blocksize(cbuf_tex->b.b.format) == 4) {
if (util_format_get_blocksize(cbuf_tex->b.format) == 4) {
clear_color = u_color.ui[0];
color_clear_bbp = 32;
} else {
@ -87,12 +87,12 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
clear_params |= CLEARPARAM_WRITE_DEPTH;
depth_tex = i915_texture(zbuf->texture);
packed_z_stencil = util_pack_z_stencil(depth_tex->b.b.format, depth, stencil);
packed_z_stencil = util_pack_z_stencil(depth_tex->b.format, depth, stencil);
if (util_format_get_blocksize(depth_tex->b.b.format) == 4) {
if (util_format_get_blocksize(depth_tex->b.format) == 4) {
/* Avoid read-modify-write if there's no stencil. */
if (buffers & PIPE_CLEAR_STENCIL
|| depth_tex->b.b.format != PIPE_FORMAT_Z24_UNORM_S8_UINT) {
|| depth_tex->b.format != PIPE_FORMAT_Z24_UNORM_S8_UINT) {
clear_params |= CLEARPARAM_WRITE_STENCIL;
clear_stencil = packed_z_stencil >> 24;
}
@ -108,9 +108,9 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
clear_params |= CLEARPARAM_WRITE_STENCIL;
depth_tex = i915_texture(zbuf->texture);
assert(depth_tex->b.b.format == PIPE_FORMAT_Z24_UNORM_S8_UINT);
assert(depth_tex->b.format == PIPE_FORMAT_Z24_UNORM_S8_UINT);
packed_z_stencil = util_pack_z_stencil(depth_tex->b.b.format, depth, stencil);
packed_z_stencil = util_pack_z_stencil(depth_tex->b.format, depth, stencil);
depth_clear_bbp = 32;
clear_stencil = packed_z_stencil >> 24;
}

8
src/gallium/drivers/i915/i915_resource.h
View File

@ -40,7 +40,7 @@ struct i915_screen;
struct i915_buffer {
struct u_resource b;
struct pipe_resource b;
uint8_t *data;
boolean free_on_destroy;
};
@ -64,7 +64,7 @@ struct offset_pair {
};
struct i915_texture {
struct u_resource b;
struct pipe_resource b;
/* tiling flags */
enum i915_winsys_buffer_tile tiling;
@ -94,14 +94,14 @@ void i915_init_resource_functions(struct i915_context *i915);
static inline struct i915_texture *i915_texture(struct pipe_resource *resource)
{
struct i915_texture *tex = (struct i915_texture *)resource;
assert(tex->b.b.target != PIPE_BUFFER);
assert(tex->b.target != PIPE_BUFFER);
return tex;
}
static inline struct i915_buffer *i915_buffer(struct pipe_resource *resource)
{
struct i915_buffer *tex = (struct i915_buffer *)resource;
assert(tex->b.b.target == PIPE_BUFFER);
assert(tex->b.target == PIPE_BUFFER);
return tex;
}

30
src/gallium/drivers/i915/i915_resource_buffer.c
View File

@ -118,16 +118,16 @@ i915_buffer_create(struct pipe_screen *screen,
if (!buf)
return NULL;
buf->b.b = *template;
pipe_reference_init(&buf->b.b.reference, 1);
buf->b.b.screen = screen;
buf->b = *template;
pipe_reference_init(&buf->b.reference, 1);
buf->b.screen = screen;
buf->data = align_malloc(template->width0, 64);
buf->free_on_destroy = TRUE;
if (!buf->data)
goto err;
return &buf->b.b;
return &buf->b;
err:
FREE(buf);
@ -147,19 +147,19 @@ i915_user_buffer_create(struct pipe_screen *screen,
if (!buf)
return NULL;
pipe_reference_init(&buf->b.b.reference, 1);
buf->b.b.screen = screen;
buf->b.b.format = PIPE_FORMAT_R8_UNORM; /* ?? */
buf->b.b.usage = PIPE_USAGE_IMMUTABLE;
buf->b.b.bind = bind;
buf->b.b.flags = 0;
buf->b.b.width0 = bytes;
buf->b.b.height0 = 1;
buf->b.b.depth0 = 1;
buf->b.b.array_size = 1;
pipe_reference_init(&buf->b.reference, 1);
buf->b.screen = screen;
buf->b.format = PIPE_FORMAT_R8_UNORM; /* ?? */
buf->b.usage = PIPE_USAGE_IMMUTABLE;
buf->b.bind = bind;
buf->b.flags = 0;
buf->b.width0 = bytes;
buf->b.height0 = 1;
buf->b.depth0 = 1;
buf->b.array_size = 1;
buf->data = ptr;
buf->free_on_destroy = FALSE;
return &buf->b.b;
return &buf->b;
}

62
src/gallium/drivers/i915/i915_resource_texture.c
View File

@ -148,7 +148,7 @@ unsigned i915_texture_offset(const struct i915_texture *tex,
{
unsigned x, y;
x = tex->image_offset[level][layer].nblocksx
* util_format_get_blocksize(tex->b.b.format);
* util_format_get_blocksize(tex->b.format);
y = tex->image_offset[level][layer].nblocksy;
return y * tex->stride + x;
@ -178,10 +178,10 @@ i915_texture_tiling(struct i915_screen *is, struct i915_texture *tex)
if (!is->debug.tiling)
return I915_TILE_NONE;
if (tex->b.b.target == PIPE_TEXTURE_1D)
if (tex->b.target == PIPE_TEXTURE_1D)
return I915_TILE_NONE;
if (util_format_is_s3tc(tex->b.b.format))
if (util_format_is_s3tc(tex->b.format))
return I915_TILE_X;
if (is->debug.use_blitter)
@ -202,7 +202,7 @@ i915_texture_tiling(struct i915_screen *is, struct i915_texture *tex)
static boolean
i9x5_scanout_layout(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
if (pt->last_level > 0 || util_format_get_blocksize(pt->format) != 4)
return FALSE;
@ -237,7 +237,7 @@ i9x5_scanout_layout(struct i915_texture *tex)
static boolean
i9x5_display_target_layout(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
if (pt->last_level > 0 || util_format_get_blocksize(pt->format) != 4)
return FALSE;
@ -268,7 +268,7 @@ i9x5_display_target_layout(struct i915_texture *tex)
static boolean
i9x5_special_layout(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
/* Scanouts needs special care */
if (pt->bind & PIPE_BIND_SCANOUT)
@ -294,7 +294,7 @@ i9x5_special_layout(struct i915_texture *tex)
static void
i9x5_texture_layout_cube(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
unsigned width = util_next_power_of_two(pt->width0);
const unsigned nblocks = util_format_get_nblocksx(pt->format, width);
unsigned level;
@ -332,7 +332,7 @@ i9x5_texture_layout_cube(struct i915_texture *tex)
static void
i915_texture_layout_2d(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
unsigned level;
unsigned width = util_next_power_of_two(pt->width0);
unsigned height = util_next_power_of_two(pt->height0);
@ -360,7 +360,7 @@ i915_texture_layout_2d(struct i915_texture *tex)
static void
i915_texture_layout_3d(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
unsigned level;
unsigned width = util_next_power_of_two(pt->width0);
@ -405,7 +405,7 @@ i915_texture_layout_3d(struct i915_texture *tex)
static boolean
i915_texture_layout(struct i915_texture * tex)
{
switch (tex->b.b.target) {
switch (tex->b.target) {
case PIPE_TEXTURE_1D:
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
@ -435,7 +435,7 @@ i915_texture_layout(struct i915_texture * tex)
static void
i945_texture_layout_2d(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
int align_x = 4, align_y = 2;
unsigned level;
unsigned x = 0;
@ -498,7 +498,7 @@ i945_texture_layout_2d(struct i915_texture *tex)
static void
i945_texture_layout_3d(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
unsigned width = util_next_power_of_two(pt->width0);
unsigned height = util_next_power_of_two(pt->height0);
unsigned depth = util_next_power_of_two(pt->depth0);
@ -553,7 +553,7 @@ i945_texture_layout_3d(struct i915_texture *tex)
static void
i945_texture_layout_cube(struct i915_texture *tex)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
unsigned width = util_next_power_of_two(pt->width0);
const unsigned nblocks = util_format_get_nblocksx(pt->format, width);
const unsigned dim = width;
@ -649,7 +649,7 @@ i945_texture_layout_cube(struct i915_texture *tex)
static boolean
i945_texture_layout(struct i915_texture * tex)
{
switch (tex->b.b.target) {
switch (tex->b.target) {
case PIPE_TEXTURE_1D:
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
@ -660,7 +660,7 @@ i945_texture_layout(struct i915_texture * tex)
i945_texture_layout_3d(tex);
break;
case PIPE_TEXTURE_CUBE:
if (!util_format_is_s3tc(tex->b.b.format))
if (!util_format_is_s3tc(tex->b.format))
i9x5_texture_layout_cube(tex);
else
i945_texture_layout_cube(tex);
@ -781,7 +781,7 @@ i915_texture_transfer_unmap(struct pipe_context *pipe,
struct i915_context *i915 = i915_context(pipe);
struct i915_transfer *itransfer = (struct i915_transfer*)transfer;
struct i915_texture *tex = i915_texture(itransfer->b.resource);
struct i915_winsys *iws = i915_screen(tex->b.b.screen)->iws;
struct i915_winsys *iws = i915_screen(tex->b.screen)->iws;
if (itransfer->staging_texture)
tex = i915_texture(itransfer->staging_texture);
@ -831,16 +831,16 @@ static void i915_texture_subdata(struct pipe_context *pipe,
if (itransfer->staging_texture) {
struct i915_texture *tex = i915_texture(itransfer->staging_texture);
enum pipe_format format = tex->b.b.format;
struct i915_winsys *iws = i915_screen(tex->b.b.screen)->iws;
enum pipe_format format = tex->b.format;
struct i915_winsys *iws = i915_screen(tex->b.screen)->iws;
size_t offset;
size_t size;
offset = i915_texture_offset(tex, transfer->level, transfer->box.z);
for (i = 0; i < box->depth; i++) {
if (!tex->b.b.last_level &&
tex->b.b.width0 == transfer->box.width) {
if (!tex->b.last_level &&
tex->b.width0 == transfer->box.width) {
unsigned nby = util_format_get_nblocksy(format, transfer->box.y);
assert(!offset);
assert(!transfer->box.x);
@ -906,9 +906,9 @@ i915_texture_create(struct pipe_screen *screen,
if (!tex)
return NULL;
tex->b.b = *template;
pipe_reference_init(&tex->b.b.reference, 1);
tex->b.b.screen = screen;
tex->b = *template;
pipe_reference_init(&tex->b.reference, 1);
tex->b.screen = screen;
if ( (force_untiled) || (template->usage == PIPE_USAGE_STREAM) )
tex->tiling = I915_TILE_NONE;
@ -940,10 +940,10 @@ i915_texture_create(struct pipe_screen *screen,
I915_DBG(DBG_TEXTURE, "%s: %p stride %u, blocks (%u, %u) tiling %s\n", __func__,
tex, tex->stride,
tex->stride / util_format_get_blocksize(tex->b.b.format),
tex->stride / util_format_get_blocksize(tex->b.format),
tex->total_nblocksy, get_tiling_string(tex->tiling));
return &tex->b.b;
return &tex->b;
fail:
FREE(tex);
@ -978,13 +978,13 @@ i915_texture_from_handle(struct pipe_screen * screen,
if (!tex)
return NULL;
tex->b.b = *template;
pipe_reference_init(&tex->b.b.reference, 1);
tex->b.b.screen = screen;
tex->b = *template;
pipe_reference_init(&tex->b.reference, 1);
tex->b.screen = screen;
tex->stride = stride;
tex->tiling = tiling;
tex->total_nblocksy = align_nblocksy(tex->b.b.format, tex->b.b.height0, 8);
tex->total_nblocksy = align_nblocksy(tex->b.format, tex->b.height0, 8);
i915_texture_set_level_info(tex, 0, 1);
i915_texture_set_image_offset(tex, 0, 0, 0, 0);
@ -993,9 +993,9 @@ i915_texture_from_handle(struct pipe_screen * screen,
I915_DBG(DBG_TEXTURE, "%s: %p stride %u, blocks (%u, %u) tiling %s\n", __func__,
tex, tex->stride,
tex->stride / util_format_get_blocksize(tex->b.b.format),
tex->stride / util_format_get_blocksize(tex->b.format),
tex->total_nblocksy, get_tiling_string(tex->tiling));
return &tex->b.b;
return &tex->b;
}

4
src/gallium/drivers/i915/i915_state.c
View File

@ -701,7 +701,7 @@ static void i915_set_constant_buffer(struct pipe_context *pipe,
struct i915_buffer *old = old_buf ? i915_buffer(old_buf) : NULL;
unsigned old_num = i915->current.num_user_constants[shader];
new_num = ibuf->b.b.width0 / 4 * sizeof(float);
new_num = ibuf->b.width0 / 4 * sizeof(float);
if (old_num == new_num) {
if (old_num == 0)
@ -710,7 +710,7 @@ static void i915_set_constant_buffer(struct pipe_context *pipe,
/* XXX no point in running this code since st/mesa only uses user buffers */
/* Can't compare the buffer data since they are userbuffers */
else if (old && old->free_on_destroy)
diff = memcmp(old->data, ibuf->data, ibuf->b.b.width0);
diff = memcmp(old->data, ibuf->data, ibuf->b.width0);
#else
(void)old;
#endif

4
src/gallium/drivers/i915/i915_state_sampler.c
View File

@ -85,7 +85,7 @@ static void update_sampler(struct i915_context *i915,
const struct i915_texture *tex,
unsigned state[3])
{
const struct pipe_resource *pt = &tex->b.b;
const struct pipe_resource *pt = &tex->b;
unsigned minlod, lastlod;
state[0] = sampler->state[0];
@ -304,7 +304,7 @@ static void update_map(struct i915_context *i915,
const struct pipe_sampler_view* view,
uint state[3])
{
const struct pipe_resource *pt = &tex->b.b;
const struct pipe_resource *pt = &tex->b;
uint width = pt->width0, height = pt->height0, depth = pt->depth0;
int first_level = view->u.tex.first_level;
const uint num_levels = pt->last_level - first_level;

8
src/gallium/drivers/i915/i915_surface.c
View File

@ -209,8 +209,8 @@ i915_surface_copy_blitter(struct pipe_context *pipe,
{
struct i915_texture *dst_tex = i915_texture(dst);
struct i915_texture *src_tex = i915_texture(src);
struct pipe_resource *dpt = &dst_tex->b.b;
struct pipe_resource *spt = &src_tex->b.b;
struct pipe_resource *dpt = &dst_tex->b;
struct pipe_resource *spt = &src_tex->b;
unsigned dst_offset, src_offset; /* in bytes */
/* Fallback for buffers. */
@ -287,7 +287,7 @@ i915_clear_render_target_blitter(struct pipe_context *pipe,
bool render_condition_enabled)
{
struct i915_texture *tex = i915_texture(dst->texture);
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
union util_color uc;
unsigned offset = i915_texture_offset(tex, dst->u.tex.level, dst->u.tex.first_layer);
@ -316,7 +316,7 @@ i915_clear_depth_stencil_blitter(struct pipe_context *pipe,
bool render_condition_enabled)
{
struct i915_texture *tex = i915_texture(dst->texture);
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
unsigned packedds;
unsigned mask = 0;
unsigned offset = i915_texture_offset(tex, dst->u.tex.level, dst->u.tex.first_layer);

2
src/gallium/drivers/r300/r300_context.h
View File

@ -389,7 +389,7 @@ struct r300_texture_desc {
struct r300_resource
{
struct u_resource b;
struct pipe_resource b;
/* Winsys buffer backing this resource. */
struct pb_buffer *buf;

10
src/gallium/drivers/r300/r300_emit.c
View File

@ -142,9 +142,9 @@ static void get_rc_constant_state(
case RC_STATE_R300_TEXSCALE_FACTOR:
tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
/* Add a small number to the texture size to work around rounding errors in hw. */
vec[0] = tex->b.b.width0 / (tex->tex.width0 + 0.001f);
vec[1] = tex->b.b.height0 / (tex->tex.height0 + 0.001f);
vec[2] = tex->b.b.depth0 / (tex->tex.depth0 + 0.001f);
vec[0] = tex->b.width0 / (tex->tex.width0 + 0.001f);
vec[1] = tex->b.height0 / (tex->tex.height0 + 0.001f);
vec[2] = tex->b.depth0 / (tex->tex.depth0 + 0.001f);
vec[3] = 1;
break;
@ -1325,7 +1325,7 @@ validate:
r300->rws->cs_add_buffer(&r300->cs, tex->buf,
RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED,
r300_surface(fb->cbufs[i])->domain,
tex->b.b.nr_samples > 1 ?
tex->b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
}
@ -1336,7 +1336,7 @@ validate:
r300->rws->cs_add_buffer(&r300->cs, tex->buf,
RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED,
r300_surface(fb->zsbuf)->domain,
tex->b.b.nr_samples > 1 ?
tex->b.nr_samples > 1 ?
RADEON_PRIO_DEPTH_BUFFER_MSAA :
RADEON_PRIO_DEPTH_BUFFER);
}

2
src/gallium/drivers/r300/r300_fs.c
View File

@ -199,7 +199,7 @@ static void get_external_state(
state->unit[i].wrap_mode = RC_WRAP_NONE;
}
if (t->b.b.target == PIPE_TEXTURE_3D)
if (t->b.target == PIPE_TEXTURE_3D)
state->unit[i].clamp_and_scale_before_fetch = TRUE;
}
}

16
src/gallium/drivers/r300/r300_screen_buffer.c
View File

@ -116,7 +116,7 @@ r300_buffer_transfer_map( struct pipe_context *context,
struct pb_buffer *new_buf;
/* Create a new one in the same pipe_resource. */
new_buf = r300->rws->buffer_create(r300->rws, rbuf->b.b.width0,
new_buf = r300->rws->buffer_create(r300->rws, rbuf->b.width0,
R300_BUFFER_ALIGNMENT,
rbuf->domain,
RADEON_FLAG_NO_INTERPROCESS_SHARING);
@ -127,7 +127,7 @@ r300_buffer_transfer_map( struct pipe_context *context,
/* We changed the buffer, now we need to bind it where the old one was bound. */
for (i = 0; i < r300->nr_vertex_buffers; i++) {
if (r300->vertex_buffer[i].buffer.resource == &rbuf->b.b) {
if (r300->vertex_buffer[i].buffer.resource == &rbuf->b) {
r300->vertex_arrays_dirty = TRUE;
break;
}
@ -169,9 +169,9 @@ struct pipe_resource *r300_buffer_create(struct pipe_screen *screen,
rbuf = MALLOC_STRUCT(r300_resource);
rbuf->b.b = *templ;
pipe_reference_init(&rbuf->b.b.reference, 1);
rbuf->b.b.screen = screen;
rbuf->b = *templ;
pipe_reference_init(&rbuf->b.reference, 1);
rbuf->b.screen = screen;
rbuf->domain = RADEON_DOMAIN_GTT;
rbuf->buf = NULL;
rbuf->malloced_buffer = NULL;
@ -183,11 +183,11 @@ struct pipe_resource *r300_buffer_create(struct pipe_screen *screen,
if (templ->bind & PIPE_BIND_CONSTANT_BUFFER ||
(!r300screen->caps.has_tcl && !(templ->bind & PIPE_BIND_CUSTOM))) {
rbuf->malloced_buffer = align_malloc(templ->width0, 64);
return &rbuf->b.b;
return &rbuf->b;
}
rbuf->buf =
r300screen->rws->buffer_create(r300screen->rws, rbuf->b.b.width0,
r300screen->rws->buffer_create(r300screen->rws, rbuf->b.width0,
R300_BUFFER_ALIGNMENT,
rbuf->domain,
RADEON_FLAG_NO_INTERPROCESS_SHARING);
@ -195,5 +195,5 @@ struct pipe_resource *r300_buffer_create(struct pipe_screen *screen,
FREE(rbuf);
return NULL;
}
return &rbuf->b.b;
return &rbuf->b;
}

6
src/gallium/drivers/r300/r300_state_derived.c
View File

@ -828,7 +828,7 @@ static void r300_merge_textures_and_samplers(struct r300_context* r300)
base_level = view->base.u.tex.first_level;
min_level = sampler->min_lod;
level_count = MIN3(sampler->max_lod,
tex->b.b.last_level - base_level,
tex->b.last_level - base_level,
view->base.u.tex.last_level - base_level);
if (base_level + min_level) {
@ -891,14 +891,14 @@ static void r300_merge_textures_and_samplers(struct r300_context* r300)
}
/* to emulate 1D textures through 2D ones correctly */
if (tex->b.b.target == PIPE_TEXTURE_1D) {
if (tex->b.target == PIPE_TEXTURE_1D) {
texstate->filter0 &= ~R300_TX_WRAP_T_MASK;
texstate->filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
}
/* The hardware doesn't like CLAMP and CLAMP_TO_BORDER
* for the 3rd coordinate if the texture isn't 3D. */
if (tex->b.b.target != PIPE_TEXTURE_3D) {
if (tex->b.target != PIPE_TEXTURE_3D) {
texstate->filter0 &= ~R300_TX_WRAP_R_MASK;
}

14
src/gallium/drivers/r300/r300_texture.c
View File

@ -911,7 +911,7 @@ void r300_texture_setup_format_state(struct r300_screen *screen,
unsigned height0_override,
struct r300_texture_format_state *out)
{
struct pipe_resource *pt = &tex->b.b;
struct pipe_resource *pt = &tex->b;
struct r300_texture_desc *desc = &tex->tex;
boolean is_r500 = screen->caps.is_r500;
unsigned width, height, depth;
@ -1058,11 +1058,11 @@ r300_texture_create_object(struct r300_screen *rscreen,
goto fail;
}
pipe_reference_init(&tex->b.b.reference, 1);
tex->b.b.screen = &rscreen->screen;
tex->b.b.usage = base->usage;
tex->b.b.bind = base->bind;
tex->b.b.flags = base->flags;
pipe_reference_init(&tex->b.reference, 1);
tex->b.screen = &rscreen->screen;
tex->b.usage = base->usage;
tex->b.bind = base->bind;
tex->b.flags = base->flags;
tex->tex.microtile = microtile;
tex->tex.macrotile[0] = macrotile;
tex->tex.stride_in_bytes_override = stride_in_bytes_override;
@ -1234,7 +1234,7 @@ struct pipe_surface* r300_create_surface_custom(struct pipe_context * ctx,
/* Height must be aligned to the size of a tile. */
tile_height = r300_get_pixel_alignment(surface->base.format,
tex->b.b.nr_samples,
tex->b.nr_samples,
tex->tex.microtile,
tex->tex.macrotile[level],
DIM_HEIGHT, 0);

150
src/gallium/drivers/r300/r300_texture_desc.c
View File

@ -87,11 +87,11 @@ static boolean r300_texture_macro_switch(struct r300_resource *tex,
{
unsigned tile, texdim;
if (tex->b.b.nr_samples > 1) {
if (tex->b.nr_samples > 1) {
return TRUE;
}
tile = r300_get_pixel_alignment(tex->b.b.format, tex->b.b.nr_samples,
tile = r300_get_pixel_alignment(tex->b.format, tex->b.nr_samples,
tex->tex.microtile, RADEON_LAYOUT_TILED, dim, 0);
if (dim == DIM_WIDTH) {
texdim = u_minify(tex->tex.width0, level);
@ -124,27 +124,27 @@ static unsigned r300_texture_get_stride(struct r300_screen *screen,
return tex->tex.stride_in_bytes_override;
/* Check the level. */
if (level > tex->b.b.last_level) {
if (level > tex->b.last_level) {
SCREEN_DBG(screen, DBG_TEX, "%s: level (%u) > last_level (%u)\n",
__FUNCTION__, level, tex->b.b.last_level);
__FUNCTION__, level, tex->b.last_level);
return 0;
}
width = u_minify(tex->tex.width0, level);
if (util_format_is_plain(tex->b.b.format)) {
tile_width = r300_get_pixel_alignment(tex->b.b.format,
tex->b.b.nr_samples,
if (util_format_is_plain(tex->b.format)) {
tile_width = r300_get_pixel_alignment(tex->b.format,
tex->b.nr_samples,
tex->tex.microtile,
tex->tex.macrotile[level],
DIM_WIDTH, is_rs690);
width = align(width, tile_width);
stride = util_format_get_stride(tex->b.b.format, width);
stride = util_format_get_stride(tex->b.format, width);
/* The alignment to 32 bytes is sort of implied by the layout... */
return stride;
} else {
return align(util_format_get_stride(tex->b.b.format, width), is_rs690 ? 64 : 32);
return align(util_format_get_stride(tex->b.format, width), is_rs690 ? 64 : 32);
}
}
@ -157,16 +157,16 @@ static unsigned r300_texture_get_nblocksy(struct r300_resource *tex,
height = u_minify(tex->tex.height0, level);
/* Mipmapped and 3D textures must have their height aligned to POT. */
if ((tex->b.b.target != PIPE_TEXTURE_1D &&
tex->b.b.target != PIPE_TEXTURE_2D &&
tex->b.b.target != PIPE_TEXTURE_RECT) ||
tex->b.b.last_level != 0) {
if ((tex->b.target != PIPE_TEXTURE_1D &&
tex->b.target != PIPE_TEXTURE_2D &&
tex->b.target != PIPE_TEXTURE_RECT) ||
tex->b.last_level != 0) {
height = util_next_power_of_two(height);
}
if (util_format_is_plain(tex->b.b.format)) {
tile_height = r300_get_pixel_alignment(tex->b.b.format,
tex->b.b.nr_samples,
if (util_format_is_plain(tex->b.format)) {
tile_height = r300_get_pixel_alignment(tex->b.format,
tex->b.nr_samples,
tex->tex.microtile,
tex->tex.macrotile[level],
DIM_HEIGHT, 0);
@ -183,10 +183,10 @@ static unsigned r300_texture_get_nblocksy(struct r300_resource *tex,
/* Align the height so that there is an even number of macrotiles.
* Do so for 3 or more macrotiles in the Y direction. */
if (level == 0 && tex->b.b.last_level == 0 &&
(tex->b.b.target == PIPE_TEXTURE_1D ||
tex->b.b.target == PIPE_TEXTURE_2D ||
tex->b.b.target == PIPE_TEXTURE_RECT) &&
if (level == 0 && tex->b.last_level == 0 &&
(tex->b.target == PIPE_TEXTURE_1D ||
tex->b.target == PIPE_TEXTURE_2D ||
tex->b.target == PIPE_TEXTURE_RECT) &&
height >= tile_height * 3) {
height = align(height, tile_height * 2);
}
@ -198,7 +198,7 @@ static unsigned r300_texture_get_nblocksy(struct r300_resource *tex,
}
}
return util_format_get_nblocksy(tex->b.b.format, height);
return util_format_get_nblocksy(tex->b.format, height);
}
/* Get a width in pixels from a stride in bytes. */
@ -213,7 +213,7 @@ static void r300_setup_miptree(struct r300_screen *screen,
struct r300_resource *tex,
boolean align_for_cbzb)
{
struct pipe_resource *base = &tex->b.b;
struct pipe_resource *base = &tex->b;
unsigned stride, size, layer_size, nblocksy, i;
boolean rv350_mode = screen->caps.family >= CHIP_R350;
boolean aligned_for_cbzb;
@ -270,15 +270,15 @@ static void r300_setup_miptree(struct r300_screen *screen,
static void r300_setup_flags(struct r300_resource *tex)
{
tex->tex.uses_stride_addressing =
!util_is_power_of_two_or_zero(tex->b.b.width0) ||
!util_is_power_of_two_or_zero(tex->b.width0) ||
(tex->tex.stride_in_bytes_override &&
r300_stride_to_width(tex->b.b.format,
tex->tex.stride_in_bytes_override) != tex->b.b.width0);
r300_stride_to_width(tex->b.format,
tex->tex.stride_in_bytes_override) != tex->b.width0);
tex->tex.is_npot =
tex->tex.uses_stride_addressing ||
!util_is_power_of_two_or_zero(tex->b.b.height0) ||
!util_is_power_of_two_or_zero(tex->b.b.depth0);
!util_is_power_of_two_or_zero(tex->b.height0) ||
!util_is_power_of_two_or_zero(tex->b.depth0);
}
static void r300_setup_cbzb_flags(struct r300_screen *rscreen,
@ -287,20 +287,20 @@ static void r300_setup_cbzb_flags(struct r300_screen *rscreen,
unsigned i, bpp;
boolean first_level_valid;
bpp = util_format_get_blocksizebits(tex->b.b.format);
bpp = util_format_get_blocksizebits(tex->b.format);
/* 1) The texture must be point-sampled,
* 2) The depth must be 16 or 32 bits.
* 3) If the midpoint ZB offset is not aligned to 2048, it returns garbage
* with certain texture sizes. Macrotiling ensures the alignment. */
first_level_valid = tex->b.b.nr_samples <= 1 &&
first_level_valid = tex->b.nr_samples <= 1 &&
(bpp == 16 || bpp == 32) &&
tex->tex.macrotile[0];
if (SCREEN_DBG_ON(rscreen, DBG_NO_CBZB))
first_level_valid = FALSE;
for (i = 0; i <= tex->b.b.last_level; i++)
for (i = 0; i <= tex->b.last_level; i++)
tex->tex.cbzb_allowed[i] = first_level_valid && tex->tex.macrotile[i];
}
@ -349,8 +349,8 @@ static void r300_setup_hyperz_properties(struct r300_screen *screen,
static unsigned hiz_align_x[4] = {8, 32, 48, 32};
static unsigned hiz_align_y[4] = {8, 8, 8, 32};
if (util_format_is_depth_or_stencil(tex->b.b.format) &&
util_format_get_blocksizebits(tex->b.b.format) == 32 &&
if (util_format_is_depth_or_stencil(tex->b.format) &&
util_format_get_blocksizebits(tex->b.format) == 32 &&
tex->tex.microtile) {
unsigned i, pipes;
@ -360,18 +360,18 @@ static void r300_setup_hyperz_properties(struct r300_screen *screen,
pipes = screen->info.r300_num_gb_pipes;
}
for (i = 0; i <= tex->b.b.last_level; i++) {
for (i = 0; i <= tex->b.last_level; i++) {
unsigned zcomp_numdw, zcompsize, hiz_numdw, stride, height;
stride = r300_stride_to_width(tex->b.b.format,
stride = r300_stride_to_width(tex->b.format,
tex->tex.stride_in_bytes[i]);
stride = align(stride, 16);
height = u_minify(tex->b.b.height0, i);
height = u_minify(tex->b.height0, i);
/* The 8x8 compression mode needs macrotiling. */
zcompsize = screen->caps.z_compress == R300_ZCOMP_8X8 &&
tex->tex.macrotile[i] &&
tex->b.b.nr_samples <= 1 ? 8 : 4;
tex->b.nr_samples <= 1 ? 8 : 4;
/* Get the ZMASK buffer size in dwords. */
zcomp_numdw = r300_pixels_to_dwords(stride, height,
@ -379,7 +379,7 @@ static void r300_setup_hyperz_properties(struct r300_screen *screen,
zmask_blocks_y_per_dw[pipes-1] * zcompsize);
/* Check whether we have enough ZMASK memory. */
if (util_format_get_blocksizebits(tex->b.b.format) == 32 &&
if (util_format_get_blocksizebits(tex->b.format) == 32 &&
zcomp_numdw <= screen->caps.zmask_ram * pipes) {
tex->tex.zmask_dwords[i] = zcomp_numdw;
tex->tex.zcomp8x8[i] = zcompsize == 8;
@ -423,15 +423,15 @@ static void r300_setup_cmask_properties(struct r300_screen *screen,
}
/* We need an AA colorbuffer, no mipmaps. */
if (tex->b.b.nr_samples <= 1 ||
tex->b.b.last_level > 0 ||
util_format_is_depth_or_stencil(tex->b.b.format)) {
if (tex->b.nr_samples <= 1 ||
tex->b.last_level > 0 ||
util_format_is_depth_or_stencil(tex->b.format)) {
return;
}
/* FP16 AA needs R500 and a fairly new DRM. */
if ((tex->b.b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
tex->b.b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
if ((tex->b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
tex->b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
(!screen->caps.is_r500 || screen->info.drm_minor < 29)) {
return;
}
@ -447,12 +447,12 @@ static void r300_setup_cmask_properties(struct r300_screen *screen,
* the other cards have 4096 dwords of CMASK RAM per pipe. */
cmask_max_size = pipes == 1 ? 5120 : pipes * 4096;
stride = r300_stride_to_width(tex->b.b.format,
stride = r300_stride_to_width(tex->b.format,
tex->tex.stride_in_bytes[0]);
stride = align(stride, 16);
/* Get the CMASK size in dwords. */
cmask_num_dw = r300_pixels_to_dwords(stride, tex->b.b.height0,
cmask_num_dw = r300_pixels_to_dwords(stride, tex->b.height0,
cmask_align_x[pipes-1],
cmask_align_y[pipes-1]);
@ -467,14 +467,14 @@ static void r300_setup_cmask_properties(struct r300_screen *screen,
static void r300_setup_tiling(struct r300_screen *screen,
struct r300_resource *tex)
{
enum pipe_format format = tex->b.b.format;
enum pipe_format format = tex->b.format;
boolean rv350_mode = screen->caps.family >= CHIP_R350;
boolean is_zb = util_format_is_depth_or_stencil(format);
boolean dbg_no_tiling = SCREEN_DBG_ON(screen, DBG_NO_TILING);
boolean force_microtiling =
(tex->b.b.flags & R300_RESOURCE_FORCE_MICROTILING) != 0;
(tex->b.flags & R300_RESOURCE_FORCE_MICROTILING) != 0;
if (tex->b.b.nr_samples > 1) {
if (tex->b.nr_samples > 1) {
tex->tex.microtile = RADEON_LAYOUT_TILED;
tex->tex.macrotile[0] = RADEON_LAYOUT_TILED;
return;
@ -483,7 +483,7 @@ static void r300_setup_tiling(struct r300_screen *screen,
tex->tex.microtile = RADEON_LAYOUT_LINEAR;
tex->tex.macrotile[0] = RADEON_LAYOUT_LINEAR;
if (tex->b.b.usage == PIPE_USAGE_STAGING) {
if (tex->b.usage == PIPE_USAGE_STAGING) {
return;
}
@ -493,7 +493,7 @@ static void r300_setup_tiling(struct r300_screen *screen,
/* If height == 1, disable microtiling except for zbuffer. */
if (!force_microtiling && !is_zb &&
(tex->b.b.height0 == 1 || dbg_no_tiling)) {
(tex->b.height0 == 1 || dbg_no_tiling)) {
return;
}
@ -530,25 +530,25 @@ static void r300_tex_print_info(struct r300_resource *tex,
func,
tex->tex.macrotile[0] ? "YES" : " NO",
tex->tex.microtile ? "YES" : " NO",
r300_stride_to_width(tex->b.b.format, tex->tex.stride_in_bytes[0]),
tex->b.b.width0, tex->b.b.height0, tex->b.b.depth0,
tex->b.b.last_level, tex->tex.size_in_bytes,
util_format_short_name(tex->b.b.format),
tex->b.b.nr_samples);
r300_stride_to_width(tex->b.format, tex->tex.stride_in_bytes[0]),
tex->b.width0, tex->b.height0, tex->b.depth0,
tex->b.last_level, tex->tex.size_in_bytes,
util_format_short_name(tex->b.format),
tex->b.nr_samples);
}
void r300_texture_desc_init(struct r300_screen *rscreen,
struct r300_resource *tex,
const struct pipe_resource *base)
{
tex->b.b.target = base->target;
tex->b.b.format = base->format;
tex->b.b.width0 = base->width0;
tex->b.b.height0 = base->height0;
tex->b.b.depth0 = base->depth0;
tex->b.b.array_size = base->array_size;
tex->b.b.last_level = base->last_level;
tex->b.b.nr_samples = base->nr_samples;
tex->b.target = base->target;
tex->b.format = base->format;
tex->b.width0 = base->width0;
tex->b.height0 = base->height0;
tex->b.depth0 = base->depth0;
tex->b.array_size = base->array_size;
tex->b.last_level = base->last_level;
tex->b.nr_samples = base->nr_samples;
tex->tex.width0 = base->width0;
tex->tex.height0 = base->height0;
tex->tex.depth0 = base->depth0;
@ -564,26 +564,26 @@ void r300_texture_desc_init(struct r300_screen *rscreen,
* for rendering. */
if (rscreen->caps.is_r500) {
/* FP16 6x MSAA buffers are limited to a width of 1360 pixels. */
if ((tex->b.b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
tex->b.b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
tex->b.b.nr_samples == 6 && tex->b.b.width0 > 1360) {
tex->b.b.nr_samples = 4;
if ((tex->b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
tex->b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
tex->b.nr_samples == 6 && tex->b.width0 > 1360) {
tex->b.nr_samples = 4;
}
/* FP16 4x MSAA buffers are limited to a width of 2048 pixels. */
if ((tex->b.b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
tex->b.b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
tex->b.b.nr_samples == 4 && tex->b.b.width0 > 2048) {
tex->b.b.nr_samples = 2;
if ((tex->b.format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
tex->b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) &&
tex->b.nr_samples == 4 && tex->b.width0 > 2048) {
tex->b.nr_samples = 2;
}
}
/* 32-bit 6x MSAA buffers are limited to a width of 2720 pixels.
* This applies to all R300-R500 cards. */
if (util_format_get_blocksizebits(tex->b.b.format) == 32 &&
!util_format_is_depth_or_stencil(tex->b.b.format) &&
tex->b.b.nr_samples == 6 && tex->b.b.width0 > 2720) {
tex->b.b.nr_samples = 4;
if (util_format_get_blocksizebits(tex->b.format) == 32 &&
!util_format_is_depth_or_stencil(tex->b.format) &&
tex->b.nr_samples == 6 && tex->b.width0 > 2720) {
tex->b.nr_samples = 4;
}
r300_setup_flags(tex);
@ -635,7 +635,7 @@ unsigned r300_texture_get_offset(struct r300_resource *tex,
{
unsigned offset = tex->tex.offset_in_bytes[level];
switch (tex->b.b.target) {
switch (tex->b.target) {
case PIPE_TEXTURE_3D:
case PIPE_TEXTURE_CUBE:
return offset + layer * tex->tex.layer_size_in_bytes[level];

6
src/gallium/drivers/r300/r300_transfer.c
View File

@ -50,7 +50,7 @@ static void r300_copy_from_tiled_texture(struct pipe_context *ctx,
{
struct pipe_transfer *transfer = (struct pipe_transfer*)r300transfer;
struct pipe_resource *src = transfer->resource;
struct pipe_resource *dst = &r300transfer->linear_texture->b.b;
struct pipe_resource *dst = &r300transfer->linear_texture->b;
if (src->nr_samples <= 1) {
ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
@ -90,7 +90,7 @@ static void r300_copy_into_tiled_texture(struct pipe_context *ctx,
ctx->resource_copy_region(ctx, tex, transfer->level,
transfer->box.x, transfer->box.y, transfer->box.z,
&r300transfer->linear_texture->b.b, 0, &src_box);
&r300transfer->linear_texture->b, 0, &src_box);
/* XXX remove this. */
r300_flush(ctx, 0, NULL);
@ -108,7 +108,7 @@ r300_texture_transfer_map(struct pipe_context *ctx,
struct r300_resource *tex = r300_resource(texture);
struct r300_transfer *trans;
boolean referenced_cs, referenced_hw;
enum pipe_format format = tex->b.b.format;
enum pipe_format format = tex->b.format;
char *map;
referenced_cs =

10
src/gallium/drivers/svga/svga_draw.c
View File

@ -449,7 +449,7 @@ validate_constant_buffers(struct svga_context *svga)
* Rebind the resource if needed.
*/
if (buffer && !buffer->use_swbuf)
handle = svga_buffer_handle(svga, &buffer->b.b,
handle = svga_buffer_handle(svga, &buffer->b,
PIPE_BIND_CONSTANT_BUFFER);
else
handle = svga->state.hw_draw.constbufoffsets[shader][i].handle;
@ -545,12 +545,12 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
svga_buffer(hwtnl->cmd.vbufs[i].buffer.resource);
if (sbuf) {
vbuffer_handles[i] = svga_buffer_handle(svga, &sbuf->b.b,
vbuffer_handles[i] = svga_buffer_handle(svga, &sbuf->b,
PIPE_BIND_VERTEX_BUFFER);
assert(sbuf->key.flags & SVGA3D_SURFACE_BIND_VERTEX_BUFFER);
if (vbuffer_handles[i] == NULL)
return PIPE_ERROR_OUT_OF_MEMORY;
vbuffers[i] = &sbuf->b.b;
vbuffers[i] = &sbuf->b;
last_vbuf = i;
}
else {
@ -571,12 +571,12 @@ validate_vertex_buffers(struct svga_hwtnl *hwtnl,
svga_buffer(hwtnl->cmd.vbufs[i].buffer.resource);
if (sbuf) {
vbuffer_handles[i] = svga_buffer_handle(svga, &sbuf->b.b,
vbuffer_handles[i] = svga_buffer_handle(svga, &sbuf->b,
PIPE_BIND_VERTEX_BUFFER);
assert(sbuf->key.flags & SVGA3D_SURFACE_BIND_VERTEX_BUFFER);
if (vbuffer_handles[i] == NULL)
return PIPE_ERROR_OUT_OF_MEMORY;
vbuffers[i] = &sbuf->b.b;
vbuffers[i] = &sbuf->b;
last_vbuf = i;
}
else {

2
src/gallium/drivers/svga/svga_pipe_blit.c
View File

@ -447,7 +447,7 @@ can_blit_via_surface_copy(struct svga_context *svga,
* This is what we've been using before, but it can probably be
* relaxed. The device checks are less stringent.
*/
return (stex->b.b.format == dtex->b.b.format);
return (stex->b.format == dtex->b.format);
}

44
src/gallium/drivers/svga/svga_resource_buffer.c
View File

@ -255,10 +255,10 @@ svga_buffer_transfer_map(struct pipe_context *pipe,
debug_printf("%s: failed to allocate %u KB of DMA, "
"splitting DMA transfers\n",
__FUNCTION__,
(sbuf->b.b.width0 + 1023)/1024);
(sbuf->b.width0 + 1023)/1024);
}
sbuf->swbuf = align_malloc(sbuf->b.b.width0, 16);
sbuf->swbuf = align_malloc(sbuf->b.width0, 16);
if (!sbuf->swbuf) {
FREE(transfer);
goto done;
@ -367,7 +367,7 @@ svga_buffer_transfer_unmap(struct pipe_context *pipe,
sbuf->dma.flags.discard = TRUE;
if (!(svga->swc->force_coherent || sbuf->key.coherent) || sbuf->swbuf)
svga_buffer_add_range(sbuf, 0, sbuf->b.b.width0);
svga_buffer_add_range(sbuf, 0, sbuf->b.width0);
}
if (sbuf->swbuf &&
@ -467,9 +467,9 @@ svga_buffer_create(struct pipe_screen *screen,
if (!sbuf)
goto error1;
sbuf->b.b = *template;
pipe_reference_init(&sbuf->b.b.reference, 1);
sbuf->b.b.screen = screen;
sbuf->b = *template;
pipe_reference_init(&sbuf->b.reference, 1);
sbuf->b.screen = screen;
bind_flags = template->bind & ~PIPE_BIND_CUSTOM;
list_inithead(&sbuf->surfaces);
@ -487,7 +487,7 @@ svga_buffer_create(struct pipe_screen *screen,
* in multiples of 16, in order to allow bind_flags promotion,
* we are mandating all buffer size to be in multiples of 16.
*/
sbuf->b.b.width0 = align(sbuf->b.b.width0, 16);
sbuf->b.width0 = align(sbuf->b.width0, 16);
if (svga_buffer_needs_hw_storage(ss, template)) {
@ -517,7 +517,7 @@ svga_buffer_create(struct pipe_screen *screen,
goto error2;
}
else {
sbuf->swbuf = align_malloc(sbuf->b.b.width0, 64);
sbuf->swbuf = align_malloc(sbuf->b.width0, 64);
if (!sbuf->swbuf)
goto error2;
@ -529,17 +529,17 @@ svga_buffer_create(struct pipe_screen *screen,
sbuf->use_swbuf = TRUE;
}
debug_reference(&sbuf->b.b.reference,
debug_reference(&sbuf->b.reference,
(debug_reference_descriptor)debug_describe_resource, 0);
sbuf->bind_flags = bind_flags;
sbuf->size = util_resource_size(&sbuf->b.b);
sbuf->size = util_resource_size(&sbuf->b);
ss->hud.total_resource_bytes += sbuf->size;
ss->hud.num_resources++;
SVGA_STATS_TIME_POP(ss->sws);
return &sbuf->b.b;
return &sbuf->b;
error2:
FREE(sbuf);
@ -562,26 +562,26 @@ svga_user_buffer_create(struct pipe_screen *screen,
if (!sbuf)
goto no_sbuf;
pipe_reference_init(&sbuf->b.b.reference, 1);
sbuf->b.b.screen = screen;
sbuf->b.b.format = PIPE_FORMAT_R8_UNORM; /* ?? */
sbuf->b.b.usage = PIPE_USAGE_IMMUTABLE;
sbuf->b.b.bind = bind;
sbuf->b.b.width0 = bytes;
sbuf->b.b.height0 = 1;
sbuf->b.b.depth0 = 1;
sbuf->b.b.array_size = 1;
pipe_reference_init(&sbuf->b.reference, 1);
sbuf->b.screen = screen;
sbuf->b.format = PIPE_FORMAT_R8_UNORM; /* ?? */
sbuf->b.usage = PIPE_USAGE_IMMUTABLE;
sbuf->b.bind = bind;
sbuf->b.width0 = bytes;
sbuf->b.height0 = 1;
sbuf->b.depth0 = 1;
sbuf->b.array_size = 1;
sbuf->bind_flags = bind;
sbuf->swbuf = ptr;
sbuf->user = TRUE;
debug_reference(&sbuf->b.b.reference,
debug_reference(&sbuf->b.reference,
(debug_reference_descriptor)debug_describe_resource, 0);
ss->hud.num_resources++;
return &sbuf->b.b;
return &sbuf->b;
no_sbuf:
return NULL;

6
src/gallium/drivers/svga/svga_resource_buffer.h
View File

@ -72,7 +72,7 @@ struct svga_buffer_surface
*/
struct svga_buffer
{
struct u_resource b;
struct pipe_resource b;
/** This is a superset of b.b.bind */
unsigned bind_flags;
@ -230,7 +230,7 @@ static inline struct svga_buffer *
svga_buffer(struct pipe_resource *resource)
{
struct svga_buffer *buf = (struct svga_buffer *) resource;
assert(buf == NULL || buf->b.b.target == PIPE_BUFFER);
assert(buf == NULL || buf->b.target == PIPE_BUFFER);
return buf;
}
@ -256,7 +256,7 @@ svga_buffer_is_user_buffer(struct pipe_resource *buffer)
static inline struct svga_winsys_screen *
svga_buffer_winsys_screen(struct svga_buffer *sbuf)
{
return svga_screen(sbuf->b.b.screen)->sws;
return svga_screen(sbuf->b.screen)->sws;
}

44
src/gallium/drivers/svga/svga_resource_buffer_upload.c
View File

@ -128,7 +128,7 @@ svga_buffer_create_hw_storage(struct svga_screen *ss,
struct svga_winsys_screen *sws = ss->sws;
unsigned alignment = 16;
unsigned usage = 0;
unsigned size = sbuf->b.b.width0;
unsigned size = sbuf->b.width0;
sbuf->hwbuf = sws->buffer_create(sws, alignment, usage, size);
if (!sbuf->hwbuf)
@ -182,7 +182,7 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
sbuf->key.flags |= SVGA3D_SURFACE_DRAWINDIRECT_ARGS;
}
if (!bind_flags && sbuf->b.b.usage == PIPE_USAGE_STAGING) {
if (!bind_flags && sbuf->b.usage == PIPE_USAGE_STAGING) {
/* This surface is to be used with the
* SVGA3D_CMD_DX_TRANSFER_FROM_BUFFER command, and no other
* bind flags are allowed to be set for this surface.
@ -190,7 +190,7 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
sbuf->key.flags = SVGA3D_SURFACE_TRANSFER_FROM_BUFFER;
}
if (sbuf->b.b.flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
if (sbuf->b.flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
/* This surface can be mapped persistently. We use
* coherent memory to avoid implementing memory barriers for
* persistent non-coherent memory for now.
@ -198,7 +198,7 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
sbuf->key.coherent = 1;
}
sbuf->key.size.width = sbuf->b.b.width0;
sbuf->key.size.width = sbuf->b.width0;
sbuf->key.size.height = 1;
sbuf->key.size.depth = 1;
@ -209,10 +209,10 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
sbuf->key.sampleCount = 0;
SVGA_DBG(DEBUG_DMA, "surface_create for buffer sz %d\n",
sbuf->b.b.width0);
sbuf->b.width0);
sbuf->handle = svga_screen_surface_create(ss, bind_flags,
sbuf->b.b.usage,
sbuf->b.usage,
&validated, &sbuf->key);
if (!sbuf->handle)
return PIPE_ERROR_OUT_OF_MEMORY;
@ -224,7 +224,7 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
sbuf->dma.flags.discard = TRUE;
SVGA_DBG(DEBUG_DMA, " --> got sid %p sz %d (buffer)\n",
sbuf->handle, sbuf->b.b.width0);
sbuf->handle, sbuf->b.width0);
/* Add the new surface to the buffer surface list */
ret = svga_buffer_add_host_surface(sbuf, sbuf->handle, &sbuf->key,
@ -265,7 +265,7 @@ svga_buffer_recreate_host_surface(struct svga_context *svga,
assert(sbuf->handle);
SVGA_RETRY(svga, SVGA3D_vgpu10_BufferCopy(svga->swc, old_handle,
sbuf->handle,
0, 0, sbuf->b.b.width0));
0, 0, sbuf->b.width0));
}
/* Set the new bind flags for this buffer resource */
@ -357,7 +357,7 @@ svga_buffer_bind_host_surface(struct svga_context *svga,
if (sbuf->bind_flags & PIPE_BIND_STREAM_OUTPUT) {
SVGA_RETRY(svga, SVGA3D_vgpu10_BufferCopy(svga->swc, sbuf->handle,
bufsurf->handle,
0, 0, sbuf->b.b.width0));
0, 0, sbuf->b.width0));
}
/* Set this surface as the current one */
@ -408,7 +408,7 @@ svga_buffer_validate_host_surface(struct svga_context *svga,
tobind_flags);
/* Destroy the old surface */
svga_screen_surface_destroy(svga_screen(sbuf->b.b.screen),
svga_screen_surface_destroy(svga_screen(sbuf->b.screen),
&bufsurf->key, &bufsurf->handle);
list_del(&bufsurf->list);
@ -433,7 +433,7 @@ svga_buffer_destroy_host_surface(struct svga_screen *ss,
LIST_FOR_EACH_ENTRY_SAFE(bufsurf, next, &sbuf->surfaces, list) {
SVGA_DBG(DEBUG_DMA, " ungrab sid %p sz %d\n",
bufsurf->handle, sbuf->b.b.width0);
bufsurf->handle, sbuf->b.width0);
svga_screen_surface_destroy(ss, &bufsurf->key, &bufsurf->handle);
FREE(bufsurf);
}
@ -544,7 +544,7 @@ svga_buffer_upload_gb_command(struct svga_context *svga,
/* Increment reference count */
sbuf->dma.svga = svga;
dummy = NULL;
pipe_resource_reference(&dummy, &sbuf->b.b);
pipe_resource_reference(&dummy, &sbuf->b);
SVGA_FIFOCommitAll(swc);
swc->hints |= SVGA_HINT_FLAG_CAN_PRE_FLUSH;
@ -615,11 +615,11 @@ svga_buffer_upload_hb_command(struct svga_context *svga,
/* Increment reference count */
dummy = NULL;
pipe_resource_reference(&dummy, &sbuf->b.b);
pipe_resource_reference(&dummy, &sbuf->b);
pSuffix = (SVGA3dCmdSurfaceDMASuffix *)((uint8_t*)cmd + sizeof *cmd + numBoxes * sizeof *boxes);
pSuffix->suffixSize = sizeof *pSuffix;
pSuffix->maximumOffset = sbuf->b.b.width0;
pSuffix->maximumOffset = sbuf->b.width0;
pSuffix->flags = sbuf->dma.flags;
SVGA_FIFOCommitAll(swc);
@ -688,8 +688,8 @@ svga_buffer_upload_flush(struct svga_context *svga, struct svga_buffer *sbuf)
box->h = 1;
box->d = 1;
assert(box->x <= sbuf->b.b.width0);
assert(box->x + box->w <= sbuf->b.b.width0);
assert(box->x <= sbuf->b.width0);
assert(box->x + box->w <= sbuf->b.width0);
svga->hud.num_bytes_uploaded += box->w;
svga->hud.num_buffer_uploads++;
@ -716,8 +716,8 @@ svga_buffer_upload_flush(struct svga_context *svga, struct svga_buffer *sbuf)
box->srcy = 0;
box->srcz = 0;
assert(box->x <= sbuf->b.b.width0);
assert(box->x + box->w <= sbuf->b.b.width0);
assert(box->x <= sbuf->b.width0);
assert(box->x + box->w <= sbuf->b.width0);
svga->hud.num_bytes_uploaded += box->w;
svga->hud.num_buffer_uploads++;
@ -739,7 +739,7 @@ svga_buffer_upload_flush(struct svga_context *svga, struct svga_buffer *sbuf)
sbuf->dma.updates = NULL;
/* Decrement reference count (and potentially destroy) */
dummy = &sbuf->b.b;
dummy = &sbuf->b;
pipe_resource_reference(&dummy, NULL);
}
@ -850,7 +850,7 @@ svga_buffer_update_hw(struct svga_context *svga, struct svga_buffer *sbuf,
{
assert(!sbuf->user);
if (!svga_buffer_has_hw_storage(sbuf)) {
struct svga_screen *ss = svga_screen(sbuf->b.b.screen);
struct svga_screen *ss = svga_screen(sbuf->b.screen);
enum pipe_error ret;
boolean retry;
void *map;
@ -860,7 +860,7 @@ svga_buffer_update_hw(struct svga_context *svga, struct svga_buffer *sbuf,
if (!sbuf->swbuf)
return PIPE_ERROR;
ret = svga_buffer_create_hw_storage(svga_screen(sbuf->b.b.screen), sbuf,
ret = svga_buffer_create_hw_storage(svga_screen(sbuf->b.screen), sbuf,
bind_flags);
if (ret != PIPE_OK)
return ret;
@ -1094,7 +1094,7 @@ svga_context_flush_buffers(struct svga_context *svga)
while (curr != &svga->dirty_buffers) {
struct svga_buffer *sbuf = LIST_ENTRY(struct svga_buffer, curr, head);
assert(p_atomic_read(&sbuf->b.b.reference.count) != 0);
assert(p_atomic_read(&sbuf->b.reference.count) != 0);
assert(sbuf->dma.pending);
svga_buffer_upload_flush(svga, sbuf);

66
src/gallium/drivers/svga/svga_resource_texture.c
View File

@ -82,9 +82,9 @@ svga_transfer_dma_band(struct svga_context *svga,
x + w,
y + h,
z + 1,
util_format_get_blocksize(texture->b.b.format) * 8 /
(util_format_get_blockwidth(texture->b.b.format)
* util_format_get_blockheight(texture->b.b.format)));
util_format_get_blocksize(texture->b.format) * 8 /
(util_format_get_blockwidth(texture->b.format)
* util_format_get_blockheight(texture->b.format)));
SVGA_RETRY(svga, SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags));
}
@ -97,7 +97,7 @@ svga_transfer_dma(struct svga_context *svga,
SVGA3dSurfaceDMAFlags flags)
{
struct svga_texture *texture = svga_texture(st->base.resource);
struct svga_screen *screen = svga_screen(texture->b.b.screen);
struct svga_screen *screen = svga_screen(texture->b.screen);
struct svga_winsys_screen *sws = screen->sws;
struct pipe_fence_handle *fence = NULL;
@ -356,7 +356,7 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
for (i = 0; i < st->box.d; i++) {
if (svga_have_vgpu10(svga)) {
readback_image_vgpu10(svga, surf, st->slice + i, level,
tex->b.b.last_level + 1);
tex->b.last_level + 1);
} else {
readback_image_vgpu9(svga, surf, st->slice + i, level);
}
@ -450,27 +450,27 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
/**
* Compute the offset to the specific texture slice in the buffer.
*/
baseLevelSize.width = tex->b.b.width0;
baseLevelSize.height = tex->b.b.height0;
baseLevelSize.depth = tex->b.b.depth0;
baseLevelSize.width = tex->b.width0;
baseLevelSize.height = tex->b.height0;
baseLevelSize.depth = tex->b.depth0;
if ((tex->b.b.target == PIPE_TEXTURE_1D_ARRAY) ||
(tex->b.b.target == PIPE_TEXTURE_2D_ARRAY) ||
(tex->b.b.target == PIPE_TEXTURE_CUBE_ARRAY)) {
if ((tex->b.target == PIPE_TEXTURE_1D_ARRAY) ||
(tex->b.target == PIPE_TEXTURE_2D_ARRAY) ||
(tex->b.target == PIPE_TEXTURE_CUBE_ARRAY)) {
st->base.layer_stride =
svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
tex->b.b.last_level + 1, 1, 0);
tex->b.last_level + 1, 1, 0);
}
offset = svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
tex->b.b.last_level + 1, /* numMips */
tex->b.last_level + 1, /* numMips */
st->slice, level);
if (level > 0) {
assert(offset > 0);
}
mip_width = u_minify(tex->b.b.width0, level);
mip_height = u_minify(tex->b.b.height0, level);
mip_width = u_minify(tex->b.width0, level);
mip_height = u_minify(tex->b.height0, level);
offset += svga3dsurface_get_pixel_offset(tex->key.format,
mip_width, mip_height,
@ -535,7 +535,7 @@ svga_texture_transfer_map(struct pipe_context *pipe,
st->box.h = box->height;
st->box.d = box->depth;
switch (tex->b.b.target) {
switch (tex->b.target) {
case PIPE_TEXTURE_CUBE:
st->slice = st->base.box.z;
st->box.z = 0; /* so we don't apply double offsets below */
@ -751,7 +751,7 @@ svga_texture_transfer_unmap_direct(struct svga_context *svga,
SVGA3dBox box = st->box;
unsigned nlayers;
switch (tex->b.b.target) {
switch (tex->b.target) {
case PIPE_TEXTURE_2D_ARRAY:
case PIPE_TEXTURE_CUBE_ARRAY:
case PIPE_TEXTURE_1D_ARRAY:
@ -777,7 +777,7 @@ svga_texture_transfer_unmap_direct(struct svga_context *svga,
for (i = 0; i < nlayers; i++) {
update_image_vgpu10(svga, surf, &box,
st->slice + i, transfer->level,
tex->b.b.last_level + 1);
tex->b.last_level + 1);
}
} else {
assert(nlayers == 1);
@ -913,9 +913,9 @@ svga_texture_create(struct pipe_screen *screen,
goto fail;
}
tex->b.b = *template;
pipe_reference_init(&tex->b.b.reference, 1);
tex->b.b.screen = screen;
tex->b = *template;
pipe_reference_init(&tex->b.reference, 1);
tex->b.screen = screen;
tex->key.flags = 0;
tex->key.size.width = template->width0;
@ -925,15 +925,15 @@ svga_texture_create(struct pipe_screen *screen,
tex->key.numFaces = 1;
/* nr_samples=1 must be treated as a non-multisample texture */
if (tex->b.b.nr_samples == 1) {
tex->b.b.nr_samples = 0;
if (tex->b.nr_samples == 1) {
tex->b.nr_samples = 0;
}
else if (tex->b.b.nr_samples > 1) {
else if (tex->b.nr_samples > 1) {
assert(svgascreen->sws->have_sm4_1);
tex->key.flags |= SVGA3D_SURFACE_MULTISAMPLE;
}
tex->key.sampleCount = tex->b.b.nr_samples;
tex->key.sampleCount = tex->b.nr_samples;
if (svgascreen->sws->have_vgpu10) {
switch (template->target) {
@ -1092,7 +1092,7 @@ svga_texture_create(struct pipe_screen *screen,
SVGA_DBG(DEBUG_DMA, "surface_create for texture\n");
tex->handle = svga_screen_surface_create(svgascreen, bindings,
tex->b.b.usage,
tex->b.usage,
&tex->validated, &tex->key);
if (!tex->handle) {
goto fail;
@ -1100,14 +1100,14 @@ svga_texture_create(struct pipe_screen *screen,
SVGA_DBG(DEBUG_DMA, " --> got sid %p (texture)\n", tex->handle);
debug_reference(&tex->b.b.reference,
debug_reference(&tex->b.reference,
(debug_reference_descriptor)debug_describe_resource, 0);
tex->size = util_resource_size(template);
/* Determine if texture upload buffer can be used to upload this texture */
tex->can_use_upload = svga_texture_transfer_map_can_upload(svgascreen,
&tex->b.b);
&tex->b);
/* Initialize the backing resource cache */
tex->backed_handle = NULL;
@ -1117,7 +1117,7 @@ svga_texture_create(struct pipe_screen *screen,
SVGA_STATS_TIME_POP(svgascreen->sws);
return &tex->b.b;
return &tex->b;
fail:
if (tex->dirty)
@ -1171,9 +1171,9 @@ svga_texture_from_handle(struct pipe_screen *screen,
if (!tex->defined)
goto out_no_defined;
tex->b.b = *template;
pipe_reference_init(&tex->b.b.reference, 1);
tex->b.b.screen = screen;
tex->b = *template;
pipe_reference_init(&tex->b.reference, 1);
tex->b.screen = screen;
SVGA_DBG(DEBUG_DMA, "wrap surface sid %p\n", srf);
@ -1193,7 +1193,7 @@ svga_texture_from_handle(struct pipe_screen *screen,
ss->hud.num_resources++;
return &tex->b.b;
return &tex->b;
out_no_dirty:
FREE(tex->rendered_to);

14
src/gallium/drivers/svga/svga_resource_texture.h
View File

@ -45,7 +45,7 @@ enum SVGA3dSurfaceFormat;
struct svga_texture
{
struct u_resource b;
struct pipe_resource b;
ushort *defined;
@ -155,7 +155,7 @@ static inline struct svga_texture *
svga_texture(struct pipe_resource *resource)
{
struct svga_texture *tex = (struct svga_texture *)resource;
assert(tex == NULL || tex->b.b.target != PIPE_BUFFER);
assert(tex == NULL || tex->b.target != PIPE_BUFFER);
return tex;
}
@ -186,14 +186,14 @@ static inline void
check_face_level(const struct svga_texture *tex,
unsigned face, unsigned level)
{
if (tex->b.b.target == PIPE_TEXTURE_CUBE) {
if (tex->b.target == PIPE_TEXTURE_CUBE) {
assert(face < 6);
}
else if (tex->b.b.target == PIPE_TEXTURE_3D) {
assert(face < tex->b.b.depth0);
else if (tex->b.target == PIPE_TEXTURE_3D) {
assert(face < tex->b.depth0);
}
else {
assert(face < tex->b.b.array_size);
assert(face < tex->b.array_size);
}
assert(level < 8 * sizeof(tex->rendered_to[0]));
@ -261,7 +261,7 @@ static inline void
svga_clear_texture_dirty(struct svga_texture *tex)
{
unsigned i;
for (i = 0; i < tex->b.b.depth0 * tex->b.b.array_size; i++) {
for (i = 0; i < tex->b.depth0 * tex->b.array_size; i++) {
tex->dirty[i] = 0;
}
}

8
src/gallium/drivers/svga/svga_sampler_view.c
View File

@ -193,7 +193,7 @@ svga_validate_sampler_view(struct svga_context *svga,
age = tex->age;
if (tex->b.b.target == PIPE_TEXTURE_CUBE)
if (tex->b.target == PIPE_TEXTURE_CUBE)
numFaces = 6;
else
numFaces = 1;
@ -205,9 +205,9 @@ svga_validate_sampler_view(struct svga_context *svga,
svga_texture_copy_handle(svga,
tex->handle, 0, 0, 0, i, k,
v->handle, 0, 0, 0, i - v->min_lod, k,
u_minify(tex->b.b.width0, i),
u_minify(tex->b.b.height0, i),
u_minify(tex->b.b.depth0, i));
u_minify(tex->b.width0, i),
u_minify(tex->b.height0, i),
u_minify(tex->b.depth0, i));
}
}

4
src/gallium/drivers/svga/svga_state_constants.c
View File

@ -671,7 +671,7 @@ emit_constbuf(struct svga_context *svga,
}
}
else if (sbuf) {
dst_handle = svga_buffer_handle(svga, &sbuf->b.b, PIPE_BIND_CONSTANT_BUFFER);
dst_handle = svga_buffer_handle(svga, &sbuf->b, PIPE_BIND_CONSTANT_BUFFER);
new_buf_size = align(buffer_size, 16);
offset = buffer_offset;
}
@ -834,7 +834,7 @@ emit_constbuf_vgpu10(struct svga_context *svga, enum pipe_shader_type shader)
/* GL's buffer range sizes can be any number of bytes but the
* SVGA3D device requires a multiple of 16 bytes.
*/
const unsigned total_size = buffer->b.b.width0;
const unsigned total_size = buffer->b.width0;
if (offset + align(size, 16) <= total_size) {
/* round up size to multiple of 16 */

34
src/gallium/drivers/svga/svga_surface.c
View File

@ -152,14 +152,14 @@ svga_texture_copy_handle_resource(struct svga_context *svga,
for (j = 0; j < numLayers; j++) {
if (svga_is_texture_level_defined(src_tex, j+layeroffset, miplevel)) {
unsigned depth = (zslice_pick < 0 ?
u_minify(src_tex->b.b.depth0, miplevel) : 1);
u_minify(src_tex->b.depth0, miplevel) : 1);
if (src_tex->b.b.nr_samples > 1) {
if (src_tex->b.nr_samples > 1) {
unsigned subResource = j * numMipLevels + i;
svga_texture_copy_region(svga, src_tex->handle,
subResource, 0, 0, zoffset,
dst, subResource, 0, 0, 0,
src_tex->b.b.width0, src_tex->b.b.height0, depth);
src_tex->b.width0, src_tex->b.height0, depth);
}
else {
svga_texture_copy_handle(svga,
@ -168,8 +168,8 @@ svga_texture_copy_handle_resource(struct svga_context *svga,
miplevel,
j + layeroffset,
dst, 0, 0, 0, i, j,
u_minify(src_tex->b.b.width0, miplevel),
u_minify(src_tex->b.b.height0, miplevel),
u_minify(src_tex->b.width0, miplevel),
u_minify(src_tex->b.height0, miplevel),
depth);
}
}
@ -206,26 +206,26 @@ svga_texture_view_surface(struct svga_context *svga,
key->flags = flags;
key->format = format;
key->numMipLevels = num_mip;
key->size.width = u_minify(tex->b.b.width0, start_mip);
key->size.height = u_minify(tex->b.b.height0, start_mip);
key->size.depth = zslice_pick < 0 ? u_minify(tex->b.b.depth0, start_mip) : 1;
key->size.width = u_minify(tex->b.width0, start_mip);
key->size.height = u_minify(tex->b.height0, start_mip);
key->size.depth = zslice_pick < 0 ? u_minify(tex->b.depth0, start_mip) : 1;
key->cachable = 1;
key->arraySize = 1;
key->numFaces = 1;
/* single sample surface can be treated as non-multisamples surface */
key->sampleCount = tex->b.b.nr_samples > 1 ? tex->b.b.nr_samples : 0;
key->sampleCount = tex->b.nr_samples > 1 ? tex->b.nr_samples : 0;
if (key->sampleCount > 1) {
assert(ss->sws->have_sm4_1);
key->flags |= SVGA3D_SURFACE_MULTISAMPLE;
}
if (tex->b.b.target == PIPE_TEXTURE_CUBE && layer_pick < 0) {
if (tex->b.target == PIPE_TEXTURE_CUBE && layer_pick < 0) {
key->flags |= SVGA3D_SURFACE_CUBEMAP;
key->numFaces = 6;
} else if (tex->b.b.target == PIPE_TEXTURE_1D_ARRAY ||
tex->b.b.target == PIPE_TEXTURE_2D_ARRAY) {
} else if (tex->b.target == PIPE_TEXTURE_1D_ARRAY ||
tex->b.target == PIPE_TEXTURE_2D_ARRAY) {
key->arraySize = num_layers;
}
@ -476,7 +476,7 @@ create_backed_surface_view(struct svga_context *svga, struct svga_surface *s)
SVGA_STATS_TIME_CREATEBACKEDSURFACEVIEW);
backed_view = svga_create_surface_view(&svga->pipe,
&tex->b.b,
&tex->b,
&s->base,
TRUE);
if (!backed_view)
@ -497,7 +497,7 @@ create_backed_surface_view(struct svga_context *svga, struct svga_surface *s)
assert(bs->handle);
switch (tex->b.b.target) {
switch (tex->b.target) {
case PIPE_TEXTURE_CUBE:
case PIPE_TEXTURE_CUBE_ARRAY:
case PIPE_TEXTURE_1D_ARRAY:
@ -788,11 +788,11 @@ svga_propagate_surface(struct svga_context *svga, struct pipe_surface *surf,
unsigned zslice, layer;
unsigned nlayers = 1;
unsigned i;
unsigned numMipLevels = tex->b.b.last_level + 1;
unsigned numMipLevels = tex->b.last_level + 1;
unsigned srcLevel = s->real_level;
unsigned dstLevel = surf->u.tex.level;
unsigned width = u_minify(tex->b.b.width0, dstLevel);
unsigned height = u_minify(tex->b.b.height0, dstLevel);
unsigned width = u_minify(tex->b.width0, dstLevel);
unsigned height = u_minify(tex->b.height0, dstLevel);
if (surf->texture->target == PIPE_TEXTURE_CUBE) {
zslice = 0;

4
src/gallium/drivers/virgl/virgl_context.c
View File

@ -1169,8 +1169,8 @@ static void virgl_resource_copy_region(struct pipe_context *ctx,
struct virgl_resource *dres = virgl_resource(dst);
struct virgl_resource *sres = virgl_resource(src);
if (dres->u.b.target == PIPE_BUFFER)
util_range_add(&dres->u.b, &dres->valid_buffer_range, dstx, dstx + src_box->width);
if (dres->b.target == PIPE_BUFFER)
util_range_add(&dres->b, &dres->valid_buffer_range, dstx, dstx + src_box->width);
virgl_resource_dirty(dres, dst_level);
virgl_encode_resource_copy_region(vctx, dres,

14
src/gallium/drivers/virgl/virgl_encode.c
View File

@ -621,7 +621,7 @@ int virgl_encode_clear_texture(struct virgl_context *ctx,
const struct pipe_box *box,
const void *data)
{
const struct util_format_description *desc = util_format_description(res->u.b.format);
const struct util_format_description *desc = util_format_description(res->b.format);
unsigned block_bits = desc->block.bits;
uint32_t arr[4] = {0};
/* The spec describe <data> as a pointer to an array of between one
@ -889,7 +889,7 @@ int virgl_encoder_inline_write(struct virgl_context *ctx,
struct virgl_transfer transfer;
struct virgl_screen *vs = virgl_screen(ctx->base.screen);
transfer.base.resource = &res->u.b;
transfer.base.resource = &res->b;
transfer.hw_res = res->hw_res;
transfer.base.level = level;
transfer.base.usage = usage;
@ -976,7 +976,7 @@ int virgl_encode_sampler_view(struct virgl_context *ctx,
if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW)
dword_fmt_target |= (state->target << 24);
virgl_encoder_write_dword(ctx->cbuf, dword_fmt_target);
if (res->u.b.target == PIPE_BUFFER) {
if (res->b.target == PIPE_BUFFER) {
virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size);
virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1);
} else {
@ -1319,7 +1319,7 @@ int virgl_encode_set_shader_buffers(struct virgl_context *ctx,
virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_size);
virgl_encoder_write_res(ctx, res);
util_range_add(&res->u.b, &res->valid_buffer_range, buffers[i].buffer_offset,
util_range_add(&res->b, &res->valid_buffer_range, buffers[i].buffer_offset,
buffers[i].buffer_offset + buffers[i].buffer_size);
virgl_resource_dirty(res, 0);
} else {
@ -1346,7 +1346,7 @@ int virgl_encode_set_hw_atomic_buffers(struct virgl_context *ctx,
virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_size);
virgl_encoder_write_res(ctx, res);
util_range_add(&res->u.b, &res->valid_buffer_range, buffers[i].buffer_offset,
util_range_add(&res->b, &res->valid_buffer_range, buffers[i].buffer_offset,
buffers[i].buffer_offset + buffers[i].buffer_size);
virgl_resource_dirty(res, 0);
} else {
@ -1377,8 +1377,8 @@ int virgl_encode_set_shader_images(struct virgl_context *ctx,
virgl_encoder_write_dword(ctx->cbuf, images[i].u.buf.size);
virgl_encoder_write_res(ctx, res);
if (res->u.b.target == PIPE_BUFFER) {
util_range_add(&res->u.b, &res->valid_buffer_range, images[i].u.buf.offset,
if (res->b.target == PIPE_BUFFER) {
util_range_add(&res->b, &res->valid_buffer_range, images[i].u.buf.offset,
images[i].u.buf.offset + images[i].u.buf.size);
}
virgl_resource_dirty(res, images[i].u.tex.level);

4
src/gallium/drivers/virgl/virgl_query.c
View File

@ -114,7 +114,7 @@ static struct pipe_query *virgl_create_query(struct pipe_context *ctx,
query->result_size = (query_type == PIPE_QUERY_TIMESTAMP ||
query_type == PIPE_QUERY_TIME_ELAPSED) ? 8 : 4;
util_range_add(&query->buf->u.b, &query->buf->valid_buffer_range, 0,
util_range_add(&query->buf->b, &query->buf->valid_buffer_range, 0,
sizeof(struct virgl_host_query_state));
virgl_resource_dirty(query->buf, 0);
@ -209,7 +209,7 @@ static bool virgl_get_query_result(struct pipe_context *ctx,
return false;
}
host_state = pipe_buffer_map(ctx, &query->buf->u.b,
host_state = pipe_buffer_map(ctx, &query->buf->b,
PIPE_MAP_READ, &transfer);
}

62
src/gallium/drivers/virgl/virgl_resource.c
View File

@ -130,7 +130,7 @@ virgl_resource_transfer_prepare(struct virgl_context *vctx,
* We can proceed as if PIPE_MAP_UNSYNCHRONIZED and
* PIPE_MAP_DISCARD_RANGE are set.
*/
if (res->u.b.target == PIPE_BUFFER &&
if (res->b.target == PIPE_BUFFER &&
!util_ranges_intersect(&res->valid_buffer_range, xfer->base.box.x,
xfer->base.box.x + xfer->base.box.width) &&
likely(!(virgl_debug & VIRGL_DEBUG_XFER))) {
@ -156,7 +156,7 @@ virgl_resource_transfer_prepare(struct virgl_context *vctx,
* valid data.
*/
if (xfer->base.usage & PIPE_MAP_DISCARD_WHOLE_RESOURCE) {
can_realloc = virgl_can_rebind_resource(vctx, &res->u.b);
can_realloc = virgl_can_rebind_resource(vctx, &res->b);
} else {
can_staging = vctx->supports_staging;
}
@ -294,7 +294,7 @@ virgl_staging_map(struct virgl_context *vctx,
* |---| ==> align_offset
* |------------| ==> allocation of size + align_offset
*/
align_offset = vres->u.b.target == PIPE_BUFFER ?
align_offset = vres->b.target == PIPE_BUFFER ?
vtransfer->base.box.x % VIRGL_MAP_BUFFER_ALIGNMENT :
0;
@ -334,7 +334,7 @@ static bool
virgl_resource_realloc(struct virgl_context *vctx, struct virgl_resource *res)
{
struct virgl_screen *vs = virgl_screen(vctx->base.screen);
const struct pipe_resource *templ = &res->u.b;
const struct pipe_resource *templ = &res->b;
unsigned vbind, vflags;
struct virgl_hw_res *hw_res;
@ -366,7 +366,7 @@ virgl_resource_realloc(struct virgl_context *vctx, struct virgl_resource *res)
/* count toward the staging resource size limit */
vctx->queued_staging_res_size += res->metadata.total_size;
virgl_rebind_resource(vctx, &res->u.b);
virgl_rebind_resource(vctx, &res->b);
return true;
}
@ -425,7 +425,7 @@ virgl_resource_transfer_map(struct pipe_context *ctx,
return NULL;
}
if (vres->u.b.target == PIPE_BUFFER) {
if (vres->b.target == PIPE_BUFFER) {
/* For the checks below to be able to use 'usage', we assume that
* transfer preparation doesn't affect the usage.
*/
@ -448,7 +448,7 @@ virgl_resource_transfer_map(struct pipe_context *ctx,
}
if (usage & PIPE_MAP_WRITE)
util_range_add(&vres->u.b, &vres->valid_buffer_range, box->x, box->x + box->width);
util_range_add(&vres->b, &vres->valid_buffer_range, box->x, box->x + box->width);
}
*transfer = &trans->base;
@ -507,12 +507,12 @@ static struct pipe_resource *virgl_resource_create(struct pipe_screen *screen,
struct virgl_screen *vs = virgl_screen(screen);
struct virgl_resource *res = CALLOC_STRUCT(virgl_resource);
res->u.b = *templ;
res->u.b.screen = &vs->base;
pipe_reference_init(&res->u.b.reference, 1);
res->b = *templ;
res->b.screen = &vs->base;
pipe_reference_init(&res->b.reference, 1);
vbind = pipe_to_virgl_bind(vs, templ->bind);
vflags = pipe_to_virgl_flags(vs, templ->flags);
virgl_resource_layout(&res->u.b, &res->metadata, 0, 0, 0, 0);
virgl_resource_layout(&res->b, &res->metadata, 0, 0, 0, 0);
if ((vs->caps.caps.v2.capability_bits & VIRGL_CAP_APP_TWEAK_SUPPORT) &&
vs->tweak_gles_emulate_bgra &&
@ -547,7 +547,7 @@ static struct pipe_resource *virgl_resource_create(struct pipe_screen *screen,
virgl_texture_init(res);
}
return &res->u.b;
return &res->b;
}
@ -563,9 +563,9 @@ static struct pipe_resource *virgl_resource_from_handle(struct pipe_screen *scre
return NULL;
struct virgl_resource *res = CALLOC_STRUCT(virgl_resource);
res->u.b = *templ;
res->u.b.screen = &vs->base;
pipe_reference_init(&res->u.b.reference, 1);
res->b = *templ;
res->b.screen = &vs->base;
pipe_reference_init(&res->b.reference, 1);
plane = winsys_stride = plane_offset = modifier = 0;
res->hw_res = vs->vws->resource_create_from_handle(vs->vws, whandle,
@ -582,7 +582,7 @@ static struct pipe_resource *virgl_resource_from_handle(struct pipe_screen *scre
modifier = 0;
}
virgl_resource_layout(&res->u.b, &res->metadata, plane, winsys_stride,
virgl_resource_layout(&res->b, &res->metadata, plane, winsys_stride,
plane_offset, modifier);
if (!res->hw_res) {
FREE(res);
@ -595,17 +595,17 @@ static struct pipe_resource *virgl_resource_from_handle(struct pipe_screen *scre
uint32_t plane_strides[VIRGL_MAX_PLANE_COUNT];
uint32_t plane_offsets[VIRGL_MAX_PLANE_COUNT];
uint32_t plane_count = 0;
struct pipe_resource *iter = &res->u.b;
struct pipe_resource *iter = &res->b;
do {
struct virgl_resource *plane = virgl_resource(iter);
/* must be a plain 2D texture sharing the same hw_res */
if (plane->u.b.target != PIPE_TEXTURE_2D ||
plane->u.b.depth0 != 1 ||
plane->u.b.array_size != 1 ||
plane->u.b.last_level != 0 ||
plane->u.b.nr_samples > 1 ||
if (plane->b.target != PIPE_TEXTURE_2D ||
plane->b.depth0 != 1 ||
plane->b.array_size != 1 ||
plane->b.last_level != 0 ||
plane->b.nr_samples > 1 ||
plane->hw_res != res->hw_res ||
plane_count >= VIRGL_MAX_PLANE_COUNT) {
vs->vws->resource_reference(vs->vws, &res->hw_res, NULL);
@ -621,10 +621,10 @@ static struct pipe_resource *virgl_resource_from_handle(struct pipe_screen *scre
vs->vws->resource_set_type(vs->vws,
res->hw_res,
pipe_to_virgl_format(res->u.b.format),
pipe_to_virgl_bind(vs, res->u.b.bind),
res->u.b.width0,
res->u.b.height0,
pipe_to_virgl_format(res->b.format),
pipe_to_virgl_bind(vs, res->b.bind),
res->b.width0,
res->b.height0,
usage,
res->metadata.modifier,
plane_count,
@ -634,7 +634,7 @@ static struct pipe_resource *virgl_resource_from_handle(struct pipe_screen *scre
virgl_texture_init(res);
return &res->u.b;
return &res->b;
}
void virgl_init_screen_resource_functions(struct pipe_screen *screen)
@ -663,7 +663,7 @@ static void virgl_buffer_subdata(struct pipe_context *pipe,
likely(!(virgl_debug & VIRGL_DEBUG_XFER)) &&
virgl_transfer_queue_extend_buffer(&vctx->queue,
vbuf->hw_res, offset, size, data)) {
util_range_add(&vbuf->u.b, &vbuf->valid_buffer_range, offset, offset + size);
util_range_add(&vbuf->b, &vbuf->valid_buffer_range, offset, offset + size);
return;
}
@ -766,7 +766,7 @@ void virgl_resource_destroy(struct pipe_screen *screen,
struct virgl_screen *vs = virgl_screen(screen);
struct virgl_resource *res = virgl_resource(resource);
if (res->u.b.target == PIPE_BUFFER)
if (res->b.target == PIPE_BUFFER)
util_range_destroy(&res->valid_buffer_range);
vs->vws->resource_reference(vs->vws, &res->hw_res, NULL);
@ -782,7 +782,7 @@ bool virgl_resource_get_handle(struct pipe_screen *screen,
struct virgl_screen *vs = virgl_screen(screen);
struct virgl_resource *res = virgl_resource(resource);
if (res->u.b.target == PIPE_BUFFER)
if (res->b.target == PIPE_BUFFER)
return false;
return vs->vws->resource_get_handle(vs->vws, res->hw_res,
@ -793,7 +793,7 @@ bool virgl_resource_get_handle(struct pipe_screen *screen,
void virgl_resource_dirty(struct virgl_resource *res, uint32_t level)
{
if (res) {
if (res->u.b.target == PIPE_BUFFER)
if (res->b.target == PIPE_BUFFER)
res->clean_mask &= ~1;
else
res->clean_mask &= ~(1 << level);

2
src/gallium/drivers/virgl/virgl_resource.h
View File

@ -51,7 +51,7 @@ struct virgl_resource_metadata
};
struct virgl_resource {
struct u_resource u;
struct pipe_resource b;
uint16_t clean_mask;
struct virgl_hw_res *hw_res;
struct virgl_resource_metadata metadata;

4
src/gallium/drivers/virgl/virgl_screen.c
View File

@ -873,7 +873,7 @@ static void virgl_query_memory_info(struct pipe_screen *screen, struct pipe_memo
virgl_encode_get_memory_info(vctx, res);
ctx->flush(ctx, NULL, 0);
vscreen->vws->resource_wait(vscreen->vws, res->hw_res);
pipe_buffer_read(ctx, &res->u.b, 0, sizeof(struct virgl_memory_info), &virgl_info);
pipe_buffer_read(ctx, &res->b, 0, sizeof(struct virgl_memory_info), &virgl_info);
info->avail_device_memory = virgl_info.avail_device_memory;
info->avail_staging_memory = virgl_info.avail_staging_memory;
@ -882,7 +882,7 @@ static void virgl_query_memory_info(struct pipe_screen *screen, struct pipe_memo
info->total_device_memory = virgl_info.total_device_memory;
info->total_staging_memory = virgl_info.total_staging_memory;
screen->resource_destroy(screen, &res->u.b);
screen->resource_destroy(screen, &res->b);
ctx->destroy(ctx);
}

2
src/gallium/drivers/virgl/virgl_streamout.c
View File

@ -50,7 +50,7 @@ static struct pipe_stream_output_target *virgl_create_so_target(
t->handle = handle;
res->bind_history |= PIPE_BIND_STREAM_OUTPUT;
util_range_add(&res->u.b, &res->valid_buffer_range, buffer_offset,
util_range_add(&res->b, &res->valid_buffer_range, buffer_offset,
buffer_offset + buffer_size);
virgl_resource_dirty(res, 0);