diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 9d9d40ae62f..f7bf02d004b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -4789,7 +4789,7 @@ void eg_trace_emit(struct r600_context *rctx)
 
 	rctx->trace_id++;
 	radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
-			      RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
+			      RADEON_USAGE_READWRITE, RADEON_PRIO_FENCE_TRACE);
 	radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
 	radeon_emit(cs, rctx->trace_buf->gpu_address);
 	radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index c3aef0f4be6..2f3e376c5f9 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -461,7 +461,7 @@ void r600_emit_pfp_sync_me(struct r600_context *rctx)
 
 		reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, buf,
 						  RADEON_USAGE_READWRITE,
-						  RADEON_PRIO_FENCE);
+						  RADEON_PRIO_FENCE_TRACE);
 
 		va = buf->gpu_address + offset;
 		assert(va % 16 == 0);
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index b234a66ceb7..4aaa62d6873 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -143,48 +143,41 @@ enum radeon_value_id
 };
 
 /* Each group of two has the same priority. */
-#define RADEON_PRIO_FENCE (1 << 0)
-#define RADEON_PRIO_TRACE (1 << 1)
+#define RADEON_PRIO_FENCE_TRACE (1 << 0)
+#define RADEON_PRIO_SO_FILLED_SIZE (1 << 1)
 
-#define RADEON_PRIO_SO_FILLED_SIZE (1 << 2)
-#define RADEON_PRIO_QUERY (1 << 3)
+#define RADEON_PRIO_QUERY (1 << 2)
+#define RADEON_PRIO_IB (1 << 3)
 
-#define RADEON_PRIO_IB1 (1 << 4) /* main IB submitted to the kernel */
-#define RADEON_PRIO_IB2 (1 << 5)     /* IB executed with INDIRECT_BUFFER */
+#define RADEON_PRIO_DRAW_INDIRECT (1 << 4)
+#define RADEON_PRIO_INDEX_BUFFER (1 << 5)
 
-#define RADEON_PRIO_DRAW_INDIRECT (1 << 6)
-#define RADEON_PRIO_INDEX_BUFFER (1 << 7)
+#define RADEON_PRIO_CP_DMA (1 << 6)
+#define RADEON_PRIO_BORDER_COLORS (1 << 7)
 
-#define RADEON_PRIO_CP_DMA (1 << 8)
-#define RADEON_PRIO_BORDER_COLORS (1 << 9)
+#define RADEON_PRIO_CONST_BUFFER (1 << 8)
+#define RADEON_PRIO_DESCRIPTORS (1 << 9)
 
-#define RADEON_PRIO_CONST_BUFFER (1 << 10)
-#define RADEON_PRIO_DESCRIPTORS (1 << 11)
+#define RADEON_PRIO_SAMPLER_BUFFER (1 << 10)
+#define RADEON_PRIO_VERTEX_BUFFER (1 << 11)
 
-#define RADEON_PRIO_SAMPLER_BUFFER (1 << 12)
-#define RADEON_PRIO_VERTEX_BUFFER (1 << 13)
+#define RADEON_PRIO_SHADER_RW_BUFFER (1 << 12)
+#define RADEON_PRIO_SAMPLER_TEXTURE (1 << 13)
 
-#define RADEON_PRIO_SHADER_RW_BUFFER (1 << 14)
-#define RADEON_PRIO_COMPUTE_GLOBAL (1 << 15)
+#define RADEON_PRIO_SHADER_RW_IMAGE (1 << 14)
+#define RADEON_PRIO_SAMPLER_TEXTURE_MSAA (1 << 15)
 
-#define RADEON_PRIO_SAMPLER_TEXTURE (1 << 16)
-#define RADEON_PRIO_SHADER_RW_IMAGE (1 << 17)
+#define RADEON_PRIO_COLOR_BUFFER (1 << 16)
+#define RADEON_PRIO_DEPTH_BUFFER (1 << 17)
 
-#define RADEON_PRIO_SAMPLER_TEXTURE_MSAA (1 << 18)
-#define RADEON_PRIO_COLOR_BUFFER (1 << 19)
+#define RADEON_PRIO_COLOR_BUFFER_MSAA (1 << 18)
+#define RADEON_PRIO_DEPTH_BUFFER_MSAA (1 << 19)
 
-#define RADEON_PRIO_DEPTH_BUFFER (1 << 20)
+#define RADEON_PRIO_SEPARATE_META (1 << 20)
+#define RADEON_PRIO_SHADER_BINARY (1 << 21) /* the hw can't hide instruction cache misses */
 
-#define RADEON_PRIO_COLOR_BUFFER_MSAA (1 << 22)
-
-#define RADEON_PRIO_DEPTH_BUFFER_MSAA (1 << 24)
-
-#define RADEON_PRIO_SEPARATE_META (1 << 26)
-#define RADEON_PRIO_SHADER_BINARY (1 << 27) /* the hw can't hide instruction cache misses */
-
-#define RADEON_PRIO_SHADER_RINGS (1 << 28)
-
-#define RADEON_PRIO_SCRATCH_BUFFER (1 << 30)
+#define RADEON_PRIO_SHADER_RINGS (1 << 22)
+#define RADEON_PRIO_SCRATCH_BUFFER (1 << 23)
 
 struct winsys_handle;
 struct radeon_winsys_ctx;
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 0ae232db271..df7a4da2b0c 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -977,7 +977,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
          continue;
       }
       radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buffer, RADEON_USAGE_READWRITE,
-                                RADEON_PRIO_COMPUTE_GLOBAL);
+                                RADEON_PRIO_SHADER_RW_BUFFER);
    }
 
    /* Registers that are not read from memory should be set before this: */
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index 7f700f12ae6..a195bc18b3c 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -501,22 +501,19 @@ void si_log_hw_flush(struct si_context *sctx)
 static const char *priority_to_string(unsigned priority)
 {
 #define ITEM(x) if (priority == RADEON_PRIO_##x) return #x
-   ITEM(FENCE);
-   ITEM(TRACE);
+   ITEM(FENCE_TRACE);
    ITEM(SO_FILLED_SIZE);
    ITEM(QUERY);
-   ITEM(IB1);
-   ITEM(IB2);
+   ITEM(IB);
    ITEM(DRAW_INDIRECT);
    ITEM(INDEX_BUFFER);
    ITEM(CP_DMA);
+   ITEM(BORDER_COLORS);
    ITEM(CONST_BUFFER);
    ITEM(DESCRIPTORS);
-   ITEM(BORDER_COLORS);
    ITEM(SAMPLER_BUFFER);
    ITEM(VERTEX_BUFFER);
    ITEM(SHADER_RW_BUFFER);
-   ITEM(COMPUTE_GLOBAL);
    ITEM(SAMPLER_TEXTURE);
    ITEM(SHADER_RW_IMAGE);
    ITEM(SAMPLER_TEXTURE_MSAA);
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index e38b18f71fa..e2b06089412 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -196,7 +196,7 @@ static void si_begin_gfx_cs_debug(struct si_context *ctx)
    si_trace_emit(ctx);
 
    radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
-                             RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
+                             RADEON_USAGE_READWRITE, RADEON_PRIO_FENCE_TRACE);
 }
 
 static void si_add_gds_to_buffer_list(struct si_context *sctx)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index ac27cce8d82..9071bf13adc 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -807,7 +807,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
    ib->ptr_ib_size_inside_ib = false;
 
    amdgpu_cs_add_buffer(cs->main.rcs, ib->big_ib_buffer,
-                        RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
+                        RADEON_USAGE_READ, 0, RADEON_PRIO_IB);
 
    rcs->current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 
@@ -1061,7 +1061,7 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i
    cs->preamble_ib_bo = preamble_bo;
 
    amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo, RADEON_USAGE_READ, 0,
-                        RADEON_PRIO_IB1);
+                        RADEON_PRIO_IB);
    return true;
 }
 
@@ -1152,7 +1152,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw)
    rcs->gpu_address = va;
 
    amdgpu_cs_add_buffer(cs->main.rcs, ib->big_ib_buffer,
-                        RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
+                        RADEON_USAGE_READ, 0, RADEON_PRIO_IB);
 
    return true;
 }
@@ -1773,7 +1773,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
 
    if (cs->preamble_ib_bo) {
       amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo, RADEON_USAGE_READ, 0,
-                           RADEON_PRIO_IB1);
+                           RADEON_PRIO_IB);
    }
 
    rcs->used_gart_kb = 0;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 59ce65f0b70..395484c3179 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -793,7 +793,7 @@ static struct pipe_fence_handle *radeon_cs_create_fence(struct radeon_cmdbuf *rc
    /* Add the fence as a dummy relocation. */
    cs->ws->base.cs_add_buffer(rcs, fence,
                               RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT,
-                              RADEON_PRIO_FENCE);
+                              RADEON_PRIO_FENCE_TRACE);
    return (struct pipe_fence_handle*)fence;
 }