intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions. If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.
Fixes: 232ed89802
"i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -667,16 +667,15 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
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* messages adding a node interference to the grf127_send_hack_node.
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* This node has a fixed asignment to grf127.
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*
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* We don't apply it to SIMD16 because previous code avoids any register
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* overlap between sources and destination.
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* We don't apply it to SIMD16 instructions because previous code avoids
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* any register overlap between sources and destination.
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*/
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ra_set_node_reg(g, grf127_send_hack_node, 127);
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if (dispatch_width == 8) {
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foreach_block_and_inst(block, fs_inst, inst, cfg) {
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if (inst->is_send_from_grf() && inst->dst.file == VGRF)
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if (inst->exec_size < 16 && inst->is_send_from_grf() &&
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inst->dst.file == VGRF)
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ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
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}
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}
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if (spilled_any_registers) {
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foreach_block_and_inst(block, fs_inst, inst, cfg) {
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