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intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode 

Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions.  If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.

Fixes: 232ed89802 "i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2019-01-15 10:53:44 -06:00
parent 79724a0756
commit b4f0d062cd
1 changed files with 6 additions and 7 deletions
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13
src/intel/compiler/brw_fs_reg_allocate.cpp
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@ -667,15 +667,14 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
* messages adding a node interference to the grf127_send_hack_node.
* This node has a fixed asignment to grf127.
*
* We don't apply it to SIMD16 because previous code avoids any register
* overlap between sources and destination.
* We don't apply it to SIMD16 instructions because previous code avoids
* any register overlap between sources and destination.
*/
ra_set_node_reg(g, grf127_send_hack_node, 127);
if (dispatch_width == 8) {
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->is_send_from_grf() && inst->dst.file == VGRF)
ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
}
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->exec_size < 16 && inst->is_send_from_grf() &&
inst->dst.file == VGRF)
ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
}
if (spilled_any_registers) {