freedreno/a6xx: use program cache
Use the in-memory cache to construct shader program state and re-use it on subsequent draws, to lower driver overhead. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
1d7fbe2cd1
commit
b4e94af37d
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@ -56,6 +56,8 @@ fd6_context_destroy(struct pipe_context *pctx)
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fd_context_cleanup_common_vbos(&fd6_ctx->base);
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ir3_cache_destroy(fd6_ctx->shader_cache);
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fd6_texture_fini(pctx);
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free(fd6_ctx);
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@ -38,13 +38,6 @@
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#include "a6xx.xml.h"
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struct fd6_streamout_state {
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uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
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uint32_t prog[256/2];
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uint32_t prog_count;
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uint32_t vpc_so_buf_cntl;
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};
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struct fd6_context {
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struct fd_context base;
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@ -101,10 +94,13 @@ struct fd6_context {
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/* number of active samples-passed queries: */
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int samples_passed_queries;
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/* cached state about current emitted shader program (3d): */
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/*{*/
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struct fd6_streamout_state tf;
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/*}*/
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/* maps per-shader-stage state plus variant key to hw
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* program stateobj:
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*/
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struct ir3_cache *shader_cache;
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/* cached stateobjs to avoid hashtable lookup when not dirty: */
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const struct fd6_program_state *prog;
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uint16_t tex_seqno;
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struct hash_table *tex_cache;
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@ -199,41 +199,52 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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{
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struct fd6_context *fd6_ctx = fd6_context(ctx);
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struct fd6_emit emit = {
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.debug = &ctx->debug,
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.ctx = ctx,
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.vtx = &ctx->vtx,
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.prog = &ctx->prog,
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.info = info,
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.key = {
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.color_two_side = ctx->rasterizer->light_twoside,
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.vclamp_color = ctx->rasterizer->clamp_vertex_color,
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.fclamp_color = ctx->rasterizer->clamp_fragment_color,
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.rasterflat = ctx->rasterizer->flatshade,
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.half_precision = ctx->in_blit &&
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fd_half_precision(&ctx->batch->framebuffer),
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.ucp_enables = ctx->rasterizer->clip_plane_enable,
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.has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
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fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
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.vsaturate_s = fd6_ctx->vsaturate_s,
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.vsaturate_t = fd6_ctx->vsaturate_t,
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.vsaturate_r = fd6_ctx->vsaturate_r,
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.fsaturate_s = fd6_ctx->fsaturate_s,
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.fsaturate_t = fd6_ctx->fsaturate_t,
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.fsaturate_r = fd6_ctx->fsaturate_r,
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.vastc_srgb = fd6_ctx->vastc_srgb,
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.fastc_srgb = fd6_ctx->fastc_srgb,
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.vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
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.fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
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.vs = ctx->prog.vp,
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.fs = ctx->prog.fp,
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.key = {
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.color_two_side = ctx->rasterizer->light_twoside,
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.vclamp_color = ctx->rasterizer->clamp_vertex_color,
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.fclamp_color = ctx->rasterizer->clamp_fragment_color,
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.rasterflat = ctx->rasterizer->flatshade,
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.ucp_enables = ctx->rasterizer->clip_plane_enable,
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.has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate ||
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fd6_ctx->fastc_srgb || fd6_ctx->vastc_srgb),
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.vsaturate_s = fd6_ctx->vsaturate_s,
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.vsaturate_t = fd6_ctx->vsaturate_t,
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.vsaturate_r = fd6_ctx->vsaturate_r,
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.fsaturate_s = fd6_ctx->fsaturate_s,
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.fsaturate_t = fd6_ctx->fsaturate_t,
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.fsaturate_r = fd6_ctx->fsaturate_r,
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.vastc_srgb = fd6_ctx->vastc_srgb,
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.fastc_srgb = fd6_ctx->fastc_srgb,
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.vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
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.fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
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}
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},
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.rasterflat = ctx->rasterizer->flatshade,
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.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
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.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
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};
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fixup_shader_state(ctx, &emit.key);
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fixup_shader_state(ctx, &emit.key.key);
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unsigned dirty = ctx->dirty;
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const struct ir3_shader_variant *vp = fd6_emit_get_vp(&emit);
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const struct ir3_shader_variant *fp = fd6_emit_get_fp(&emit);
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if (!(dirty & FD_DIRTY_PROG)) {
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emit.prog = fd6_ctx->prog;
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} else {
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fd6_ctx->prog = fd6_emit_get_prog(&emit);
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}
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emit.vs = fd6_emit_get_prog(&emit)->vs;
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emit.fs = fd6_emit_get_prog(&emit)->fs;
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const struct ir3_shader_variant *vp = emit.vs;
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const struct ir3_shader_variant *fp = emit.fs;
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/* do regular pass first, since that is more likely to fail compiling: */
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@ -256,8 +267,8 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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/* and now binning pass: */
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emit.binning_pass = true;
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emit.dirty = dirty & ~(FD_DIRTY_BLEND);
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emit.vp = NULL; /* we changed key so need to refetch vp */
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emit.fp = NULL;
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emit.vs = fd6_emit_get_prog(&emit)->bs;
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draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
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if (emit.streamout_mask) {
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@ -533,7 +533,7 @@ fd6_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd6_emit *emit)
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{
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int32_t i, j;
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const struct fd_vertex_state *vtx = emit->vtx;
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const struct ir3_shader_variant *vp = fd6_emit_get_vp(emit);
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const struct ir3_shader_variant *vp = emit->vs;
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for (i = 0, j = 0; i <= vp->inputs_count; i++) {
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if (vp->inputs[i].sysval)
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@ -588,8 +588,9 @@ fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
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struct fd6_emit *emit)
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{
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struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
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const struct ir3_shader_variant *vp = fd6_emit_get_vp(emit);
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const struct ir3_shader_variant *fp = fd6_emit_get_fp(emit);
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const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
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const struct ir3_shader_variant *vp = emit->vs;
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const struct ir3_shader_variant *fp = emit->fs;
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const enum fd_dirty_3d_state dirty = emit->dirty;
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bool needs_border = false;
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@ -719,8 +720,19 @@ fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_RING(ring, A6XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
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}
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if (dirty & FD_DIRTY_PROG)
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fd6_program_emit(ctx, ring, emit);
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if (dirty & FD_DIRTY_PROG) {
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struct fd_ringbuffer *stateobj = emit->binning_pass ?
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prog->binning_stateobj : prog->stateobj;
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fd6_emit_add_group(emit, stateobj, FD6_GROUP_PROG, 0x7);
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/* emit remaining non-stateobj program state, ie. what depends
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* on other emit state, so cannot be pre-baked. This could
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* be moved to a separate stateobj which is dynamically
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* created.
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*/
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fd6_program_emit(ring, emit);
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}
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if (dirty & FD_DIRTY_RASTERIZER) {
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struct fd6_rasterizer_stateobj *rasterizer =
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@ -854,7 +866,7 @@ fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
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}
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if (emit->streamout_mask) {
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struct fd6_streamout_state *tf = &fd6_context(ctx)->tf;
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const struct fd6_streamout_state *tf = &prog->tf;
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OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
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OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
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@ -43,6 +43,7 @@ struct fd_ringbuffer;
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* need to be emit'd.
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*/
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enum fd6_state_id {
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FD6_GROUP_PROG,
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FD6_GROUP_VS_CONST,
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FD6_GROUP_FS_CONST,
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FD6_GROUP_VS_TEX,
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@ -57,12 +58,11 @@ struct fd6_state_group {
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/* grouped together emit-state for prog/vertex/state emit: */
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struct fd6_emit {
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struct pipe_debug_callback *debug;
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struct fd_context *ctx;
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const struct fd_vertex_state *vtx;
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const struct fd_program_stateobj *prog;
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const struct pipe_draw_info *info;
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bool binning_pass;
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struct ir3_shader_key key;
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struct ir3_cache_key key;
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enum fd_dirty_3d_state dirty;
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uint32_t sprite_coord_enable; /* bitmask */
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@ -76,9 +76,11 @@ struct fd6_emit {
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*/
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bool no_lrz_write;
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/* cached to avoid repeated lookups of same variants: */
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const struct ir3_shader_variant *vp, *fp;
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/* TODO: other shader stages.. */
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/* cached to avoid repeated lookups: */
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const struct fd6_program_state *prog;
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struct ir3_shader_variant *vs;
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struct ir3_shader_variant *fs;
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unsigned streamout_mask;
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@ -86,32 +88,16 @@ struct fd6_emit {
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unsigned num_groups;
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};
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static inline const struct ir3_shader_variant *
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fd6_emit_get_vp(struct fd6_emit *emit)
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static inline const struct fd6_program_state *
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fd6_emit_get_prog(struct fd6_emit *emit)
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{
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if (!emit->vp) {
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struct ir3_shader *shader = emit->prog->vp;
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emit->vp = ir3_shader_variant(shader, emit->key,
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emit->binning_pass, emit->debug);
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if (!emit->prog) {
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struct fd6_context *fd6_ctx = fd6_context(emit->ctx);
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struct ir3_program_state *s =
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ir3_cache_lookup(fd6_ctx->shader_cache, &emit->key, &emit->ctx->debug);
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emit->prog = fd6_program_state(s);
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}
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return emit->vp;
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}
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static inline const struct ir3_shader_variant *
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fd6_emit_get_fp(struct fd6_emit *emit)
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{
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if (!emit->fp) {
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if (emit->binning_pass) {
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/* use dummy stateobj to simplify binning vs non-binning: */
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static const struct ir3_shader_variant binning_fp = {};
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emit->fp = &binning_fp;
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} else {
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struct ir3_shader *shader = emit->prog->fp;
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emit->fp = ir3_shader_variant(shader, emit->key,
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false, emit->debug);
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}
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}
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return emit->fp;
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return emit->prog;
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}
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static inline void
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@ -59,6 +59,8 @@ static void
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fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
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{
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struct ir3_shader *so = hwcso;
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struct fd_context *ctx = fd_context(pctx);
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ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
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ir3_shader_destroy(so);
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}
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@ -73,6 +75,8 @@ static void
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fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
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{
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struct ir3_shader *so = hwcso;
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struct fd_context *ctx = fd_context(pctx);
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ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
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ir3_shader_destroy(so);
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}
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@ -178,11 +182,11 @@ link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v
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}
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static void
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setup_stream_out(struct fd_context *ctx, const struct ir3_shader_variant *v,
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setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
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struct ir3_shader_linkage *l)
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{
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const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
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struct fd6_streamout_state *tf = &fd6_context(ctx)->tf;
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struct fd6_streamout_state *tf = &state->tf;
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memset(tf, 0, sizeof(*tf));
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@ -251,12 +255,19 @@ enum {
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};
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static void
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setup_stages(struct fd6_emit *emit, struct stage *s)
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setup_stages(struct fd6_program_state *state, struct stage *s, bool binning_pass)
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{
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unsigned i;
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s[VS].v = fd6_emit_get_vp(emit);
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s[FS].v = fd6_emit_get_fp(emit);
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if (binning_pass) {
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static const struct ir3_shader_variant dummy_fs = {0};
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s[VS].v = state->bs;
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s[FS].v = &dummy_fs;
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} else {
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s[VS].v = state->vs;
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s[FS].v = state->fs;
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}
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s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
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@ -287,9 +298,9 @@ setup_stages(struct fd6_emit *emit, struct stage *s)
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s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
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}
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void
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fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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struct fd6_emit *emit)
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static void
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setup_stateobj(struct fd_ringbuffer *ring,
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struct fd6_program_state *state, bool binning_pass)
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{
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struct stage s[MAX_STAGES];
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uint32_t pos_regid, psize_regid, color_regid[8];
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@ -299,7 +310,7 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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uint8_t psize_loc = ~0;
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int i, j;
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setup_stages(emit, s);
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setup_stages(state, s, binning_pass);
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fssz = FOUR_QUADS;
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@ -392,8 +403,7 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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struct ir3_shader_linkage l = {0};
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ir3_link_shaders(&l, s[VS].v, s[FS].v);
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if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
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!emit->binning_pass)
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if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass)
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link_stream_out(&l, s[VS].v);
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BITSET_DECLARE(varbs, 128) = {0};
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@ -418,9 +428,8 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
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}
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if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
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!emit->binning_pass) {
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setup_stream_out(ctx, s[VS].v, &l);
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if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass) {
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setup_stream_out(state, s[VS].v, &l);
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}
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for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
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@ -478,7 +487,7 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
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COND(psize_regid != regid(63,0), 0x100));
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if (emit->binning_pass) {
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if (binning_pass) {
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OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
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OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
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OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
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@ -549,8 +558,10 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
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for (i = 0; i < 8; i++) {
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// TODO we could have a mix of half and full precision outputs,
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// we really need to figure out half-precision from IR3_REG_HALF
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OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
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COND(emit->key.half_precision,
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COND(false,
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A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
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}
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@ -559,27 +570,7 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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A6XX_VPC_PACK_PSIZELOC(psize_loc) |
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A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
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if (!emit->binning_pass) {
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uint32_t vinterp[8], vpsrepl[8];
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memset(vinterp, 0, sizeof(vinterp));
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memset(vpsrepl, 0, sizeof(vpsrepl));
|
||||
|
||||
/* looks like we need to do int varyings in the frag
|
||||
* shader on a5xx (no flatshad reg? or a420.0 bug?):
|
||||
*
|
||||
* (sy)(ss)nop
|
||||
* (sy)ldlv.u32 r0.x,l[r0.x], 1
|
||||
* ldlv.u32 r0.y,l[r0.x+1], 1
|
||||
* (ss)bary.f (ei)r63.x, 0, r0.x
|
||||
* (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
|
||||
* (rpt5)nop
|
||||
* sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
|
||||
*
|
||||
* Possibly on later a5xx variants we'll be able to use
|
||||
* something like the code below instead of workaround
|
||||
* in the shader:
|
||||
*/
|
||||
if (!binning_pass) {
|
||||
/* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
|
||||
for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
|
||||
/* NOTE: varyings are packed, so if compmask is 0xb
|
||||
|
|
@ -590,20 +581,83 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
|
|||
|
||||
uint32_t inloc = s[FS].v->inputs[j].inloc;
|
||||
|
||||
if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
|
||||
(s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
|
||||
if (s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) {
|
||||
uint32_t loc = inloc;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (compmask & (1 << i)) {
|
||||
state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
|
||||
loc++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!binning_pass)
|
||||
if (s[FS].instrlen)
|
||||
fd6_emit_shader(ring, s[FS].v);
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
|
||||
OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
|
||||
A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
|
||||
0xfcfc0000);
|
||||
OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
|
||||
OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
|
||||
OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
|
||||
OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
|
||||
OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
|
||||
}
|
||||
|
||||
/* emits the program state which is not part of the stateobj because of
|
||||
* dependency on other gl state (rasterflat or sprite-coord-replacement)
|
||||
*/
|
||||
void
|
||||
fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
|
||||
{
|
||||
const struct fd6_program_state *state = fd6_emit_get_prog(emit);
|
||||
|
||||
if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
|
||||
/* fastpath: */
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
|
||||
for (int i = 0; i < 8; i++)
|
||||
OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
|
||||
for (int i = 0; i < 8; i++)
|
||||
OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
|
||||
} else {
|
||||
/* slow-path: */
|
||||
struct ir3_shader_variant *fs = state->fs;
|
||||
uint32_t vinterp[8], vpsrepl[8];
|
||||
|
||||
memset(vinterp, 0, sizeof(vinterp));
|
||||
memset(vpsrepl, 0, sizeof(vpsrepl));
|
||||
|
||||
for (int i = 0; i < state->fs_inputs_count; i++) {
|
||||
int j = state->fs_inputs[i];
|
||||
|
||||
/* NOTE: varyings are packed, so if compmask is 0xb
|
||||
* then first, third, and fourth component occupy
|
||||
* three consecutive varying slots:
|
||||
*/
|
||||
unsigned compmask = fs->inputs[j].compmask;
|
||||
|
||||
uint32_t inloc = fs->inputs[j].inloc;
|
||||
|
||||
if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
|
||||
(fs->inputs[j].rasterflat && emit->rasterflat)) {
|
||||
uint32_t loc = inloc;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (compmask & (1 << i)) {
|
||||
vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
|
||||
//flatshade[loc / 32] |= 1 << (loc % 32);
|
||||
loc++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
gl_varying_slot slot = s[FS].v->inputs[j].slot;
|
||||
gl_varying_slot slot = fs->inputs[j].slot;
|
||||
|
||||
/* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
|
||||
if (slot >= VARYING_SLOT_VAR0) {
|
||||
|
|
@ -642,32 +696,57 @@ fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
|
|||
}
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
|
||||
for (i = 0; i < 8; i++)
|
||||
for (int i = 0; i < 8; i++)
|
||||
OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
|
||||
for (i = 0; i < 8; i++)
|
||||
OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
|
||||
for (int i = 0; i < 8; i++)
|
||||
OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
|
||||
}
|
||||
|
||||
if (!emit->binning_pass)
|
||||
if (s[FS].instrlen)
|
||||
fd6_emit_shader(ring, s[FS].v);
|
||||
|
||||
OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
|
||||
OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
|
||||
A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
|
||||
0xfcfc0000);
|
||||
OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
|
||||
OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
|
||||
OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
|
||||
OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
|
||||
OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
|
||||
}
|
||||
|
||||
static struct ir3_program_state *
|
||||
fd6_program_create(void *data, struct ir3_shader_variant *bs,
|
||||
struct ir3_shader_variant *vs,
|
||||
struct ir3_shader_variant *fs,
|
||||
const struct ir3_shader_key *key)
|
||||
{
|
||||
struct fd_context *ctx = data;
|
||||
struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
|
||||
|
||||
state->bs = bs;
|
||||
state->vs = vs;
|
||||
state->fs = fs;
|
||||
state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
|
||||
state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
|
||||
|
||||
setup_stateobj(state->binning_stateobj, state, true);
|
||||
setup_stateobj(state->stateobj, state, false);
|
||||
|
||||
return &state->base;
|
||||
}
|
||||
|
||||
static void
|
||||
fd6_program_destroy(void *data, struct ir3_program_state *state)
|
||||
{
|
||||
struct fd6_program_state *so = fd6_program_state(state);
|
||||
fd_ringbuffer_del(so->stateobj);
|
||||
fd_ringbuffer_del(so->binning_stateobj);
|
||||
free(so);
|
||||
}
|
||||
|
||||
static const struct ir3_cache_funcs cache_funcs = {
|
||||
.create_state = fd6_program_create,
|
||||
.destroy_state = fd6_program_destroy,
|
||||
};
|
||||
|
||||
void
|
||||
fd6_prog_init(struct pipe_context *pctx)
|
||||
{
|
||||
struct fd_context *ctx = fd_context(pctx);
|
||||
|
||||
fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
|
||||
|
||||
pctx->create_fs_state = fd6_fp_state_create;
|
||||
pctx->delete_fs_state = fd6_fp_state_delete;
|
||||
|
||||
|
|
|
|||
|
|
@ -31,13 +31,44 @@
|
|||
#include "pipe/p_context.h"
|
||||
#include "freedreno_context.h"
|
||||
#include "ir3_shader.h"
|
||||
#include "ir3_cache.h"
|
||||
|
||||
struct fd6_streamout_state {
|
||||
uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
|
||||
uint32_t prog[256/2];
|
||||
uint32_t prog_count;
|
||||
uint32_t vpc_so_buf_cntl;
|
||||
};
|
||||
|
||||
struct fd6_emit;
|
||||
|
||||
struct fd6_program_state {
|
||||
struct ir3_program_state base;
|
||||
struct ir3_shader_variant *bs; /* binning pass vs */
|
||||
struct ir3_shader_variant *vs;
|
||||
struct ir3_shader_variant *fs;
|
||||
struct fd_ringbuffer *binning_stateobj;
|
||||
struct fd_ringbuffer *stateobj;
|
||||
|
||||
/* cached state about current emitted shader program (3d): */
|
||||
struct fd6_streamout_state tf;
|
||||
|
||||
/* index and # of varyings: */
|
||||
uint8_t fs_inputs[16];
|
||||
uint8_t fs_inputs_count;
|
||||
|
||||
uint32_t vinterp[8];
|
||||
};
|
||||
|
||||
static inline struct fd6_program_state *
|
||||
fd6_program_state(struct ir3_program_state *state)
|
||||
{
|
||||
return (struct fd6_program_state *)state;
|
||||
}
|
||||
|
||||
void fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so);
|
||||
|
||||
void fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
|
||||
struct fd6_emit *emit);
|
||||
void fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit);
|
||||
|
||||
void fd6_prog_init(struct pipe_context *pctx);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue