radeon/llvm: Inline immediate offset when lowering implicit parameters
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@ -254,18 +254,22 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
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void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
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void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
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MachineRegisterInfo & MRI, unsigned dword_offset) const
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MachineRegisterInfo & MRI, unsigned dword_offset) const
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{
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{
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unsigned ByteOffset = dword_offset * 4;
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// We shouldn't be using an offset wider than 16-bits for implicit parameters.
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assert(isInt<16>(ByteOffset));
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MachineBasicBlock::iterator I = *MI;
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MachineBasicBlock::iterator I = *MI;
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unsigned PtrReg = MRI.createVirtualRegister(&AMDGPU::R600_TReg32_XRegClass);
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unsigned PtrReg = MRI.createVirtualRegister(&AMDGPU::R600_TReg32_XRegClass);
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MRI.setRegClass(MI->getOperand(0).getReg(), &AMDGPU::R600_TReg32_XRegClass);
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MRI.setRegClass(MI->getOperand(0).getReg(), &AMDGPU::R600_TReg32_XRegClass);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::MOV), PtrReg)
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::COPY), PtrReg)
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.addReg(AMDGPU::ALU_LITERAL_X)
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.addReg(AMDGPU::ZERO);
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.addImm(dword_offset * 4);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_i32_eg))
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_i32_eg))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(0))
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.addReg(PtrReg)
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.addReg(PtrReg)
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.addImm(0);
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.addImm(ByteOffset);
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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