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radeon/vcn: add dynamic dpb buffer Tier1 support 

Also add its buffer index and fill up messages for the buffer.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8851>
This commit is contained in:
Leo Liu 2021-02-02 21:24:47 -05:00
parent 6b4326346b
commit b460c9b5d1
2 changed files with 63 additions and 12 deletions
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70
src/gallium/drivers/radeon/radeon_vcn_dec.c
View File

@ -69,7 +69,7 @@
#define NUM_AV1_REFS 8
#define NUM_AV1_REFS_PER_FRAME 7
static unsigned calc_dpb_size(struct radeon_decoder *dec);
static unsigned calc_dpb_size(struct radeon_decoder *dec, unsigned db_alignment);
static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec);
static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec);
static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec,
@ -1321,11 +1321,14 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
rvcn_dec_message_header_t *header;
rvcn_dec_message_index_t *index_codec;
rvcn_dec_message_index_t *index_drm = NULL;
rvcn_dec_message_index_t *index_dynamic_dpb = NULL;
rvcn_dec_message_decode_t *decode;
unsigned sizes = 0, offset_decode, offset_codec;
unsigned offset_drm = 0;
unsigned offset_drm = 0, offset_dynamic_dpb = 0;
void *codec;
rvcn_dec_message_drm_t *drm = NULL;
rvcn_dec_message_dynamic_dpb_t *dynamic_dpb = NULL;
unsigned db_alignment;
header = dec->msg;
sizes += sizeof(rvcn_dec_message_header_t);
@ -1338,6 +1341,11 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
sizes += sizeof(rvcn_dec_message_index_t);
}
if (dec->dpb_type == DPB_DYNAMIC_TIER_1) {
index_dynamic_dpb = (void*)header + sizes;
sizes += sizeof(rvcn_dec_message_index_t);
}
offset_decode = sizes;
decode = (void*)header + sizes;
sizes += sizeof(rvcn_dec_message_decode_t);
@ -1348,6 +1356,12 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
sizes += sizeof(rvcn_dec_message_drm_t);
}
if (dec->dpb_type == DPB_DYNAMIC_TIER_1) {
offset_dynamic_dpb = sizes;
dynamic_dpb = (void*)header + sizes;
sizes += sizeof(rvcn_dec_message_dynamic_dpb_t);
}
offset_codec = sizes;
codec = (void*)header + sizes;
@ -1377,6 +1391,14 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
++header->num_buffers;
}
if (dec->dpb_type == DPB_DYNAMIC_TIER_1) {
index_dynamic_dpb->message_id = RDECODE_MESSAGE_DYNAMIC_DPB;
index_dynamic_dpb->offset = offset_dynamic_dpb;
index_dynamic_dpb->size = sizeof(rvcn_dec_message_dynamic_dpb_t);
index_dynamic_dpb->filled = 0;
++header->num_buffers;
}
decode->stream_type = dec->stream_type;
decode->decode_flags = 0;
decode->width_in_samples = dec->base.width;
@ -1384,8 +1406,12 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->bsd_size = align(dec->bs_size, 128);
db_alignment = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR &&
dec->base.width > 32 && (dec->stream_type == RDECODE_CODEC_VP9 ||
dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)) ? 64 : 32;
if (!dec->dpb.res) {
unsigned dpb_size = calc_dpb_size(dec);
unsigned dpb_size = calc_dpb_size(dec, db_alignment);
bool r;
if (dpb_size) {
if (encrypted) {
@ -1492,11 +1518,8 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->sc_coeff_size = 0;
decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
decode->db_pitch = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR &&
dec->base.width > 32 && (dec->stream_type == RDECODE_CODEC_VP9 ||
dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10))
? align(dec->base.width, 64)
: align(dec->base.width, 32);
decode->db_pitch = align(dec->base.width, db_alignment);
if (((struct si_screen*)dec->screen)->info.family >= CHIP_SIENNA_CICHLID &&
(dec->stream_type == RDECODE_CODEC_VP9 || dec->stream_type == RDECODE_CODEC_AV1 ||
dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10))
@ -1533,6 +1556,25 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
set_drm_keys(drm, decrypt);
}
if (dec->dpb_type == DPB_DYNAMIC_TIER_1) {
decode->decode_flags = 1;
dynamic_dpb->dpbArraySize = NUM_VP9_REFS + 1;
dynamic_dpb->dpbLumaPitch = align(decode->width_in_samples, db_alignment);
dynamic_dpb->dpbLumaAlignedHeight = align(decode->height_in_samples, db_alignment);
dynamic_dpb->dpbLumaAlignedSize =
dynamic_dpb->dpbLumaPitch * dynamic_dpb->dpbLumaAlignedHeight;
dynamic_dpb->dpbChromaPitch = dynamic_dpb->dpbLumaPitch >> 1;
dynamic_dpb->dpbChromaAlignedHeight = dynamic_dpb->dpbLumaAlignedHeight >> 1;
dynamic_dpb->dpbChromaAlignedSize =
dynamic_dpb->dpbChromaPitch * dynamic_dpb->dpbChromaAlignedHeight * 2;
dynamic_dpb->dpbReserved0[0] = db_alignment;
if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
dynamic_dpb->dpbLumaAlignedSize = dynamic_dpb->dpbLumaAlignedSize * 3 / 2;
dynamic_dpb->dpbChromaAlignedSize = dynamic_dpb->dpbChromaAlignedSize * 3 / 2;
}
}
switch (u_reduce_video_profile(picture->profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
rvcn_dec_message_avc_t avc = get_h264_msg(dec, (struct pipe_h264_picture_desc *)picture);
@ -1809,7 +1851,7 @@ static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec)
}
/* calculate size of reference picture buffer */
static unsigned calc_dpb_size(struct radeon_decoder *dec)
static unsigned calc_dpb_size(struct radeon_decoder *dec, unsigned db_alignment)
{
unsigned width_in_mb, height_in_mb, image_size, dpb_size;
@ -1921,9 +1963,13 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
case PIPE_VIDEO_FORMAT_VP9:
max_references = MAX2(max_references, 9);
dpb_size = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR)
? (8192 * 4320 * 3 / 2) * max_references
: (4096 * 3000 * 3 / 2) * max_references;
if (dec->dpb_type == DPB_MAX_RES)
dpb_size = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR)
? (8192 * 4320 * 3 / 2) * max_references
: (4096 * 3000 * 3 / 2) * max_references;
else
dpb_size = (align(dec->base.width, db_alignment) *
align(dec->base.height, db_alignment) * 3 / 2) * max_references;
if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
dpb_size = dpb_size * 3 / 2;

5
src/gallium/drivers/radeon/radeon_vcn_dec.h
View File

@ -1085,6 +1085,11 @@ struct radeon_decoder {
unsigned cntl;
} reg;
struct jpeg_params jpg;
enum {
DPB_MAX_RES = 0,
DPB_DYNAMIC_TIER_1,
} dpb_type;
void (*send_cmd)(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture);
};