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vc4: Write the alignment of level width consistently in validation. 

16 / cpp happens to be the same as utile_w on the only raster format
supported (4 bytes per pixel), but simulator/hw source code generally
talks in terms of utiles.
This commit is contained in:
Eric Anholt 2015-03-23 16:34:24 -07:00
parent 8975a09494
commit b3ea377f86
1 changed files with 2 additions and 2 deletions
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4
src/gallium/drivers/vc4/kernel/vc4_validate.c
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@ -164,7 +164,7 @@ check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
switch (tiling_format) {
case VC4_TILING_FORMAT_LINEAR:
aligned_width = roundup(width, 16 / cpp);
aligned_width = roundup(width, utile_w);
aligned_height = height;
break;
case VC4_TILING_FORMAT_T:
@ -951,7 +951,7 @@ reloc_tex(struct vc4_exec_info *exec,
aligned_height = roundup(level_height, utile_h);
break;
default:
aligned_width = roundup(level_width, 16 / cpp);
aligned_width = roundup(level_width, utile_w);
aligned_height = level_height;
break;
}