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freedreno/ir3: add encoding/decoding for (sat) bit 

Seems to be there since a3xx, but we always lowered fsat.  But we can
shave some instructions, especially in shaders that use lots of
clamp(foo, 0.0, 1.0) by not lowering fsat.

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2018-01-21 12:20:01 -05:00
parent 1b658533e1
commit b2fc94f074
4 changed files with 42 additions and 12 deletions
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12
src/gallium/drivers/freedreno/ir3/disasm-a3xx.c
View File

@ -980,18 +980,18 @@ static void print_instr(uint32_t *dwords, int level, int n)
* diff'ing..
*/
repeat = instr_repeat(instr);
if (instr->sync)
printf("(sy)");
if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7)))
printf("(ss)");
if (instr->jmp_tgt)
printf("(jp)");
if (instr->repeat && (instr->opc_cat <= 4)) {
printf("(rpt%d)", instr->repeat);
repeat = instr->repeat;
} else {
repeat = 0;
}
if (instr_sat(instr))
printf("(sat)");
if (repeat)
printf("(rpt%d)", repeat);
if (instr->ul && ((2 <= instr->opc_cat) && (instr->opc_cat <= 4)))
printf("(ul)");

38
src/gallium/drivers/freedreno/ir3/instr-a3xx.h
View File

@ -410,7 +410,8 @@ typedef struct PACKED {
/* dword1: */
uint32_t dst : 8;
uint32_t repeat : 3;
uint32_t repeat : 2;
uint32_t sat : 1;
uint32_t src1_r : 1;
uint32_t ss : 1;
uint32_t ul : 1; /* dunno */
@ -473,7 +474,8 @@ typedef struct PACKED {
/* dword1: */
uint32_t dst : 8;
uint32_t repeat : 3;
uint32_t repeat : 2;
uint32_t sat : 1;
uint32_t src1_r : 1;
uint32_t ss : 1;
uint32_t ul : 1;
@ -529,7 +531,8 @@ typedef struct PACKED {
/* dword1: */
uint32_t dst : 8;
uint32_t repeat : 3;
uint32_t repeat : 2;
uint32_t sat : 1;
uint32_t src_r : 1;
uint32_t ss : 1;
uint32_t ul : 1;
@ -752,9 +755,10 @@ typedef union PACKED {
instr_cat7_t cat7;
struct PACKED {
/* dword0: */
uint64_t pad1 : 40;
uint32_t repeat : 3; /* cat0-cat4 */
uint32_t pad2 : 1;
uint32_t pad1 : 32;
/* dword1: */
uint32_t pad2 : 12;
uint32_t ss : 1; /* cat1-cat4 (cat0??) and cat7 (?) */
uint32_t ul : 1; /* cat2-cat4 (and cat1 in blob.. which may be bug??) */
uint32_t pad3 : 13;
@ -765,6 +769,28 @@ typedef union PACKED {
};
} instr_t;
static inline uint32_t instr_repeat(instr_t *instr)
{
switch (instr->opc_cat) {
case 0: return instr->cat0.repeat;
case 1: return instr->cat1.repeat;
case 2: return instr->cat2.repeat;
case 3: return instr->cat3.repeat;
case 4: return instr->cat4.repeat;
default: return 0;
}
}
static inline bool instr_sat(instr_t *instr)
{
switch (instr->opc_cat) {
case 2: return instr->cat2.sat;
case 3: return instr->cat3.sat;
case 4: return instr->cat4.sat;
default: return false;
}
}
static inline uint32_t instr_opc(instr_t *instr)
{
switch (instr->opc_cat) {

3
src/gallium/drivers/freedreno/ir3/ir3.c
View File

@ -258,6 +258,7 @@ static int emit_cat2(struct ir3_instruction *instr, void *ptr,
cat2->dst = reg(dst, info, instr->repeat,
IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
cat2->repeat = instr->repeat;
cat2->sat = !!(instr->flags & IR3_INSTR_SAT);
cat2->ss = !!(instr->flags & IR3_INSTR_SS);
cat2->ul = !!(instr->flags & IR3_INSTR_UL);
cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
@ -354,6 +355,7 @@ static int emit_cat3(struct ir3_instruction *instr, void *ptr,
cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
cat3->repeat = instr->repeat;
cat3->sat = !!(instr->flags & IR3_INSTR_SAT);
cat3->ss = !!(instr->flags & IR3_INSTR_SS);
cat3->ul = !!(instr->flags & IR3_INSTR_UL);
cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
@ -401,6 +403,7 @@ static int emit_cat4(struct ir3_instruction *instr, void *ptr,
cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
cat4->repeat = instr->repeat;
cat4->sat = !!(instr->flags & IR3_INSTR_SAT);
cat4->ss = !!(instr->flags & IR3_INSTR_SS);
cat4->ul = !!(instr->flags & IR3_INSTR_UL);
cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);

1
src/gallium/drivers/freedreno/ir3/ir3.h
View File

@ -204,6 +204,7 @@ struct ir3_instruction {
IR3_INSTR_S = 0x100,
IR3_INSTR_S2EN = 0x200,
IR3_INSTR_G = 0x400,
IR3_INSTR_SAT = 0x800,
/* meta-flags, for intermediate stages of IR, ie.
* before register assignment is done:
*/