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pan/midgard: Fix 32/64 mixed swizzle packing 

Occurs in SSBO address computation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
This commit is contained in:
Alyssa Rosenzweig 2020-02-04 09:29:59 -05:00
parent a55a2e02a5
commit b2cab6b6db
1 changed files with 7 additions and 2 deletions
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9
src/panfrost/midgard/midgard_emit.c
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@ -194,8 +194,13 @@ mir_pack_swizzle_alu(midgard_instruction *ins)
packed = mir_pack_swizzle_64(ins->swizzle[i], components);
if (mode == midgard_reg_mode_32) {
src[i].rep_low |= (ins->swizzle[i][0] >= COMPONENT_Z);
src[i].rep_high |= (ins->swizzle[i][1] >= COMPONENT_Z);
bool lo = ins->swizzle[i][0] >= COMPONENT_Z;
bool hi = ins->swizzle[i][1] >= COMPONENT_Z;
/* TODO: can we mix halves? */
assert(lo == hi);
src[i].rep_low |= lo;
} else if (mode < midgard_reg_mode_32) {
unreachable("Cannot encode 8/16 swizzle in 64-bit");
}