spirv: convert some operands for bitwise shift and bitwise ops to uint32
SPIR-V allows to define the shift, offset and count operands for shift and bitfield opcodes with a bit-size different than 32 bits, but in NIR the opcodes have that limitation. As agreed in the mailing list, this patch adds a conversion to 32 bits to fix this. For more info, see: https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html v2: - src_bit_size will have zero value for variable bit-size operands (Jason). Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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@ -635,6 +635,41 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
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break;
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}
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case SpvOpBitFieldInsert:
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case SpvOpBitFieldSExtract:
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case SpvOpBitFieldUExtract:
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case SpvOpShiftLeftLogical:
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case SpvOpShiftRightArithmetic:
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case SpvOpShiftRightLogical: {
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bool swap;
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unsigned src0_bit_size = glsl_get_bit_size(vtn_src[0]->type);
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unsigned dst_bit_size = glsl_get_bit_size(type);
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nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap,
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src0_bit_size, dst_bit_size);
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assert (op == nir_op_ushr || op == nir_op_ishr || op == nir_op_ishl ||
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op == nir_op_bitfield_insert || op == nir_op_ubitfield_extract ||
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op == nir_op_ibitfield_extract);
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for (unsigned i = 0; i < nir_op_infos[op].num_inputs; i++) {
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unsigned src_bit_size =
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nir_alu_type_get_type_size(nir_op_infos[op].input_types[i]);
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if (src_bit_size == 0)
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continue;
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if (src_bit_size != src[i]->bit_size) {
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assert(src_bit_size == 32);
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/* Convert the Shift, Offset and Count operands to 32 bits, which is the bitsize
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* supported by the NIR instructions. See discussion here:
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*
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* https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
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*/
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src[i] = nir_u2u32(&b->nb, src[i]);
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}
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}
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val->ssa->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2], src[3]);
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break;
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}
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default: {
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bool swap;
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unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);
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