radv: remove RADV_DEBUG=nosisched and RADV_PERFTEST=sisched
They are no longer useful. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>
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@ -589,8 +589,6 @@ Mesa EGL supports different sets of environment variables. See the
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<dd>disable out-of-order rasterization</dd>
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<dd>disable out-of-order rasterization</dd>
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<dt><code>noshaderballot</code></dt>
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<dt><code>noshaderballot</code></dt>
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<dd>disable shader ballot</dd>
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<dd>disable shader ballot</dd>
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<dt><code>nosisched</code></dt>
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<dd>disable LLVM sisched experimental scheduler</dd>
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<dt><code>nothreadllvm</code></dt>
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<dt><code>nothreadllvm</code></dt>
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<dd>disable LLVM threaded compilation</dd>
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<dd>disable LLVM threaded compilation</dd>
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<dt><code>preoptir</code></dt>
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<dt><code>preoptir</code></dt>
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@ -636,8 +634,6 @@ Mesa EGL supports different sets of environment variables. See the
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<dd>enable wave32 for pixel shaders (GFX10+)</dd>
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<dd>enable wave32 for pixel shaders (GFX10+)</dd>
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<dt><code>shader_ballot</code></dt>
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<dt><code>shader_ballot</code></dt>
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<dd>enable shader ballot</dd>
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<dd>enable shader ballot</dd>
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<dt><code>sisched</code></dt>
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<dd>enable LLVM sisched experimental scheduler</dd>
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<dt><code>tccompatcmask</code></dt>
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<dt><code>tccompatcmask</code></dt>
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<dd>enable TC-compat cmask for MSAA images</dd>
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<dd>enable TC-compat cmask for MSAA images</dd>
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</dl>
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</dl>
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@ -41,38 +41,36 @@ enum {
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RADV_DEBUG_VM_FAULTS = 0x400,
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RADV_DEBUG_VM_FAULTS = 0x400,
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RADV_DEBUG_ZERO_VRAM = 0x800,
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RADV_DEBUG_ZERO_VRAM = 0x800,
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RADV_DEBUG_SYNC_SHADERS = 0x1000,
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RADV_DEBUG_SYNC_SHADERS = 0x1000,
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RADV_DEBUG_NO_SISCHED = 0x2000,
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RADV_DEBUG_PREOPTIR = 0x2000,
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RADV_DEBUG_PREOPTIR = 0x4000,
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RADV_DEBUG_NO_DYNAMIC_BOUNDS = 0x4000,
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RADV_DEBUG_NO_DYNAMIC_BOUNDS = 0x8000,
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RADV_DEBUG_NO_OUT_OF_ORDER = 0x8000,
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RADV_DEBUG_NO_OUT_OF_ORDER = 0x10000,
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RADV_DEBUG_INFO = 0x10000,
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RADV_DEBUG_INFO = 0x20000,
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RADV_DEBUG_ERRORS = 0x20000,
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RADV_DEBUG_ERRORS = 0x40000,
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RADV_DEBUG_STARTUP = 0x40000,
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RADV_DEBUG_STARTUP = 0x80000,
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RADV_DEBUG_CHECKIR = 0x80000,
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RADV_DEBUG_CHECKIR = 0x100000,
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RADV_DEBUG_NOTHREADLLVM = 0x100000,
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RADV_DEBUG_NOTHREADLLVM = 0x200000,
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RADV_DEBUG_NOBINNING = 0x200000,
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RADV_DEBUG_NOBINNING = 0x400000,
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RADV_DEBUG_NO_LOAD_STORE_OPT = 0x400000,
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RADV_DEBUG_NO_LOAD_STORE_OPT = 0x800000,
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RADV_DEBUG_NO_NGG = 0x800000,
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RADV_DEBUG_NO_NGG = 0x1000000,
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RADV_DEBUG_NO_SHADER_BALLOT = 0x1000000,
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RADV_DEBUG_NO_SHADER_BALLOT = 0x2000000,
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RADV_DEBUG_ALL_ENTRYPOINTS = 0x2000000,
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RADV_DEBUG_ALL_ENTRYPOINTS = 0x4000000,
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RADV_DEBUG_DUMP_META_SHADERS = 0x4000000,
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RADV_DEBUG_DUMP_META_SHADERS = 0x8000000,
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RADV_DEBUG_NO_MEMORY_CACHE = 0x8000000,
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RADV_DEBUG_NO_MEMORY_CACHE = 0x10000000,
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RADV_DEBUG_NOOP = 0x10000000,
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RADV_DEBUG_NOOP = 0x20000000,
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};
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};
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enum {
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enum {
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RADV_PERFTEST_NO_BATCHCHAIN = 0x1,
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RADV_PERFTEST_NO_BATCHCHAIN = 0x1,
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RADV_PERFTEST_SISCHED = 0x2,
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RADV_PERFTEST_LOCAL_BOS = 0x2,
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RADV_PERFTEST_LOCAL_BOS = 0x4,
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RADV_PERFTEST_DCC_MSAA = 0x4,
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RADV_PERFTEST_DCC_MSAA = 0x8,
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RADV_PERFTEST_BO_LIST = 0x8,
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RADV_PERFTEST_BO_LIST = 0x10,
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RADV_PERFTEST_SHADER_BALLOT = 0x10,
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RADV_PERFTEST_SHADER_BALLOT = 0x20,
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RADV_PERFTEST_TC_COMPAT_CMASK = 0x20,
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RADV_PERFTEST_TC_COMPAT_CMASK = 0x40,
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RADV_PERFTEST_CS_WAVE_32 = 0x40,
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RADV_PERFTEST_CS_WAVE_32 = 0x80,
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RADV_PERFTEST_PS_WAVE_32 = 0x80,
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RADV_PERFTEST_PS_WAVE_32 = 0x100,
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RADV_PERFTEST_GE_WAVE_32 = 0x100,
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RADV_PERFTEST_GE_WAVE_32 = 0x200,
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RADV_PERFTEST_DFSM = 0x200,
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RADV_PERFTEST_DFSM = 0x400,
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RADV_PERFTEST_ACO = 0x400,
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RADV_PERFTEST_ACO = 0x800,
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};
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};
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bool
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bool
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@ -414,9 +414,7 @@ radv_physical_device_init(struct radv_physical_device *device,
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}
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}
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/* These flags affect shader compilation. */
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/* These flags affect shader compilation. */
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uint64_t shader_env_flags =
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uint64_t shader_env_flags = (device->use_aco ? 0x2 : 0);
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(device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
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(device->use_aco ? 0x2 : 0);
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/* The gpu id is already embedded in the uuid so we just pass "radv"
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/* The gpu id is already embedded in the uuid so we just pass "radv"
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* when creating the cache.
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* when creating the cache.
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@ -547,7 +545,6 @@ static const struct debug_control radv_debug_options[] = {
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{"vmfaults", RADV_DEBUG_VM_FAULTS},
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{"vmfaults", RADV_DEBUG_VM_FAULTS},
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{"zerovram", RADV_DEBUG_ZERO_VRAM},
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{"zerovram", RADV_DEBUG_ZERO_VRAM},
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{"syncshaders", RADV_DEBUG_SYNC_SHADERS},
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{"syncshaders", RADV_DEBUG_SYNC_SHADERS},
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{"nosisched", RADV_DEBUG_NO_SISCHED},
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{"preoptir", RADV_DEBUG_PREOPTIR},
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{"preoptir", RADV_DEBUG_PREOPTIR},
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{"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
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{"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
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{"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
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{"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
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@ -576,7 +573,6 @@ radv_get_debug_option_name(int id)
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static const struct debug_control radv_perftest_options[] = {
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static const struct debug_control radv_perftest_options[] = {
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{"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
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{"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
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{"sisched", RADV_PERFTEST_SISCHED},
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{"localbos", RADV_PERFTEST_LOCAL_BOS},
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{"localbos", RADV_PERFTEST_LOCAL_BOS},
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{"dccmsaa", RADV_PERFTEST_DCC_MSAA},
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{"dccmsaa", RADV_PERFTEST_DCC_MSAA},
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{"bolist", RADV_PERFTEST_BO_LIST},
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{"bolist", RADV_PERFTEST_BO_LIST},
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@ -218,8 +218,6 @@ static uint32_t get_hash_flags(struct radv_device *device)
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if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
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if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
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hash_flags |= RADV_HASH_SHADER_NO_NGG;
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hash_flags |= RADV_HASH_SHADER_NO_NGG;
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if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
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hash_flags |= RADV_HASH_SHADER_SISCHED;
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if (device->physical_device->cs_wave_size == 32)
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if (device->physical_device->cs_wave_size == 32)
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hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
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hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
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if (device->physical_device->ps_wave_size == 32)
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if (device->physical_device->ps_wave_size == 32)
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@ -1538,12 +1538,11 @@ struct radv_event {
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struct radv_shader_module;
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struct radv_shader_module;
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#define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
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#define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
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#define RADV_HASH_SHADER_SISCHED (1 << 1)
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#define RADV_HASH_SHADER_NO_NGG (1 << 1)
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#define RADV_HASH_SHADER_NO_NGG (1 << 2)
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#define RADV_HASH_SHADER_CS_WAVE32 (1 << 2)
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#define RADV_HASH_SHADER_CS_WAVE32 (1 << 3)
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#define RADV_HASH_SHADER_PS_WAVE32 (1 << 3)
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#define RADV_HASH_SHADER_PS_WAVE32 (1 << 4)
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#define RADV_HASH_SHADER_GE_WAVE32 (1 << 4)
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#define RADV_HASH_SHADER_GE_WAVE32 (1 << 5)
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#define RADV_HASH_SHADER_ACO (1 << 5)
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#define RADV_HASH_SHADER_ACO (1 << 6)
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void
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void
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radv_hash_shaders(unsigned char *hash,
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radv_hash_shaders(unsigned char *hash,
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@ -1122,8 +1122,6 @@ shader_variant_compile(struct radv_device *device,
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bool thread_compiler;
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bool thread_compiler;
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tm_options |= AC_TM_SUPPORTS_SPILL;
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tm_options |= AC_TM_SUPPORTS_SPILL;
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if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
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tm_options |= AC_TM_SISCHED;
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if (options->check_ir)
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if (options->check_ir)
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tm_options |= AC_TM_CHECK_IR;
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tm_options |= AC_TM_CHECK_IR;
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if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
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if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
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