From b2455e1ccb566a239fd01db337d2f2a43652b3a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 7 Jul 2022 20:08:43 -0400 Subject: [PATCH] gallium/radeon: require radeon DRM 2.45.0 from April 2016 This removes most non-radeonsi workarounds. Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/r300/r300_emit.c | 2 +- src/gallium/drivers/r300/r300_state.c | 2 +- src/gallium/drivers/r300/r300_texture_desc.c | 2 +- src/gallium/drivers/r600/evergreen_state.c | 17 +--- src/gallium/drivers/r600/r600_buffer_common.c | 24 ----- src/gallium/drivers/r600/r600_pipe.c | 54 +++------- src/gallium/drivers/r600/r600_query.c | 5 +- src/gallium/drivers/r600/r600_state.c | 6 +- src/gallium/drivers/r600/r600_texture.c | 4 - src/gallium/drivers/r600/radeon_vce.c | 3 +- src/gallium/drivers/radeonsi/radeon_vce.c | 5 +- src/gallium/include/winsys/radeon_winsys.h | 2 +- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 3 - .../winsys/radeon/drm/radeon_drm_winsys.c | 98 +++++++------------ 14 files changed, 64 insertions(+), 163 deletions(-) diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index f28cdb7252f..08cd544871e 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -435,7 +435,7 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state) OUT_CS_REG(R300_RB3D_CMASK_OFFSET0, 0); OUT_CS_REG(R300_RB3D_CMASK_PITCH0, surf->pitch_cmask); OUT_CS_REG(R300_RB3D_COLOR_CLEAR_VALUE, r300->color_clear_value); - if (r300->screen->caps.is_r500 && r300->screen->info.drm_minor >= 29) { + if (r300->screen->caps.is_r500) { OUT_CS_REG_SEQ(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2); OUT_CS(r300->color_clear_value_ar); OUT_CS(r300->color_clear_value_gb); diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 4e8c2eca754..2e9126db5bb 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -890,7 +890,7 @@ void r300_mark_fb_state_dirty(struct r300_context *r300, if (r300->cmask_in_use) { r300->fb_state.size += 6; - if (r300->screen->caps.is_r500 && r300->screen->info.drm_minor >= 29) { + if (r300->screen->caps.is_r500) { r300->fb_state.size += 3; } } diff --git a/src/gallium/drivers/r300/r300_texture_desc.c b/src/gallium/drivers/r300/r300_texture_desc.c index 6d86b129a04..1b6f51bda9d 100644 --- a/src/gallium/drivers/r300/r300_texture_desc.c +++ b/src/gallium/drivers/r300/r300_texture_desc.c @@ -432,7 +432,7 @@ static void r300_setup_cmask_properties(struct r300_screen *screen, /* FP16 AA needs R500 and a fairly new DRM. */ if ((tex->b.format == PIPE_FORMAT_R16G16B16A16_FLOAT || tex->b.format == PIPE_FORMAT_R16G16B16X16_FLOAT) && - (!screen->caps.is_r500 || screen->info.drm_minor < 29)) { + !screen->caps.is_r500) { return; } diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 553ebf28e21..ee124034df6 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1424,11 +1424,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, S_028044_TILE_SPLIT(stile_split); } else { surf->db_stencil_base = offset; - /* DRM 2.6.18 allows the INVALID format to disable stencil. - * Older kernels are out of luck. */ - surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ? - S_028044_FORMAT(V_028044_STENCIL_INVALID) : - S_028044_FORMAT(V_028044_STENCIL_8); + surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); } if (r600_htile_enabled(rtex, level)) { @@ -1585,7 +1581,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, if (state->zsbuf) { rctx->framebuffer.atom.num_dw += 24; rctx->framebuffer.atom.num_dw += 2; - } else if (rctx->screen->b.info.drm_minor >= 18) { + } else { rctx->framebuffer.atom.num_dw += 4; } @@ -1952,9 +1948,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */ radeon_emit(cs, reloc); - } else if (rctx->screen->b.info.drm_minor >= 18) { - /* DRM 2.6.18 allows the INVALID format to disable depth/stencil. - * Older kernels are out of luck. */ + } else { radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */ radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */ @@ -3539,7 +3533,6 @@ void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) { - struct r600_context *rctx = (struct r600_context *)ctx; struct r600_command_buffer *cb = &shader->command_buffer; struct r600_shader *rshader = &shader->shader; struct r600_shader *cp_shader = &shader->gs_copy_shader->shader; @@ -3560,11 +3553,9 @@ void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE, r600_conv_prim_to_gs_out(shader->selector->gs_output_prim)); - if (rctx->screen->b.info.drm_minor >= 35) { - r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT, + r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT, S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) | S_028B90_ENABLE(shader->selector->gs_num_invocations > 0)); - } r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4); r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2); r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2); diff --git a/src/gallium/drivers/r600/r600_buffer_common.c b/src/gallium/drivers/r600/r600_buffer_common.c index f490dbfa658..8b4c6a94dab 100644 --- a/src/gallium/drivers/r600/r600_buffer_common.c +++ b/src/gallium/drivers/r600/r600_buffer_common.c @@ -125,15 +125,6 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen, res->domains = RADEON_DOMAIN_GTT; break; case PIPE_USAGE_DYNAMIC: - /* Older kernels didn't always flush the HDP cache before - * CS execution - */ - if (rscreen->info.drm_minor < 40) { - res->domains = RADEON_DOMAIN_GTT; - res->flags |= RADEON_FLAG_GTT_WC; - break; - } - FALLTHROUGH; case PIPE_USAGE_DEFAULT: case PIPE_USAGE_IMMUTABLE: default: @@ -144,21 +135,6 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen, break; } - if (res->b.b.target == PIPE_BUFFER && - res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT | - PIPE_RESOURCE_FLAG_MAP_COHERENT)) { - /* Use GTT for all persistent mappings with older - * kernels, because they didn't always flush the HDP - * cache before CS execution. - * - * Write-combined CPU mappings are fine, the kernel - * ensures all CPU writes finish before the GPU - * executes a command stream. - */ - if (rscreen->info.drm_minor < 40) - res->domains = RADEON_DOMAIN_GTT; - } - /* Tiled textures are unmappable. Always put them in VRAM. */ if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) || res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) { diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 51afc188595..5e4ee52d874 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -332,7 +332,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return 64 * 1024 * 1024; case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: - return rscreen->b.info.drm_minor >= 43; + return 1; case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr; @@ -365,10 +365,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_GLSL_FEATURE_LEVEL: if (family >= CHIP_CEDAR) return is_nir_enabled(&rscreen->b) ? 450 : 430; - /* pre-evergreen geom shaders need newer kernel */ - if (rscreen->b.info.drm_minor >= 37) - return 330; - return 140; + return 330; /* Supported except the original R600. */ case PIPE_CAP_INDEP_BLEND_ENABLE: @@ -393,7 +390,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return family >= CHIP_CEDAR ? 4 : 0; case PIPE_CAP_DRAW_INDIRECT: /* kernel command checker support is also required */ - return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41; + return family >= CHIP_CEDAR; case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: return family >= CHIP_CEDAR ? 0 : 1; @@ -494,10 +491,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* Timer queries, present when the clock frequency is non zero. */ case PIPE_CAP_QUERY_TIME_ELAPSED: - return rscreen->b.info.clock_crystal_freq != 0; case PIPE_CAP_QUERY_TIMESTAMP: - return rscreen->b.info.drm_minor >= 20 && - rscreen->b.info.clock_crystal_freq != 0; + return rscreen->b.info.clock_crystal_freq != 0; case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: case PIPE_CAP_MIN_TEXEL_OFFSET: @@ -562,12 +557,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_VERTEX: break; case PIPE_SHADER_GEOMETRY: - if (rscreen->b.family >= CHIP_CEDAR) - break; - /* pre-evergreen geom shaders need newer kernel */ - if (rscreen->b.info.drm_minor >= 37) - break; - return 0; + break; case PIPE_SHADER_TESS_CTRL: case PIPE_SHADER_TESS_EVAL: case PIPE_SHADER_COMPUTE: @@ -737,49 +727,27 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws, return NULL; } - /* Figure out streamout kernel support. */ - switch (rscreen->b.gfx_level) { - case R600: - if (rscreen->b.family < CHIP_RS780) { - rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14; - } else { - rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23; - } - break; - case R700: - rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17; - break; - case EVERGREEN: - case CAYMAN: - rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14; - break; - default: - rscreen->b.has_streamout = FALSE; - break; - } + rscreen->b.has_streamout = true; + + rscreen->has_msaa = true; /* MSAA support. */ switch (rscreen->b.gfx_level) { case R600: case R700: - rscreen->has_msaa = rscreen->b.info.drm_minor >= 22; rscreen->has_compressed_msaa_texturing = false; break; case EVERGREEN: - rscreen->has_msaa = rscreen->b.info.drm_minor >= 19; - rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24; + rscreen->has_compressed_msaa_texturing = true; break; case CAYMAN: - rscreen->has_msaa = rscreen->b.info.drm_minor >= 19; rscreen->has_compressed_msaa_texturing = true; break; default: - rscreen->has_msaa = FALSE; rscreen->has_compressed_msaa_texturing = false; } - rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 && - !(rscreen->b.debug_flags & DBG_NO_CP_DMA); + rscreen->b.has_cp_dma = !(rscreen->b.debug_flags & DBG_NO_CP_DMA); rscreen->b.barrier_flags.cp_to_L2 = R600_CONTEXT_INV_VERTEX_CACHE | @@ -792,7 +760,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws, /* Create the auxiliary context. This must be done last. */ rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0); - rscreen->has_atomics = rscreen->b.info.drm_minor >= 44; + rscreen->has_atomics = true; #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */ struct pipe_resource templ = {}; diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c index f9400734951..7fdca9d0f6c 100644 --- a/src/gallium/drivers/r600/r600_query.c +++ b/src/gallium/drivers/r600/r600_query.c @@ -2029,10 +2029,7 @@ static const struct pipe_driver_query_info r600_driver_query_list[] = { static unsigned r600_get_num_queries(struct r600_common_screen *rscreen) { - if (rscreen->info.drm_minor >= 42) - return ARRAY_SIZE(r600_driver_query_list); - else - return ARRAY_SIZE(r600_driver_query_list) - 25; + return ARRAY_SIZE(r600_driver_query_list); } static int r600_get_driver_query_info(struct pipe_screen *screen, diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 95f90d3b362..0b200782fab 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1216,7 +1216,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, } if (rctx->framebuffer.state.zsbuf) { rctx->framebuffer.atom.num_dw += 16; - } else if (rctx->screen->b.info.drm_minor >= 18) { + } else { rctx->framebuffer.atom.num_dw += 3; } if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) { @@ -1470,9 +1470,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); sbu |= SURFACE_BASE_UPDATE_DEPTH; - } else if (rctx->screen->b.info.drm_minor >= 18) { - /* DRM 2.6.18 allows the INVALID format to disable depth/stencil. - * Older kernels are out of luck. */ + } else { radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID)); } diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 9ef5f81fc36..fc65df682bf 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -756,10 +756,6 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen, rtex->surface.meta_size = 0; - if (rscreen->gfx_level <= EVERGREEN && - rscreen->info.drm_minor < 26) - return; - /* HW bug on R6xx. */ if (rscreen->gfx_level == R600 && (rtex->resource.b.b.width0 > 7680 || diff --git a/src/gallium/drivers/r600/radeon_vce.c b/src/gallium/drivers/r600/radeon_vce.c index 3742888121a..9bf6de36bd6 100644 --- a/src/gallium/drivers/r600/radeon_vce.c +++ b/src/gallium/drivers/r600/radeon_vce.c @@ -415,8 +415,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context, if (!enc) return NULL; - if (rscreen->info.drm_minor >= 42) - enc->use_vui = true; + enc->use_vui = true; enc->base = *templ; enc->base.context = context; diff --git a/src/gallium/drivers/radeonsi/radeon_vce.c b/src/gallium/drivers/radeonsi/radeon_vce.c index 5767d8510be..d269b97287f 100644 --- a/src/gallium/drivers/radeonsi/radeon_vce.c +++ b/src/gallium/drivers/radeonsi/radeon_vce.c @@ -404,8 +404,9 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context, if (sscreen->info.is_amdgpu) enc->use_vm = true; - if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) || sscreen->info.is_amdgpu) - enc->use_vui = true; + + enc->use_vui = true; + if (sscreen->info.family >= CHIP_TONGA && sscreen->info.family != CHIP_STONEY && sscreen->info.family != CHIP_POLARIS11 && sscreen->info.family != CHIP_POLARIS12 && sscreen->info.family != CHIP_VEGAM) diff --git a/src/gallium/include/winsys/radeon_winsys.h b/src/gallium/include/winsys/radeon_winsys.h index 3f6eeb04d53..04ea5963d84 100644 --- a/src/gallium/include/winsys/radeon_winsys.h +++ b/src/gallium/include/winsys/radeon_winsys.h @@ -116,7 +116,7 @@ enum radeon_value_id RADEON_VRAM_USAGE, RADEON_VRAM_VIS_USAGE, RADEON_GTT_USAGE, - RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */ + RADEON_GPU_TEMPERATURE, RADEON_CURRENT_SCLK, RADEON_CURRENT_MCLK, RADEON_CS_THREAD_TIME, diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 630abcd7418..9a67434398e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -179,9 +179,6 @@ static enum radeon_bo_domain radeon_bo_get_initial_domain( struct radeon_bo *bo = (struct radeon_bo*)buf; struct drm_radeon_gem_op args; - if (bo->rws->info.drm_minor < 38) - return RADEON_DOMAIN_VRAM_GTT; - memset(&args, 0, sizeof(args)); args.handle = bo->handle; args.op = RADEON_GEM_OP_GET_INITIAL_DOMAIN; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 1311056518c..1f83a8a7989 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -153,9 +153,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) /* Get DRM version. */ version = drmGetVersion(ws->fd); if (version->version_major != 2 || - version->version_minor < 12) { + version->version_minor < 45) { fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is " - "only compatible with 2.12.0 (kernel 3.2) or later.\n", + "only compatible with 2.45.0 (kernel 4.7) or later.\n", __FUNCTION__, version->version_major, version->version_minor, @@ -308,28 +308,27 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) /* Check for dma */ ws->info.ip[AMD_IP_SDMA].num_queues = 0; /* DMA is disabled on R700. There is IB corruption and hangs. */ - if (ws->info.gfx_level >= EVERGREEN && ws->info.drm_minor >= 27) { + if (ws->info.gfx_level >= EVERGREEN) { ws->info.ip[AMD_IP_SDMA].num_queues = 1; } /* Check for UVD and VCE */ ws->info.vce_fw_version = 0x00000000; - if (ws->info.drm_minor >= 32) { - uint32_t value = RADEON_CS_RING_UVD; - if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, - "UVD Ring working", &value)) { - ws->info.ip[AMD_IP_UVD].num_queues = 1; - } - value = RADEON_CS_RING_VCE; - if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, - NULL, &value) && value) { + uint32_t value = RADEON_CS_RING_UVD; + if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, + "UVD Ring working", &value)) { + ws->info.ip[AMD_IP_UVD].num_queues = 1; + } - if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION, - "VCE FW version", &value)) { - ws->info.vce_fw_version = value; - ws->info.ip[AMD_IP_VCE].num_queues = 1; - } + value = RADEON_CS_RING_VCE; + if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, + NULL, &value) && value) { + + if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION, + "VCE FW version", &value)) { + ws->info.vce_fw_version = value; + ws->info.ip[AMD_IP_VCE].num_queues = 1; } } @@ -372,12 +371,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) else ws->info.max_heap_size_kb = ws->info.gart_size_kb; - /* Old kernel driver limitation for allocation sizes. We only use this to limit per-buffer - * allocation size. - */ - if (ws->info.drm_minor < 40) - ws->info.max_heap_size_kb = MIN2(ws->info.max_heap_size_kb, 256 * 1024); - /* Both 32-bit and 64-bit address spaces only have 4GB. * This is a limitation of the VM allocator in the winsys. */ @@ -457,19 +450,19 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) &ws->info.enabled_rb_mask); ws->info.r600_has_virtual_memory = false; - if (ws->info.drm_minor >= 13) { - uint32_t ib_vm_max_size; - ws->info.r600_has_virtual_memory = true; - if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL, - &ws->va_start)) - ws->info.r600_has_virtual_memory = false; - if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL, - &ib_vm_max_size)) - ws->info.r600_has_virtual_memory = false; - radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL, - &ws->va_unmap_working); - } + uint32_t ib_vm_max_size; + + ws->info.r600_has_virtual_memory = true; + if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL, + &ws->va_start)) + ws->info.r600_has_virtual_memory = false; + if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL, + &ib_vm_max_size)) + ws->info.r600_has_virtual_memory = false; + radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL, + &ws->va_unmap_working); + if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false)) ws->info.r600_has_virtual_memory = false; } @@ -577,27 +570,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->accel_working2 < 3); ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ ws->info.ib_alignment = 4096; - ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40; + ws->info.kernel_flushes_hdp_before_ib = true; /* HTILE is broken with 1D tiling on old kernels and GFX7. */ - ws->info.htile_cmask_support_1d_tiling = ws->info.gfx_level != GFX7 || - ws->info.drm_minor >= 38; + ws->info.htile_cmask_support_1d_tiling = true; ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48; ws->info.has_bo_metadata = false; - ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43; + ws->info.has_gpu_reset_status_query = true; ws->info.has_eqaa_surface_allocator = false; - ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31; - /* Old kernels disallowed register writes via COPY_DATA - * that are used for indirect compute dispatches. */ - ws->info.has_indirect_compute_dispatch = ws->info.gfx_level == GFX7 || - (ws->info.gfx_level == GFX6 && - ws->info.drm_minor >= 45); + ws->info.has_format_bc1_through_bc7 = true; + ws->info.has_indirect_compute_dispatch = true; /* GFX6 doesn't support unaligned loads. */ ws->info.has_unaligned_shader_loads = ws->info.gfx_level == GFX7 && ws->info.drm_minor >= 50; ws->info.has_sparse_vm_mappings = false; - /* 2D tiling on GFX7 is supported since DRM 2.35.0 */ - ws->info.has_2d_tiling = ws->info.gfx_level <= GFX6 || ws->info.drm_minor >= 35; - ws->info.has_read_registers_query = ws->info.drm_minor >= 42; + ws->info.has_2d_tiling = true; + ws->info.has_read_registers_query = true; ws->info.max_alignment = 1024*1024; ws->info.has_graphics = true; ws->info.cpdma_prefetch_writes_memory = true; @@ -710,7 +697,7 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws, case RADEON_NUM_MAPPED_BUFFERS: return ws->num_mapped_buffers; case RADEON_TIMESTAMP: - if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) { + if (ws->gen < DRV_R600) { assert(0); return 0; } @@ -921,17 +908,8 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config, ws->vm32.start = ws->va_start; ws->vm32.end = 1ull << 32; - /* The maximum is 8GB of virtual address space limited by the kernel. - * It's obviously not enough for bigger cards, like Hawaiis with 4GB - * and 8GB of physical memory and 4GB of GART. - * - * Older kernels set the limit to 4GB, which is even worse, so they only - * have 32-bit address space. - */ - if (ws->info.drm_minor >= 41) { - ws->vm64.start = 1ull << 32; - ws->vm64.end = 1ull << 33; - } + ws->vm64.start = 1ull << 32; + ws->vm64.end = 1ull << 33; /* TTM aligns the BO size to the CPU page size */ ws->info.gart_page_size = sysconf(_SC_PAGESIZE);