freedreno/a6xx: update perfcntr registers (declare as arrays)
Signed-off-by: Jonathan Marek <jonathan@marek.ca> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8423>
This commit is contained in:
Jonathan Marek
Marge Bot
parent
72f00fe72e
commit
b15d4484f8
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@ -332,263 +332,263 @@ registers:
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00000000 0x23b: 00000000
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00000000 0x23c: 00000000
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00000000 0x23d: 00000000
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1a357e31 RBBM_PERFCTR_CP_0_LO: 0x1a357e31
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80405044 RBBM_PERFCTR_CP_0_HI: 0x80405044
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0731fe39 RBBM_PERFCTR_CP_1_LO: 0x731fe39
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00011001 RBBM_PERFCTR_CP_1_HI: 0x11001
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07337e41 RBBM_PERFCTR_CP_2_LO: 0x7337e41
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85001004 RBBM_PERFCTR_CP_2_HI: 0x85001004
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0b317e49 RBBM_PERFCTR_CP_3_LO: 0xb317e49
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40000000 RBBM_PERFCTR_CP_3_HI: 0x40000000
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07317e95 RBBM_PERFCTR_CP_4_LO: 0x7317e95
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00800008 RBBM_PERFCTR_CP_4_HI: 0x800008
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07317e59 RBBM_PERFCTR_CP_5_LO: 0x7317e59
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04000000 RBBM_PERFCTR_CP_5_HI: 0x4000000
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8771808b RBBM_PERFCTR_CP_6_LO: 0x8771808b
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00009000 RBBM_PERFCTR_CP_6_HI: 0x9000
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0b31826b RBBM_PERFCTR_CP_7_LO: 0xb31826b
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00000000 RBBM_PERFCTR_CP_7_HI: 0
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07b28675 RBBM_PERFCTR_CP_8_LO: 0x7b28675
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00020080 RBBM_PERFCTR_CP_8_HI: 0x20080
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0731be99 RBBM_PERFCTR_CP_9_LO: 0x731be99
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00000000 RBBM_PERFCTR_CP_9_HI: 0
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17317e83 RBBM_PERFCTR_CP_10_LO: 0x17317e83
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008c0004 RBBM_PERFCTR_CP_10_HI: 0x8c0004
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0bd182c9 RBBM_PERFCTR_CP_11_LO: 0xbd182c9
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00800000 RBBM_PERFCTR_CP_11_HI: 0x800000
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07318491 RBBM_PERFCTR_CP_12_LO: 0x7318491
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00000000 RBBM_PERFCTR_CP_12_HI: 0
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17317ed9 RBBM_PERFCTR_CP_13_LO: 0x17317ed9
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00000020 RBBM_PERFCTR_CP_13_HI: 0x20
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073180a3 RBBM_PERFCTR_RBBM_0_LO: 0x73180a3
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00010044 RBBM_PERFCTR_RBBM_0_HI: 0x10044
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07317eab RBBM_PERFCTR_RBBM_1_LO: 0x7317eab
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01008000 RBBM_PERFCTR_RBBM_1_HI: 0x1008000
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4731a6b3 RBBM_PERFCTR_RBBM_2_LO: 0x4731a6b3
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00000000 RBBM_PERFCTR_RBBM_2_HI: 0
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0731febb RBBM_PERFCTR_RBBM_3_LO: 0x731febb
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00000000 RBBM_PERFCTR_RBBM_3_HI: 0
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010011b6 RBBM_PERFCTR_PC_0_LO: 0x10011b6
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00000080 RBBM_PERFCTR_PC_0_HI: 0x80
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00000f96 RBBM_PERFCTR_PC_1_LO: 0xf96
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50000000 RBBM_PERFCTR_PC_1_HI: 0x50000000
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40041f96 RBBM_PERFCTR_PC_2_LO: 0x40041f96
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20040800 RBBM_PERFCTR_PC_2_HI: 0x20040800
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00000f96 RBBM_PERFCTR_PC_3_LO: 0xf96
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01008004 RBBM_PERFCTR_PC_3_HI: 0x1008004
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00021016 RBBM_PERFCTR_PC_4_LO: 0x21016
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00000008 RBBM_PERFCTR_PC_4_HI: 0x8
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00211096 RBBM_PERFCTR_PC_5_LO: 0x211096
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04010000 RBBM_PERFCTR_PC_5_HI: 0x4010000
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00300fb6 RBBM_PERFCTR_PC_6_LO: 0x300fb6
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10001006 RBBM_PERFCTR_PC_6_HI: 0x10001006
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00000f9a RBBM_PERFCTR_PC_7_LO: 0xf9a
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00200000 RBBM_PERFCTR_PC_7_HI: 0x200000
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04020b81 RBBM_PERFCTR_VFD_0_LO: 0x4020b81
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28046008 RBBM_PERFCTR_VFD_0_HI: 0x28046008
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0020037d RBBM_PERFCTR_VFD_1_LO: 0x20037d
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00052000 RBBM_PERFCTR_VFD_1_HI: 0x52000
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000003bd RBBM_PERFCTR_VFD_2_LO: 0x3bd
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00040000 RBBM_PERFCTR_VFD_2_HI: 0x40000
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0800037d RBBM_PERFCTR_VFD_3_LO: 0x800037d
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00000000 RBBM_PERFCTR_VFD_3_HI: 0
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0050469f RBBM_PERFCTR_VFD_4_LO: 0x50469f
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10000020 RBBM_PERFCTR_VFD_4_HI: 0x10000020
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0000037d RBBM_PERFCTR_VFD_5_LO: 0x37d
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00000000 RBBM_PERFCTR_VFD_5_HI: 0
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0000039f RBBM_PERFCTR_VFD_6_LO: 0x39f
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00000000 RBBM_PERFCTR_VFD_6_HI: 0
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0000037e RBBM_PERFCTR_VFD_7_LO: 0x37e
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04804000 RBBM_PERFCTR_VFD_7_HI: 0x4804000
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000011f4 RBBM_PERFCTR_HLSQ_0_LO: 0x11f4
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40000140 RBBM_PERFCTR_HLSQ_0_HI: 0x40000140
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000411f4 RBBM_PERFCTR_HLSQ_1_LO: 0x411f4
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04020040 RBBM_PERFCTR_HLSQ_1_HI: 0x4020040
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200092f4 RBBM_PERFCTR_HLSQ_2_LO: 0x200092f4
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40800001 RBBM_PERFCTR_HLSQ_2_HI: 0x40800001
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000019f4 RBBM_PERFCTR_HLSQ_3_LO: 0x19f4
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00000000 RBBM_PERFCTR_HLSQ_3_HI: 0
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00285216 RBBM_PERFCTR_HLSQ_4_LO: 0x285216
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04009420 RBBM_PERFCTR_HLSQ_4_HI: 0x4009420
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040031f4 RBBM_PERFCTR_HLSQ_5_LO: 0x40031f4
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00000000 RBBM_PERFCTR_HLSQ_5_HI: 0
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02402cb6 RBBM_PERFCTR_VPC_0_LO: 0x2402cb6
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05000080 RBBM_PERFCTR_VPC_0_HI: 0x5000080
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000005d6 RBBM_PERFCTR_VPC_1_LO: 0x5d6
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00820000 RBBM_PERFCTR_VPC_1_HI: 0x820000
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000004fa RBBM_PERFCTR_VPC_2_LO: 0x4fa
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00000000 RBBM_PERFCTR_VPC_2_HI: 0
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00000cb6 RBBM_PERFCTR_VPC_3_LO: 0xcb6
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40006000 RBBM_PERFCTR_VPC_3_HI: 0x40006000
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0c1004b6 RBBM_PERFCTR_VPC_4_LO: 0xc1004b6
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00000800 RBBM_PERFCTR_VPC_4_HI: 0x800
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040204ba RBBM_PERFCTR_VPC_5_LO: 0x40204ba
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00000004 RBBM_PERFCTR_VPC_5_HI: 0x4
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00000f36 RBBM_PERFCTR_CCU_0_LO: 0xf36
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00000104 RBBM_PERFCTR_CCU_0_HI: 0x104
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09000aa6 RBBM_PERFCTR_CCU_1_LO: 0x9000aa6
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00000060 RBBM_PERFCTR_CCU_1_HI: 0x60
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00010aca RBBM_PERFCTR_CCU_2_LO: 0x10aca
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01000400 RBBM_PERFCTR_CCU_2_HI: 0x1000400
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00000ac8 RBBM_PERFCTR_CCU_3_LO: 0xac8
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00004000 RBBM_PERFCTR_CCU_3_HI: 0x4000
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80000aa6 RBBM_PERFCTR_CCU_4_LO: 0x80000aa6
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04850000 RBBM_PERFCTR_CCU_4_HI: 0x4850000
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00480168 RBBM_PERFCTR_TSE_0_LO: 0x480168
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00000820 RBBM_PERFCTR_TSE_0_HI: 0x820
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2021016c RBBM_PERFCTR_TSE_1_LO: 0x2021016c
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00880000 RBBM_PERFCTR_TSE_1_HI: 0x880000
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00000968 RBBM_PERFCTR_TSE_2_LO: 0x968
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00002000 RBBM_PERFCTR_TSE_2_HI: 0x2000
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80102568 RBBM_PERFCTR_TSE_3_LO: 0x80102568
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08004200 RBBM_PERFCTR_TSE_3_HI: 0x8004200
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000000fb RBBM_PERFCTR_RAS_0_LO: 0xfb
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00004000 RBBM_PERFCTR_RAS_0_HI: 0x4000
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020002ec RBBM_PERFCTR_RAS_1_LO: 0x20002ec
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10010004 RBBM_PERFCTR_RAS_1_HI: 0x10010004
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001010eb RBBM_PERFCTR_RAS_2_LO: 0x1010eb
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20008010 RBBM_PERFCTR_RAS_2_HI: 0x20008010
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4000016b RBBM_PERFCTR_RAS_3_LO: 0x4000016b
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01801000 RBBM_PERFCTR_RAS_3_HI: 0x1801000
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040003fb RBBM_PERFCTR_UCHE_0_LO: 0x40003fb
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00000400 RBBM_PERFCTR_UCHE_0_HI: 0x400
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00000a0c RBBM_PERFCTR_UCHE_1_LO: 0xa0c
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00007010 RBBM_PERFCTR_UCHE_1_HI: 0x7010
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000021ff RBBM_PERFCTR_UCHE_2_LO: 0x21ff
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00000000 RBBM_PERFCTR_UCHE_2_HI: 0
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0400021b RBBM_PERFCTR_UCHE_3_LO: 0x400021b
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00000020 RBBM_PERFCTR_UCHE_3_HI: 0x20
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00108dfb RBBM_PERFCTR_UCHE_4_LO: 0x108dfb
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20040000 RBBM_PERFCTR_UCHE_4_HI: 0x20040000
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105082fb RBBM_PERFCTR_UCHE_5_LO: 0x105082fb
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04010110 RBBM_PERFCTR_UCHE_5_HI: 0x4010110
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000202fb RBBM_PERFCTR_UCHE_6_LO: 0x202fb
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00000810 RBBM_PERFCTR_UCHE_6_HI: 0x810
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00c007fb RBBM_PERFCTR_UCHE_7_LO: 0xc007fb
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01000800 RBBM_PERFCTR_UCHE_7_HI: 0x1000800
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480001fb RBBM_PERFCTR_UCHE_8_LO: 0x480001fb
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04000000 RBBM_PERFCTR_UCHE_8_HI: 0x4000000
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000012fb RBBM_PERFCTR_UCHE_9_LO: 0x12fb
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00820428 RBBM_PERFCTR_UCHE_9_HI: 0x820428
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0010021b RBBM_PERFCTR_UCHE_10_LO: 0x10021b
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08000000 RBBM_PERFCTR_UCHE_10_HI: 0x8000000
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100001fb RBBM_PERFCTR_UCHE_11_LO: 0x100001fb
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08001044 RBBM_PERFCTR_UCHE_11_HI: 0x8001044
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480803c0 RBBM_PERFCTR_TP_0_LO: 0x480803c0
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404b0000 RBBM_PERFCTR_TP_0_HI: 0x404b0000
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00002bd0 RBBM_PERFCTR_TP_1_LO: 0x2bd0
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30000130 RBBM_PERFCTR_TP_1_HI: 0x30000130
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000003c0 RBBM_PERFCTR_TP_2_LO: 0x3c0
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00000080 RBBM_PERFCTR_TP_2_HI: 0x80
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30200400 RBBM_PERFCTR_TP_3_LO: 0x30200400
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80002080 RBBM_PERFCTR_TP_3_HI: 0x80002080
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000003c0 RBBM_PERFCTR_TP_4_LO: 0x3c0
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00a00000 RBBM_PERFCTR_TP_4_HI: 0xa00000
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048003c0 RBBM_PERFCTR_TP_5_LO: 0x48003c0
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42000900 RBBM_PERFCTR_TP_5_HI: 0x42000900
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200003c0 RBBM_PERFCTR_TP_6_LO: 0x200003c0
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00000000 RBBM_PERFCTR_TP_6_HI: 0
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030003e1 RBBM_PERFCTR_TP_7_LO: 0x30003e1
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c01c0000 RBBM_PERFCTR_TP_7_HI: 0xc01c0000
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020005c4 RBBM_PERFCTR_TP_8_LO: 0x20005c4
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00000000 RBBM_PERFCTR_TP_8_HI: 0
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0a0005c0 RBBM_PERFCTR_TP_9_LO: 0xa0005c0
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10008188 RBBM_PERFCTR_TP_9_HI: 0x10008188
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002813c4 RBBM_PERFCTR_TP_10_LO: 0x2813c4
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00000200 RBBM_PERFCTR_TP_10_HI: 0x200
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000007c0 RBBM_PERFCTR_TP_11_LO: 0x7c0
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00000802 RBBM_PERFCTR_TP_11_HI: 0x802
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028415c0 RBBM_PERFCTR_SP_0_LO: 0x28415c0
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00121000 RBBM_PERFCTR_SP_0_HI: 0x121000
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000411bc RBBM_PERFCTR_SP_1_LO: 0x411bc
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00010020 RBBM_PERFCTR_SP_1_HI: 0x10020
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400631b8 RBBM_PERFCTR_SP_2_LO: 0x400631b8
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00000800 RBBM_PERFCTR_SP_2_HI: 0x800
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000811c8 RBBM_PERFCTR_SP_3_LO: 0x811c8
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00010040 RBBM_PERFCTR_SP_3_HI: 0x10040
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000011f8 RBBM_PERFCTR_SP_4_LO: 0x11f8
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18000000 RBBM_PERFCTR_SP_4_HI: 0x18000000
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002051c0 RBBM_PERFCTR_SP_5_LO: 0x2051c0
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00800106 RBBM_PERFCTR_SP_5_HI: 0x800106
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004011b8 RBBM_PERFCTR_SP_6_LO: 0x4011b8
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40400000 RBBM_PERFCTR_SP_6_HI: 0x40400000
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200031b8 RBBM_PERFCTR_SP_7_LO: 0x200031b8
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41040100 RBBM_PERFCTR_SP_7_HI: 0x41040100
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001011bc RBBM_PERFCTR_SP_8_LO: 0x1011bc
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00000000 RBBM_PERFCTR_SP_8_HI: 0
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204011bc RBBM_PERFCTR_SP_9_LO: 0x204011bc
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00000001 RBBM_PERFCTR_SP_9_HI: 0x1
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040011b8 RBBM_PERFCTR_SP_10_LO: 0x40011b8
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02000000 RBBM_PERFCTR_SP_10_HI: 0x2000000
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340012b8 RBBM_PERFCTR_SP_11_LO: 0x340012b8
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004000c0 RBBM_PERFCTR_SP_11_HI: 0x4000c0
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c00015b8 RBBM_PERFCTR_SP_12_LO: 0xc00015b8
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00800040 RBBM_PERFCTR_SP_12_HI: 0x800040
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003041b9 RBBM_PERFCTR_SP_13_LO: 0x3041b9
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00000000 RBBM_PERFCTR_SP_13_HI: 0
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000019bc RBBM_PERFCTR_SP_14_LO: 0x19bc
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00080000 RBBM_PERFCTR_SP_14_HI: 0x80000
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400051b9 RBBM_PERFCTR_SP_15_LO: 0x400051b9
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10000900 RBBM_PERFCTR_SP_15_HI: 0x10000900
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002011b8 RBBM_PERFCTR_SP_16_LO: 0x2011b8
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00000000 RBBM_PERFCTR_SP_16_HI: 0
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000092c0 RBBM_PERFCTR_SP_17_LO: 0x92c0
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00000020 RBBM_PERFCTR_SP_17_HI: 0x20
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000012b8 RBBM_PERFCTR_SP_18_LO: 0x12b8
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00900020 RBBM_PERFCTR_SP_18_HI: 0x900020
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000811c0 RBBM_PERFCTR_SP_19_LO: 0x811c0
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129001a0 RBBM_PERFCTR_SP_19_HI: 0x129001a0
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000011b8 RBBM_PERFCTR_SP_20_LO: 0x11b8
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80000002 RBBM_PERFCTR_SP_20_HI: 0x80000002
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800011b8 RBBM_PERFCTR_SP_21_LO: 0x800011b8
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08000000 RBBM_PERFCTR_SP_21_HI: 0x8000000
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000011b8 RBBM_PERFCTR_SP_22_LO: 0x11b8
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2000a000 RBBM_PERFCTR_SP_22_HI: 0x2000a000
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044011c0 RBBM_PERFCTR_SP_23_LO: 0x44011c0
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84090000 RBBM_PERFCTR_SP_23_HI: 0x84090000
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00104984 RBBM_PERFCTR_RB_0_LO: 0x104984
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40000000 RBBM_PERFCTR_RB_0_HI: 0x40000000
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00040b04 RBBM_PERFCTR_RB_1_LO: 0x40b04
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00200470 RBBM_PERFCTR_RB_1_HI: 0x200470
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40000984 RBBM_PERFCTR_RB_2_LO: 0x40000984
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00820400 RBBM_PERFCTR_RB_2_HI: 0x820400
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00000986 RBBM_PERFCTR_RB_3_LO: 0x986
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10000000 RBBM_PERFCTR_RB_3_HI: 0x10000000
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00001d84 RBBM_PERFCTR_RB_4_LO: 0x1d84
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00000801 RBBM_PERFCTR_RB_4_HI: 0x801
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01040b04 RBBM_PERFCTR_RB_5_LO: 0x1040b04
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08002000 RBBM_PERFCTR_RB_5_HI: 0x8002000
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00000984 RBBM_PERFCTR_RB_6_LO: 0x984
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00000000 RBBM_PERFCTR_RB_6_HI: 0
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0000198c RBBM_PERFCTR_RB_7_LO: 0x198c
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0000000c RBBM_PERFCTR_RB_7_HI: 0xc
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20000233 RBBM_PERFCTR_VSC_0_LO: 0x20000233
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20000000 RBBM_PERFCTR_VSC_0_HI: 0x20000000
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00000333 RBBM_PERFCTR_VSC_1_LO: 0x333
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30d00100 RBBM_PERFCTR_VSC_1_HI: 0x30d00100
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00000355 RBBM_PERFCTR_LRZ_0_LO: 0x355
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00080004 RBBM_PERFCTR_LRZ_0_HI: 0x80004
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10000357 RBBM_PERFCTR_LRZ_1_LO: 0x10000357
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000005a0 RBBM_PERFCTR_LRZ_1_HI: 0x5a0
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00000353 RBBM_PERFCTR_LRZ_2_LO: 0x353
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00000100 RBBM_PERFCTR_LRZ_2_HI: 0x100
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04004357 RBBM_PERFCTR_LRZ_3_LO: 0x4004357
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050c0000 RBBM_PERFCTR_LRZ_3_HI: 0x50c0000
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00000010 RBBM_PERFCTR_CMP_0_LO: 0x10
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08000000 RBBM_PERFCTR_CMP_0_HI: 0x8000000
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05000204 RBBM_PERFCTR_CMP_1_LO: 0x5000204
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40000220 RBBM_PERFCTR_CMP_1_HI: 0x40000220
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00000000 RBBM_PERFCTR_CMP_2_LO: 0
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00000400 RBBM_PERFCTR_CMP_2_HI: 0x400
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00200000 RBBM_PERFCTR_CMP_3_LO: 0x200000
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11014000 RBBM_PERFCTR_CMP_3_HI: 0x11014000
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1a357e31 RBBM_PERFCTR_CP[0]+0: 1a357e31
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80405044 RBBM_PERFCTR_CP[0]+0x1: 80405044
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0731fe39 RBBM_PERFCTR_CP[0x1]+0: 0731fe39
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00011001 RBBM_PERFCTR_CP[0x1]+0x1: 00011001
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07337e41 RBBM_PERFCTR_CP[0x2]+0: 07337e41
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85001004 RBBM_PERFCTR_CP[0x2]+0x1: 85001004
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0b317e49 RBBM_PERFCTR_CP[0x3]+0: 0b317e49
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40000000 RBBM_PERFCTR_CP[0x3]+0x1: 40000000
|
||||
07317e95 RBBM_PERFCTR_CP[0x4]+0: 07317e95
|
||||
00800008 RBBM_PERFCTR_CP[0x4]+0x1: 00800008
|
||||
07317e59 RBBM_PERFCTR_CP[0x5]+0: 07317e59
|
||||
04000000 RBBM_PERFCTR_CP[0x5]+0x1: 04000000
|
||||
8771808b RBBM_PERFCTR_CP[0x6]+0: 8771808b
|
||||
00009000 RBBM_PERFCTR_CP[0x6]+0x1: 00009000
|
||||
0b31826b RBBM_PERFCTR_CP[0x7]+0: 0b31826b
|
||||
00000000 RBBM_PERFCTR_CP[0x7]+0x1: 00000000
|
||||
07b28675 RBBM_PERFCTR_CP[0x8]+0: 07b28675
|
||||
00020080 RBBM_PERFCTR_CP[0x8]+0x1: 00020080
|
||||
0731be99 RBBM_PERFCTR_CP[0x9]+0: 0731be99
|
||||
00000000 RBBM_PERFCTR_CP[0x9]+0x1: 00000000
|
||||
17317e83 RBBM_PERFCTR_CP[0xa]+0: 17317e83
|
||||
008c0004 RBBM_PERFCTR_CP[0xa]+0x1: 008c0004
|
||||
0bd182c9 RBBM_PERFCTR_CP[0xb]+0: 0bd182c9
|
||||
00800000 RBBM_PERFCTR_CP[0xb]+0x1: 00800000
|
||||
07318491 RBBM_PERFCTR_CP[0xc]+0: 07318491
|
||||
00000000 RBBM_PERFCTR_CP[0xc]+0x1: 00000000
|
||||
17317ed9 RBBM_PERFCTR_CP[0xd]+0: 17317ed9
|
||||
00000020 RBBM_PERFCTR_CP[0xd]+0x1: 00000020
|
||||
073180a3 RBBM_PERFCTR_RBBM[0]+0: 073180a3
|
||||
00010044 RBBM_PERFCTR_RBBM[0]+0x1: 00010044
|
||||
07317eab RBBM_PERFCTR_RBBM[0x1]+0: 07317eab
|
||||
01008000 RBBM_PERFCTR_RBBM[0x1]+0x1: 01008000
|
||||
4731a6b3 RBBM_PERFCTR_RBBM[0x2]+0: 4731a6b3
|
||||
00000000 RBBM_PERFCTR_RBBM[0x2]+0x1: 00000000
|
||||
0731febb RBBM_PERFCTR_RBBM[0x3]+0: 0731febb
|
||||
00000000 RBBM_PERFCTR_RBBM[0x3]+0x1: 00000000
|
||||
010011b6 RBBM_PERFCTR_PC[0]+0: 010011b6
|
||||
00000080 RBBM_PERFCTR_PC[0]+0x1: 00000080
|
||||
00000f96 RBBM_PERFCTR_PC[0x1]+0: 00000f96
|
||||
50000000 RBBM_PERFCTR_PC[0x1]+0x1: 50000000
|
||||
40041f96 RBBM_PERFCTR_PC[0x2]+0: 40041f96
|
||||
20040800 RBBM_PERFCTR_PC[0x2]+0x1: 20040800
|
||||
00000f96 RBBM_PERFCTR_PC[0x3]+0: 00000f96
|
||||
01008004 RBBM_PERFCTR_PC[0x3]+0x1: 01008004
|
||||
00021016 RBBM_PERFCTR_PC[0x4]+0: 00021016
|
||||
00000008 RBBM_PERFCTR_PC[0x4]+0x1: 00000008
|
||||
00211096 RBBM_PERFCTR_PC[0x5]+0: 00211096
|
||||
04010000 RBBM_PERFCTR_PC[0x5]+0x1: 04010000
|
||||
00300fb6 RBBM_PERFCTR_PC[0x6]+0: 00300fb6
|
||||
10001006 RBBM_PERFCTR_PC[0x6]+0x1: 10001006
|
||||
00000f9a RBBM_PERFCTR_PC[0x7]+0: 00000f9a
|
||||
00200000 RBBM_PERFCTR_PC[0x7]+0x1: 00200000
|
||||
04020b81 RBBM_PERFCTR_VFD[0]+0: 04020b81
|
||||
28046008 RBBM_PERFCTR_VFD[0]+0x1: 28046008
|
||||
0020037d RBBM_PERFCTR_VFD[0x1]+0: 0020037d
|
||||
00052000 RBBM_PERFCTR_VFD[0x1]+0x1: 00052000
|
||||
000003bd RBBM_PERFCTR_VFD[0x2]+0: 000003bd
|
||||
00040000 RBBM_PERFCTR_VFD[0x2]+0x1: 00040000
|
||||
0800037d RBBM_PERFCTR_VFD[0x3]+0: 0800037d
|
||||
00000000 RBBM_PERFCTR_VFD[0x3]+0x1: 00000000
|
||||
0050469f RBBM_PERFCTR_VFD[0x4]+0: 0050469f
|
||||
10000020 RBBM_PERFCTR_VFD[0x4]+0x1: 10000020
|
||||
0000037d RBBM_PERFCTR_VFD[0x5]+0: 0000037d
|
||||
00000000 RBBM_PERFCTR_VFD[0x5]+0x1: 00000000
|
||||
0000039f RBBM_PERFCTR_VFD[0x6]+0: 0000039f
|
||||
00000000 RBBM_PERFCTR_VFD[0x6]+0x1: 00000000
|
||||
0000037e RBBM_PERFCTR_VFD[0x7]+0: 0000037e
|
||||
04804000 RBBM_PERFCTR_VFD[0x7]+0x1: 04804000
|
||||
000011f4 RBBM_PERFCTR_HLSQ[0]+0: 000011f4
|
||||
40000140 RBBM_PERFCTR_HLSQ[0]+0x1: 40000140
|
||||
000411f4 RBBM_PERFCTR_HLSQ[0x1]+0: 000411f4
|
||||
04020040 RBBM_PERFCTR_HLSQ[0x1]+0x1: 04020040
|
||||
200092f4 RBBM_PERFCTR_HLSQ[0x2]+0: 200092f4
|
||||
40800001 RBBM_PERFCTR_HLSQ[0x2]+0x1: 40800001
|
||||
000019f4 RBBM_PERFCTR_HLSQ[0x3]+0: 000019f4
|
||||
00000000 RBBM_PERFCTR_HLSQ[0x3]+0x1: 00000000
|
||||
00285216 RBBM_PERFCTR_HLSQ[0x4]+0: 00285216
|
||||
04009420 RBBM_PERFCTR_HLSQ[0x4]+0x1: 04009420
|
||||
040031f4 RBBM_PERFCTR_HLSQ[0x5]+0: 040031f4
|
||||
00000000 RBBM_PERFCTR_HLSQ[0x5]+0x1: 00000000
|
||||
02402cb6 RBBM_PERFCTR_VPC[0]+0: 02402cb6
|
||||
05000080 RBBM_PERFCTR_VPC[0]+0x1: 05000080
|
||||
000005d6 RBBM_PERFCTR_VPC[0x1]+0: 000005d6
|
||||
00820000 RBBM_PERFCTR_VPC[0x1]+0x1: 00820000
|
||||
000004fa RBBM_PERFCTR_VPC[0x2]+0: 000004fa
|
||||
00000000 RBBM_PERFCTR_VPC[0x2]+0x1: 00000000
|
||||
00000cb6 RBBM_PERFCTR_VPC[0x3]+0: 00000cb6
|
||||
40006000 RBBM_PERFCTR_VPC[0x3]+0x1: 40006000
|
||||
0c1004b6 RBBM_PERFCTR_VPC[0x4]+0: 0c1004b6
|
||||
00000800 RBBM_PERFCTR_VPC[0x4]+0x1: 00000800
|
||||
040204ba RBBM_PERFCTR_VPC[0x5]+0: 040204ba
|
||||
00000004 RBBM_PERFCTR_VPC[0x5]+0x1: 00000004
|
||||
00000f36 RBBM_PERFCTR_CCU[0]+0: 00000f36
|
||||
00000104 RBBM_PERFCTR_CCU[0]+0x1: 00000104
|
||||
09000aa6 RBBM_PERFCTR_CCU[0x1]+0: 09000aa6
|
||||
00000060 RBBM_PERFCTR_CCU[0x1]+0x1: 00000060
|
||||
00010aca RBBM_PERFCTR_CCU[0x2]+0: 00010aca
|
||||
01000400 RBBM_PERFCTR_CCU[0x2]+0x1: 01000400
|
||||
00000ac8 RBBM_PERFCTR_CCU[0x3]+0: 00000ac8
|
||||
00004000 RBBM_PERFCTR_CCU[0x3]+0x1: 00004000
|
||||
80000aa6 RBBM_PERFCTR_CCU[0x4]+0: 80000aa6
|
||||
04850000 RBBM_PERFCTR_CCU[0x4]+0x1: 04850000
|
||||
00480168 RBBM_PERFCTR_TSE[0]+0: 00480168
|
||||
00000820 RBBM_PERFCTR_TSE[0]+0x1: 00000820
|
||||
2021016c RBBM_PERFCTR_TSE[0x1]+0: 2021016c
|
||||
00880000 RBBM_PERFCTR_TSE[0x1]+0x1: 00880000
|
||||
00000968 RBBM_PERFCTR_TSE[0x2]+0: 00000968
|
||||
00002000 RBBM_PERFCTR_TSE[0x2]+0x1: 00002000
|
||||
80102568 RBBM_PERFCTR_TSE[0x3]+0: 80102568
|
||||
08004200 RBBM_PERFCTR_TSE[0x3]+0x1: 08004200
|
||||
000000fb RBBM_PERFCTR_RAS[0]+0: 000000fb
|
||||
00004000 RBBM_PERFCTR_RAS[0]+0x1: 00004000
|
||||
020002ec RBBM_PERFCTR_RAS[0x1]+0: 020002ec
|
||||
10010004 RBBM_PERFCTR_RAS[0x1]+0x1: 10010004
|
||||
001010eb RBBM_PERFCTR_RAS[0x2]+0: 001010eb
|
||||
20008010 RBBM_PERFCTR_RAS[0x2]+0x1: 20008010
|
||||
4000016b RBBM_PERFCTR_RAS[0x3]+0: 4000016b
|
||||
01801000 RBBM_PERFCTR_RAS[0x3]+0x1: 01801000
|
||||
040003fb RBBM_PERFCTR_UCHE[0]+0: 040003fb
|
||||
00000400 RBBM_PERFCTR_UCHE[0]+0x1: 00000400
|
||||
00000a0c RBBM_PERFCTR_UCHE[0x1]+0: 00000a0c
|
||||
00007010 RBBM_PERFCTR_UCHE[0x1]+0x1: 00007010
|
||||
000021ff RBBM_PERFCTR_UCHE[0x2]+0: 000021ff
|
||||
00000000 RBBM_PERFCTR_UCHE[0x2]+0x1: 00000000
|
||||
0400021b RBBM_PERFCTR_UCHE[0x3]+0: 0400021b
|
||||
00000020 RBBM_PERFCTR_UCHE[0x3]+0x1: 00000020
|
||||
00108dfb RBBM_PERFCTR_UCHE[0x4]+0: 00108dfb
|
||||
20040000 RBBM_PERFCTR_UCHE[0x4]+0x1: 20040000
|
||||
105082fb RBBM_PERFCTR_UCHE[0x5]+0: 105082fb
|
||||
04010110 RBBM_PERFCTR_UCHE[0x5]+0x1: 04010110
|
||||
000202fb RBBM_PERFCTR_UCHE[0x6]+0: 000202fb
|
||||
00000810 RBBM_PERFCTR_UCHE[0x6]+0x1: 00000810
|
||||
00c007fb RBBM_PERFCTR_UCHE[0x7]+0: 00c007fb
|
||||
01000800 RBBM_PERFCTR_UCHE[0x7]+0x1: 01000800
|
||||
480001fb RBBM_PERFCTR_UCHE[0x8]+0: 480001fb
|
||||
04000000 RBBM_PERFCTR_UCHE[0x8]+0x1: 04000000
|
||||
000012fb RBBM_PERFCTR_UCHE[0x9]+0: 000012fb
|
||||
00820428 RBBM_PERFCTR_UCHE[0x9]+0x1: 00820428
|
||||
0010021b RBBM_PERFCTR_UCHE[0xa]+0: 0010021b
|
||||
08000000 RBBM_PERFCTR_UCHE[0xa]+0x1: 08000000
|
||||
100001fb RBBM_PERFCTR_UCHE[0xb]+0: 100001fb
|
||||
08001044 RBBM_PERFCTR_UCHE[0xb]+0x1: 08001044
|
||||
480803c0 RBBM_PERFCTR_TP[0]+0: 480803c0
|
||||
404b0000 RBBM_PERFCTR_TP[0]+0x1: 404b0000
|
||||
00002bd0 RBBM_PERFCTR_TP[0x1]+0: 00002bd0
|
||||
30000130 RBBM_PERFCTR_TP[0x1]+0x1: 30000130
|
||||
000003c0 RBBM_PERFCTR_TP[0x2]+0: 000003c0
|
||||
00000080 RBBM_PERFCTR_TP[0x2]+0x1: 00000080
|
||||
30200400 RBBM_PERFCTR_TP[0x3]+0: 30200400
|
||||
80002080 RBBM_PERFCTR_TP[0x3]+0x1: 80002080
|
||||
000003c0 RBBM_PERFCTR_TP[0x4]+0: 000003c0
|
||||
00a00000 RBBM_PERFCTR_TP[0x4]+0x1: 00a00000
|
||||
048003c0 RBBM_PERFCTR_TP[0x5]+0: 048003c0
|
||||
42000900 RBBM_PERFCTR_TP[0x5]+0x1: 42000900
|
||||
200003c0 RBBM_PERFCTR_TP[0x6]+0: 200003c0
|
||||
00000000 RBBM_PERFCTR_TP[0x6]+0x1: 00000000
|
||||
030003e1 RBBM_PERFCTR_TP[0x7]+0: 030003e1
|
||||
c01c0000 RBBM_PERFCTR_TP[0x7]+0x1: c01c0000
|
||||
020005c4 RBBM_PERFCTR_TP[0x8]+0: 020005c4
|
||||
00000000 RBBM_PERFCTR_TP[0x8]+0x1: 00000000
|
||||
0a0005c0 RBBM_PERFCTR_TP[0x9]+0: 0a0005c0
|
||||
10008188 RBBM_PERFCTR_TP[0x9]+0x1: 10008188
|
||||
002813c4 RBBM_PERFCTR_TP[0xa]+0: 002813c4
|
||||
00000200 RBBM_PERFCTR_TP[0xa]+0x1: 00000200
|
||||
000007c0 RBBM_PERFCTR_TP[0xb]+0: 000007c0
|
||||
00000802 RBBM_PERFCTR_TP[0xb]+0x1: 00000802
|
||||
028415c0 RBBM_PERFCTR_SP[0]+0: 028415c0
|
||||
00121000 RBBM_PERFCTR_SP[0]+0x1: 00121000
|
||||
000411bc RBBM_PERFCTR_SP[0x1]+0: 000411bc
|
||||
00010020 RBBM_PERFCTR_SP[0x1]+0x1: 00010020
|
||||
400631b8 RBBM_PERFCTR_SP[0x2]+0: 400631b8
|
||||
00000800 RBBM_PERFCTR_SP[0x2]+0x1: 00000800
|
||||
000811c8 RBBM_PERFCTR_SP[0x3]+0: 000811c8
|
||||
00010040 RBBM_PERFCTR_SP[0x3]+0x1: 00010040
|
||||
000011f8 RBBM_PERFCTR_SP[0x4]+0: 000011f8
|
||||
18000000 RBBM_PERFCTR_SP[0x4]+0x1: 18000000
|
||||
002051c0 RBBM_PERFCTR_SP[0x5]+0: 002051c0
|
||||
00800106 RBBM_PERFCTR_SP[0x5]+0x1: 00800106
|
||||
004011b8 RBBM_PERFCTR_SP[0x6]+0: 004011b8
|
||||
40400000 RBBM_PERFCTR_SP[0x6]+0x1: 40400000
|
||||
200031b8 RBBM_PERFCTR_SP[0x7]+0: 200031b8
|
||||
41040100 RBBM_PERFCTR_SP[0x7]+0x1: 41040100
|
||||
001011bc RBBM_PERFCTR_SP[0x8]+0: 001011bc
|
||||
00000000 RBBM_PERFCTR_SP[0x8]+0x1: 00000000
|
||||
204011bc RBBM_PERFCTR_SP[0x9]+0: 204011bc
|
||||
00000001 RBBM_PERFCTR_SP[0x9]+0x1: 00000001
|
||||
040011b8 RBBM_PERFCTR_SP[0xa]+0: 040011b8
|
||||
02000000 RBBM_PERFCTR_SP[0xa]+0x1: 02000000
|
||||
340012b8 RBBM_PERFCTR_SP[0xb]+0: 340012b8
|
||||
004000c0 RBBM_PERFCTR_SP[0xb]+0x1: 004000c0
|
||||
c00015b8 RBBM_PERFCTR_SP[0xc]+0: c00015b8
|
||||
00800040 RBBM_PERFCTR_SP[0xc]+0x1: 00800040
|
||||
003041b9 RBBM_PERFCTR_SP[0xd]+0: 003041b9
|
||||
00000000 RBBM_PERFCTR_SP[0xd]+0x1: 00000000
|
||||
000019bc RBBM_PERFCTR_SP[0xe]+0: 000019bc
|
||||
00080000 RBBM_PERFCTR_SP[0xe]+0x1: 00080000
|
||||
400051b9 RBBM_PERFCTR_SP[0xf]+0: 400051b9
|
||||
10000900 RBBM_PERFCTR_SP[0xf]+0x1: 10000900
|
||||
002011b8 RBBM_PERFCTR_SP[0x10]+0: 002011b8
|
||||
00000000 RBBM_PERFCTR_SP[0x10]+0x1: 00000000
|
||||
000092c0 RBBM_PERFCTR_SP[0x11]+0: 000092c0
|
||||
00000020 RBBM_PERFCTR_SP[0x11]+0x1: 00000020
|
||||
000012b8 RBBM_PERFCTR_SP[0x12]+0: 000012b8
|
||||
00900020 RBBM_PERFCTR_SP[0x12]+0x1: 00900020
|
||||
000811c0 RBBM_PERFCTR_SP[0x13]+0: 000811c0
|
||||
129001a0 RBBM_PERFCTR_SP[0x13]+0x1: 129001a0
|
||||
000011b8 RBBM_PERFCTR_SP[0x14]+0: 000011b8
|
||||
80000002 RBBM_PERFCTR_SP[0x14]+0x1: 80000002
|
||||
800011b8 RBBM_PERFCTR_SP[0x15]+0: 800011b8
|
||||
08000000 RBBM_PERFCTR_SP[0x15]+0x1: 08000000
|
||||
000011b8 RBBM_PERFCTR_SP[0x16]+0: 000011b8
|
||||
2000a000 RBBM_PERFCTR_SP[0x16]+0x1: 2000a000
|
||||
044011c0 RBBM_PERFCTR_SP[0x17]+0: 044011c0
|
||||
84090000 RBBM_PERFCTR_SP[0x17]+0x1: 84090000
|
||||
00104984 RBBM_PERFCTR_RB[0]+0: 00104984
|
||||
40000000 RBBM_PERFCTR_RB[0]+0x1: 40000000
|
||||
00040b04 RBBM_PERFCTR_RB[0x1]+0: 00040b04
|
||||
00200470 RBBM_PERFCTR_RB[0x1]+0x1: 00200470
|
||||
40000984 RBBM_PERFCTR_RB[0x2]+0: 40000984
|
||||
00820400 RBBM_PERFCTR_RB[0x2]+0x1: 00820400
|
||||
00000986 RBBM_PERFCTR_RB[0x3]+0: 00000986
|
||||
10000000 RBBM_PERFCTR_RB[0x3]+0x1: 10000000
|
||||
00001d84 RBBM_PERFCTR_RB[0x4]+0: 00001d84
|
||||
00000801 RBBM_PERFCTR_RB[0x4]+0x1: 00000801
|
||||
01040b04 RBBM_PERFCTR_RB[0x5]+0: 01040b04
|
||||
08002000 RBBM_PERFCTR_RB[0x5]+0x1: 08002000
|
||||
00000984 RBBM_PERFCTR_RB[0x6]+0: 00000984
|
||||
00000000 RBBM_PERFCTR_RB[0x6]+0x1: 00000000
|
||||
0000198c RBBM_PERFCTR_RB[0x7]+0: 0000198c
|
||||
0000000c RBBM_PERFCTR_RB[0x7]+0x1: 0000000c
|
||||
20000233 RBBM_PERFCTR_VSC[0]+0: 20000233
|
||||
20000000 RBBM_PERFCTR_VSC[0]+0x1: 20000000
|
||||
00000333 RBBM_PERFCTR_VSC[0x1]+0: 00000333
|
||||
30d00100 RBBM_PERFCTR_VSC[0x1]+0x1: 30d00100
|
||||
00000355 RBBM_PERFCTR_LRZ[0]+0: 00000355
|
||||
00080004 RBBM_PERFCTR_LRZ[0]+0x1: 00080004
|
||||
10000357 RBBM_PERFCTR_LRZ[0x1]+0: 10000357
|
||||
000005a0 RBBM_PERFCTR_LRZ[0x1]+0x1: 000005a0
|
||||
00000353 RBBM_PERFCTR_LRZ[0x2]+0: 00000353
|
||||
00000100 RBBM_PERFCTR_LRZ[0x2]+0x1: 00000100
|
||||
04004357 RBBM_PERFCTR_LRZ[0x3]+0: 04004357
|
||||
050c0000 RBBM_PERFCTR_LRZ[0x3]+0x1: 050c0000
|
||||
00000010 RBBM_PERFCTR_CMP[0]+0: 00000010
|
||||
08000000 RBBM_PERFCTR_CMP[0]+0x1: 08000000
|
||||
05000204 RBBM_PERFCTR_CMP[0x1]+0: 05000204
|
||||
40000220 RBBM_PERFCTR_CMP[0x1]+0x1: 40000220
|
||||
00000000 RBBM_PERFCTR_CMP[0x2]+0: 00000000
|
||||
00000400 RBBM_PERFCTR_CMP[0x2]+0x1: 00000400
|
||||
00200000 RBBM_PERFCTR_CMP[0x3]+0: 00200000
|
||||
11014000 RBBM_PERFCTR_CMP[0x3]+0x1: 11014000
|
||||
00000001 RBBM_PERFCTR_CNTL: 0x1
|
||||
00000000 RBBM_PERFCTR_LOAD_VALUE_LO: 0
|
||||
00000000 RBBM_PERFCTR_LOAD_VALUE_HI: 0
|
||||
00000000 RBBM_PERFCTR_RBBM_SEL_0: 0
|
||||
00000000 RBBM_PERFCTR_RBBM_SEL_1: 0
|
||||
00000000 RBBM_PERFCTR_RBBM_SEL_2: 0
|
||||
00000000 RBBM_PERFCTR_RBBM_SEL_3: 0
|
||||
00000000 RBBM_PERFCTR_RBBM_SEL[0]+0: 00000000
|
||||
00000000 RBBM_PERFCTR_RBBM_SEL[0x1]+0: 00000000
|
||||
00000000 RBBM_PERFCTR_RBBM_SEL[0x2]+0: 00000000
|
||||
00000000 RBBM_PERFCTR_RBBM_SEL[0x3]+0: 00000000
|
||||
002f7fff RBBM_PERFCTR_GPU_BUSY_MASKED: 0x2f7fff
|
||||
00000000 0x50f: 00000000
|
||||
00000000 0x511: 00000000
|
||||
|
|
@ -703,20 +703,20 @@ registers:
|
|||
010000c0 CP_ROQ_THRESHOLDS_2: { SDS_START = 0x300 | ROQ_SIZE = 0x400 }
|
||||
00000080 CP_MEM_POOL_SIZE: 0x80
|
||||
00000000 0x8c4: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL_0: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_1: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_2: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_3: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_4: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_5: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_6: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_7: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_8: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_9: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_10: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_11: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_12: 0
|
||||
00000000 CP_PERFCTR_CP_SEL_13: 0
|
||||
00000000 CP_PERFCTR_CP_SEL[0]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x1]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x2]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x3]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x4]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x5]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x6]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x7]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x8]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0x9]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0xa]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0xb]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0xc]+0: 00000000
|
||||
00000000 CP_PERFCTR_CP_SEL[0xd]+0: 00000000
|
||||
00000000 0x8f0: 00000000
|
||||
00000000 0x8f1: 00000000
|
||||
00000000 0x8f2: 00000000
|
||||
|
|
@ -1025,8 +1025,8 @@ registers:
|
|||
00000000 0xcd5: 00000000
|
||||
00000000 0xcd6: 00000000
|
||||
00000000 0xcd7: 00000000
|
||||
00000000 VSC_PERFCTR_VSC_SEL_0: 0
|
||||
00000000 VSC_PERFCTR_VSC_SEL_1: 0
|
||||
00000000 VSC_PERFCTR_VSC_SEL[0]+0: 00000000
|
||||
00000000 VSC_PERFCTR_VSC_SEL[0x1]+0: 00000000
|
||||
00000001 UCHE_ADDR_MODE_CNTL: ADDR_64B
|
||||
00400000 UCHE_MODE_CNTL: 0x400000
|
||||
00000000 0xe02: 00000000
|
||||
|
|
@ -1049,18 +1049,18 @@ registers:
|
|||
00000004 UCHE_CACHE_WAYS: 0x4
|
||||
00000804 UCHE_FILTER_CNTL: 0x804
|
||||
00000001 UCHE_CLIENT_PF: { PERFSEL = 0x1 }
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_0: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_1: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_2: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_3: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_4: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_5: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_6: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_7: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_8: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_9: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_10: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL_11: 0
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x1]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x2]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x3]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x4]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x5]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x6]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x7]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x8]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0x9]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0xa]+0: 00000000
|
||||
00000000 UCHE_PERFCTR_UCHE_SEL[0xb]+0: 00000000
|
||||
00000000 0xe28: 00000000
|
||||
00000000 0xe29: 00000000
|
||||
00000000 0xe2a: 00000000
|
||||
|
|
@ -1072,18 +1072,18 @@ registers:
|
|||
00000000 0xe39: 00000000
|
||||
00000000 GRAS_UNKNOWN_8600: 0
|
||||
00000001 GRAS_ADDR_MODE_CNTL: ADDR_64B
|
||||
00000000 GRAS_PERFCTR_TSE_SEL_0: 0
|
||||
00000000 GRAS_PERFCTR_TSE_SEL_1: 0
|
||||
00000000 GRAS_PERFCTR_TSE_SEL_2: 0
|
||||
00000000 GRAS_PERFCTR_TSE_SEL_3: 0
|
||||
00000000 GRAS_PERFCTR_RAS_SEL_0: 0
|
||||
00000000 GRAS_PERFCTR_RAS_SEL_1: 0
|
||||
00000000 GRAS_PERFCTR_RAS_SEL_2: 0
|
||||
00000000 GRAS_PERFCTR_RAS_SEL_3: 0
|
||||
00000000 GRAS_PERFCTR_LRZ_SEL_0: 0
|
||||
00000000 GRAS_PERFCTR_LRZ_SEL_1: 0
|
||||
00000000 GRAS_PERFCTR_LRZ_SEL_2: 0
|
||||
00000000 GRAS_PERFCTR_LRZ_SEL_3: 0
|
||||
00000000 GRAS_PERFCTR_TSE_SEL[0]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_TSE_SEL[0x1]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_TSE_SEL[0x2]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_TSE_SEL[0x3]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_RAS_SEL[0]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_RAS_SEL[0x1]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_RAS_SEL[0x2]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_RAS_SEL[0x3]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_LRZ_SEL[0]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_LRZ_SEL[0x1]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_LRZ_SEL[0x2]+0: 00000000
|
||||
00000000 GRAS_PERFCTR_LRZ_SEL[0x3]+0: 00000000
|
||||
00000000 0x8620: 00000000
|
||||
00000000 0x8628: 00000000
|
||||
00000000 0x8629: 00000000
|
||||
|
|
@ -1101,7 +1101,7 @@ registers:
|
|||
00000001 VPC_ADDR_MODE_CNTL: ADDR_64B
|
||||
00000000 VPC_UNKNOWN_9602: FALSE
|
||||
00000000 VPC_UNKNOWN_9603: 0
|
||||
00000000 VPC_PERFCTR_VPC_SEL_0: 0
|
||||
00000000 VPC_PERFCTR_VPC_SEL[0]+0: 00000000
|
||||
00000000 0x9624: 00000000
|
||||
00000000 0x9625: 00000000
|
||||
00000000 0x9626: 00000000
|
||||
|
|
@ -1150,7 +1150,7 @@ registers:
|
|||
00000000 0x9e23: 00000000
|
||||
00000000 0x9e30: 00000000
|
||||
00000000 0x9e31: 00000000
|
||||
00000000 PC_PERFCTR_PC_SEL_0: 0
|
||||
00000000 PC_PERFCTR_PC_SEL[0]+0: 00000000
|
||||
00000000 0x9e70: 00000000
|
||||
00000000 0x9e71: 00000000
|
||||
00000000 PC_UNKNOWN_9E72: 0
|
||||
|
|
@ -1544,32 +1544,32 @@ registers:
|
|||
00000001 VFD_ADDR_MODE_CNTL: ADDR_64B
|
||||
00000000 0xa603: 00000000
|
||||
00000000 0xa60a: 00000000
|
||||
00000000 VFD_PERFCTR_VFD_SEL_0: 0
|
||||
00000000 VFD_PERFCTR_VFD_SEL_1: 0
|
||||
00000000 VFD_PERFCTR_VFD_SEL_2: 0
|
||||
00000000 VFD_PERFCTR_VFD_SEL_3: 0
|
||||
00000000 VFD_PERFCTR_VFD_SEL_4: 0
|
||||
00000000 VFD_PERFCTR_VFD_SEL_5: 0
|
||||
00000000 VFD_PERFCTR_VFD_SEL_6: 0
|
||||
00000000 VFD_PERFCTR_VFD_SEL_7: 0
|
||||
00000000 VFD_PERFCTR_VFD_SEL[0]+0: 00000000
|
||||
00000000 VFD_PERFCTR_VFD_SEL[0x1]+0: 00000000
|
||||
00000000 VFD_PERFCTR_VFD_SEL[0x2]+0: 00000000
|
||||
00000000 VFD_PERFCTR_VFD_SEL[0x3]+0: 00000000
|
||||
00000000 VFD_PERFCTR_VFD_SEL[0x4]+0: 00000000
|
||||
00000000 VFD_PERFCTR_VFD_SEL[0x5]+0: 00000000
|
||||
00000000 VFD_PERFCTR_VFD_SEL[0x6]+0: 00000000
|
||||
00000000 VFD_PERFCTR_VFD_SEL[0x7]+0: 00000000
|
||||
00000000 0xa630: 00000000
|
||||
00100000 RB_UNKNOWN_8E04: 0x100000
|
||||
00000001 RB_ADDR_MODE_CNTL: ADDR_64B
|
||||
00000000 RB_CCU_CNTL: { OFFSET = 0 }
|
||||
00000004 RB_NC_MODE_CNTL: { LOWER_BIT = 2 | UPPER_BIT = 0 }
|
||||
00000000 RB_PERFCTR_RB_SEL_0: 0
|
||||
00000000 RB_PERFCTR_RB_SEL_1: 0
|
||||
00000000 RB_PERFCTR_RB_SEL_2: 0
|
||||
00000000 RB_PERFCTR_RB_SEL_3: 0
|
||||
00000000 RB_PERFCTR_RB_SEL_4: 0
|
||||
00000000 RB_PERFCTR_RB_SEL_5: 0
|
||||
00000000 RB_PERFCTR_RB_SEL_6: 0
|
||||
00000000 RB_PERFCTR_RB_SEL_7: 0
|
||||
00000000 RB_PERFCTR_CCU_SEL_0: 0
|
||||
00000000 RB_PERFCTR_CCU_SEL_1: 0
|
||||
00000000 RB_PERFCTR_CCU_SEL_2: 0
|
||||
00000000 RB_PERFCTR_CCU_SEL_3: 0
|
||||
00000000 RB_PERFCTR_CCU_SEL_4: 0
|
||||
00000000 RB_PERFCTR_RB_SEL[0]+0: 00000000
|
||||
00000000 RB_PERFCTR_RB_SEL[0x1]+0: 00000000
|
||||
00000000 RB_PERFCTR_RB_SEL[0x2]+0: 00000000
|
||||
00000000 RB_PERFCTR_RB_SEL[0x3]+0: 00000000
|
||||
00000000 RB_PERFCTR_RB_SEL[0x4]+0: 00000000
|
||||
00000000 RB_PERFCTR_RB_SEL[0x5]+0: 00000000
|
||||
00000000 RB_PERFCTR_RB_SEL[0x6]+0: 00000000
|
||||
00000000 RB_PERFCTR_RB_SEL[0x7]+0: 00000000
|
||||
00000000 RB_PERFCTR_CCU_SEL[0]+0: 00000000
|
||||
00000000 RB_PERFCTR_CCU_SEL[0x1]+0: 00000000
|
||||
00000000 RB_PERFCTR_CCU_SEL[0x2]+0: 00000000
|
||||
00000000 RB_PERFCTR_CCU_SEL[0x3]+0: 00000000
|
||||
00000000 RB_PERFCTR_CCU_SEL[0x4]+0: 00000000
|
||||
00000000 0x8e20: 00000000
|
||||
00000000 0x8e21: 00000000
|
||||
00000000 0x8e22: 00000000
|
||||
|
|
@ -1577,10 +1577,10 @@ registers:
|
|||
00000000 0x8e24: 00000000
|
||||
00000000 0x8e25: 00000000
|
||||
00000000 RB_UNKNOWN_8E28: 0
|
||||
00000000 RB_PERFCTR_CMP_SEL_0: 0
|
||||
00000000 RB_PERFCTR_CMP_SEL_1: 0
|
||||
00000000 RB_PERFCTR_CMP_SEL_2: 0
|
||||
00000000 RB_PERFCTR_CMP_SEL_3: 0
|
||||
00000000 RB_PERFCTR_CMP_SEL[0]+0: 00000000
|
||||
00000000 RB_PERFCTR_CMP_SEL[0x1]+0: 00000000
|
||||
00000000 RB_PERFCTR_CMP_SEL[0x2]+0: 00000000
|
||||
00000000 RB_PERFCTR_CMP_SEL[0x3]+0: 00000000
|
||||
00000000 RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE: FALSE
|
||||
0006d000 RB_UNKNOWN_8E51: 0x6d000
|
||||
00000000 0x8e52: 00000000
|
||||
|
|
@ -1617,12 +1617,12 @@ registers:
|
|||
00000000 HLSQ_ADDR_MODE_CNTL: ADDR_32B
|
||||
deadbeef 0xbe08: deadbeef
|
||||
deadbeef 0xbe09: deadbeef
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL_0: 0
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL_1: 0
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL_2: 0
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL_3: 0
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL_4: 0
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL_5: 0
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL[0]+0: 00000000
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x1]+0: 00000000
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x2]+0: 00000000
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x3]+0: 00000000
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x4]+0: 00000000
|
||||
00000000 HLSQ_PERFCTR_HLSQ_SEL[0x5]+0: 00000000
|
||||
00000000 0xbe20: 00000000
|
||||
00000000 0xbe21: 00000000
|
||||
00000000 0xbe22: 00000000
|
||||
|
|
@ -1633,31 +1633,31 @@ registers:
|
|||
deadbeef SP_UNKNOWN_AE03: 0xdeadbeef
|
||||
00000004 SP_UNKNOWN_AE04: 0x4
|
||||
deadbeef 0xae0c: deadbeef
|
||||
deadbeef SP_UNKNOWN_AE0F: 0xdeadbeef
|
||||
00000000 SP_PERFCTR_SP_SEL_0: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_1: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_2: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_3: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_4: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_5: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_6: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_7: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_8: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_9: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_10: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_11: 0
|
||||
deadbeef SP_PERFCTR_SP_SEL_12: 0xdeadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL_13: 0xdeadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL_14: 0xdeadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL_15: 0xdeadbeef
|
||||
00000000 SP_PERFCTR_SP_SEL_16: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_17: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_18: 0
|
||||
00000000 SP_PERFCTR_SP_SEL_19: 0
|
||||
deadbeef SP_PERFCTR_SP_SEL_20: 0xdeadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL_21: 0xdeadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL_22: 0xdeadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL_23: 0xdeadbeef
|
||||
deadbeef SP_PERFCTR_ENABLE: { VS | HS | DS | GS | CS | 0xdeadbec0 }
|
||||
00000000 SP_PERFCTR_SP_SEL[0]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x1]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x2]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x3]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x4]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x5]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x6]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x7]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x8]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x9]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0xa]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0xb]+0: 00000000
|
||||
deadbeef SP_PERFCTR_SP_SEL[0xc]+0: deadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL[0xd]+0: deadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL[0xe]+0: deadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL[0xf]+0: deadbeef
|
||||
00000000 SP_PERFCTR_SP_SEL[0x10]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x11]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x12]+0: 00000000
|
||||
00000000 SP_PERFCTR_SP_SEL[0x13]+0: 00000000
|
||||
deadbeef SP_PERFCTR_SP_SEL[0x14]+0: deadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL[0x15]+0: deadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL[0x16]+0: deadbeef
|
||||
deadbeef SP_PERFCTR_SP_SEL[0x17]+0: deadbeef
|
||||
deadbeef 0xae28: deadbeef
|
||||
deadbeef 0xae29: deadbeef
|
||||
deadbeef 0xae2a: deadbeef
|
||||
|
|
@ -1679,18 +1679,18 @@ registers:
|
|||
00000001 TPL1_ADDR_MODE_CNTL: ADDR_64B
|
||||
00000004 TPL1_NC_MODE_CNTL: 0x4
|
||||
00000000 SP_UNKNOWN_B605: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_0: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_1: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_2: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_3: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_4: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_5: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_6: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_7: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_8: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_9: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_10: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL_11: 0
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x1]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x2]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x3]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x4]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x5]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x6]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x7]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x8]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0x9]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0xa]+0: 00000000
|
||||
00000000 TPL1_PERFCTR_TP_SEL[0xb]+0: 00000000
|
||||
00000000 0xb620: 00000000
|
||||
00000000 0xb621: 00000000
|
||||
00000000 0xb622: 00000000
|
||||
|
|
|
|||
|
|
@ -24,8 +24,8 @@ t4 write SP_UNKNOWN_AE04 (ae04)
|
|||
t4 write SP_UNKNOWN_AE00 (ae00)
|
||||
SP_UNKNOWN_AE00: 0
|
||||
000000000105802c: 0000: 40ae0001 00000000
|
||||
t4 write SP_UNKNOWN_AE0F (ae0f)
|
||||
SP_UNKNOWN_AE0F: 0x3f
|
||||
t4 write SP_PERFCTR_ENABLE (ae0f)
|
||||
SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
|
||||
0000000001058034: 0000: 40ae0f01 0000003f
|
||||
t4 write SP_UNKNOWN_B605 (b605)
|
||||
SP_UNKNOWN_B605: 0x44
|
||||
|
|
@ -351,7 +351,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
|
|||
+ 00000000 SP_UNKNOWN_AE00: 0
|
||||
!+ 00000410 SP_UNKNOWN_AE03: 0x410
|
||||
!+ 00000008 SP_UNKNOWN_AE04: 0x8
|
||||
!+ 0000003f SP_UNKNOWN_AE0F: 0x3f
|
||||
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
|
||||
!+ 01011000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
|
||||
+ 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
|
||||
+ 00000000 SP_UNKNOWN_B182: 0
|
||||
|
|
|
|||
|
|
@ -21,8 +21,8 @@ t4 write SP_UNKNOWN_AE04 (ae04)
|
|||
t4 write SP_UNKNOWN_AE00 (ae00)
|
||||
SP_UNKNOWN_AE00: 0
|
||||
0000000001d91024: 0000: 40ae0001 00000000
|
||||
t4 write SP_UNKNOWN_AE0F (ae0f)
|
||||
SP_UNKNOWN_AE0F: 0x3f
|
||||
t4 write SP_PERFCTR_ENABLE (ae0f)
|
||||
SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
|
||||
0000000001d9102c: 0000: 40ae0f01 0000003f
|
||||
t4 write SP_UNKNOWN_B605 (b605)
|
||||
SP_UNKNOWN_B605: 0x44
|
||||
|
|
@ -1125,7 +1125,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
|
|||
+ 00000000 SP_UNKNOWN_AE00: 0
|
||||
!+ 00001430 SP_UNKNOWN_AE03: 0x1430
|
||||
!+ 00000008 SP_UNKNOWN_AE04: 0x8
|
||||
!+ 0000003f SP_UNKNOWN_AE0F: 0x3f
|
||||
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
|
||||
+ 00000000 SP_UNKNOWN_B182: 0
|
||||
+ 00000000 SP_UNKNOWN_B183: 0
|
||||
+ 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
|
||||
|
|
|
|||
|
|
@ -38,20 +38,20 @@
|
|||
|
||||
static const struct fd_perfcntr_counter cp_counters[] = {
|
||||
//RESERVED: for kernel
|
||||
// COUNTER(CP_PERFCTR_CP_SEL_0, RBBM_PERFCTR_CP_0_LO, RBBM_PERFCTR_CP_0_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_1, RBBM_PERFCTR_CP_1_LO, RBBM_PERFCTR_CP_1_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_2, RBBM_PERFCTR_CP_2_LO, RBBM_PERFCTR_CP_2_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_3, RBBM_PERFCTR_CP_3_LO, RBBM_PERFCTR_CP_3_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_4, RBBM_PERFCTR_CP_4_LO, RBBM_PERFCTR_CP_4_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_5, RBBM_PERFCTR_CP_5_LO, RBBM_PERFCTR_CP_5_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_6, RBBM_PERFCTR_CP_6_LO, RBBM_PERFCTR_CP_6_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_7, RBBM_PERFCTR_CP_7_LO, RBBM_PERFCTR_CP_7_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_8, RBBM_PERFCTR_CP_8_LO, RBBM_PERFCTR_CP_8_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_9, RBBM_PERFCTR_CP_9_LO, RBBM_PERFCTR_CP_9_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_10, RBBM_PERFCTR_CP_10_LO, RBBM_PERFCTR_CP_10_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_11, RBBM_PERFCTR_CP_11_LO, RBBM_PERFCTR_CP_11_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_12, RBBM_PERFCTR_CP_12_LO, RBBM_PERFCTR_CP_12_HI),
|
||||
COUNTER(CP_PERFCTR_CP_SEL_13, RBBM_PERFCTR_CP_13_LO, RBBM_PERFCTR_CP_13_HI),
|
||||
// COUNTER(CP_PERFCTR_CP_SEL(0), RBBM_PERFCTR_CP(0), RBBM_PERFCTR_CP(0)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(1), RBBM_PERFCTR_CP(1), RBBM_PERFCTR_CP(1)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(2), RBBM_PERFCTR_CP(2), RBBM_PERFCTR_CP(2)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(3), RBBM_PERFCTR_CP(3), RBBM_PERFCTR_CP(3)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(4), RBBM_PERFCTR_CP(4), RBBM_PERFCTR_CP(4)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(5), RBBM_PERFCTR_CP(5), RBBM_PERFCTR_CP(5)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(6), RBBM_PERFCTR_CP(6), RBBM_PERFCTR_CP(6)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(7), RBBM_PERFCTR_CP(7), RBBM_PERFCTR_CP(7)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(8), RBBM_PERFCTR_CP(8), RBBM_PERFCTR_CP(8)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(9), RBBM_PERFCTR_CP(9), RBBM_PERFCTR_CP(9)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(10), RBBM_PERFCTR_CP(10), RBBM_PERFCTR_CP(10)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(11), RBBM_PERFCTR_CP(11), RBBM_PERFCTR_CP(11)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(12), RBBM_PERFCTR_CP(12), RBBM_PERFCTR_CP(12)+1),
|
||||
COUNTER(CP_PERFCTR_CP_SEL(13), RBBM_PERFCTR_CP(13), RBBM_PERFCTR_CP(13)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable cp_countables[] = {
|
||||
|
|
@ -108,11 +108,11 @@ static const struct fd_perfcntr_countable cp_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter ccu_counters[] = {
|
||||
COUNTER(RB_PERFCTR_CCU_SEL_0, RBBM_PERFCTR_CCU_0_LO, RBBM_PERFCTR_CCU_0_HI),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL_1, RBBM_PERFCTR_CCU_1_LO, RBBM_PERFCTR_CCU_1_HI),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL_2, RBBM_PERFCTR_CCU_2_LO, RBBM_PERFCTR_CCU_2_HI),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL_3, RBBM_PERFCTR_CCU_3_LO, RBBM_PERFCTR_CCU_3_HI),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL_4, RBBM_PERFCTR_CCU_4_LO, RBBM_PERFCTR_CCU_4_HI),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL(0), RBBM_PERFCTR_CCU(0), RBBM_PERFCTR_CCU(0)+1),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL(1), RBBM_PERFCTR_CCU(1), RBBM_PERFCTR_CCU(1)+1),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL(2), RBBM_PERFCTR_CCU(2), RBBM_PERFCTR_CCU(2)+1),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL(3), RBBM_PERFCTR_CCU(3), RBBM_PERFCTR_CCU(3)+1),
|
||||
COUNTER(RB_PERFCTR_CCU_SEL(4), RBBM_PERFCTR_CCU(4), RBBM_PERFCTR_CCU(4)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable ccu_countables[] = {
|
||||
|
|
@ -148,10 +148,10 @@ static const struct fd_perfcntr_countable ccu_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter tse_counters[] = {
|
||||
COUNTER(GRAS_PERFCTR_TSE_SEL_0, RBBM_PERFCTR_TSE_0_LO, RBBM_PERFCTR_TSE_0_HI),
|
||||
COUNTER(GRAS_PERFCTR_TSE_SEL_1, RBBM_PERFCTR_TSE_1_LO, RBBM_PERFCTR_TSE_1_HI),
|
||||
COUNTER(GRAS_PERFCTR_TSE_SEL_2, RBBM_PERFCTR_TSE_2_LO, RBBM_PERFCTR_TSE_2_HI),
|
||||
COUNTER(GRAS_PERFCTR_TSE_SEL_3, RBBM_PERFCTR_TSE_3_LO, RBBM_PERFCTR_TSE_3_HI),
|
||||
COUNTER(GRAS_PERFCTR_TSE_SEL(0), RBBM_PERFCTR_TSE(0), RBBM_PERFCTR_TSE(0)+1),
|
||||
COUNTER(GRAS_PERFCTR_TSE_SEL(1), RBBM_PERFCTR_TSE(1), RBBM_PERFCTR_TSE(1)+1),
|
||||
COUNTER(GRAS_PERFCTR_TSE_SEL(2), RBBM_PERFCTR_TSE(2), RBBM_PERFCTR_TSE(2)+1),
|
||||
COUNTER(GRAS_PERFCTR_TSE_SEL(3), RBBM_PERFCTR_TSE(3), RBBM_PERFCTR_TSE(3)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable tse_countables[] = {
|
||||
|
|
@ -178,10 +178,10 @@ static const struct fd_perfcntr_countable tse_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter ras_counters[] = {
|
||||
COUNTER(GRAS_PERFCTR_RAS_SEL_0, RBBM_PERFCTR_RAS_0_LO, RBBM_PERFCTR_RAS_0_HI),
|
||||
COUNTER(GRAS_PERFCTR_RAS_SEL_1, RBBM_PERFCTR_RAS_1_LO, RBBM_PERFCTR_RAS_1_HI),
|
||||
COUNTER(GRAS_PERFCTR_RAS_SEL_2, RBBM_PERFCTR_RAS_2_LO, RBBM_PERFCTR_RAS_2_HI),
|
||||
COUNTER(GRAS_PERFCTR_RAS_SEL_3, RBBM_PERFCTR_RAS_3_LO, RBBM_PERFCTR_RAS_3_HI),
|
||||
COUNTER(GRAS_PERFCTR_RAS_SEL(0), RBBM_PERFCTR_RAS(0), RBBM_PERFCTR_RAS(0)+1),
|
||||
COUNTER(GRAS_PERFCTR_RAS_SEL(1), RBBM_PERFCTR_RAS(1), RBBM_PERFCTR_RAS(1)+1),
|
||||
COUNTER(GRAS_PERFCTR_RAS_SEL(2), RBBM_PERFCTR_RAS(2), RBBM_PERFCTR_RAS(2)+1),
|
||||
COUNTER(GRAS_PERFCTR_RAS_SEL(3), RBBM_PERFCTR_RAS(3), RBBM_PERFCTR_RAS(3)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable ras_countables[] = {
|
||||
|
|
@ -201,10 +201,10 @@ static const struct fd_perfcntr_countable ras_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter lrz_counters[] = {
|
||||
COUNTER(GRAS_PERFCTR_LRZ_SEL_0, RBBM_PERFCTR_LRZ_0_LO, RBBM_PERFCTR_LRZ_0_HI),
|
||||
COUNTER(GRAS_PERFCTR_LRZ_SEL_1, RBBM_PERFCTR_LRZ_1_LO, RBBM_PERFCTR_LRZ_1_HI),
|
||||
COUNTER(GRAS_PERFCTR_LRZ_SEL_2, RBBM_PERFCTR_LRZ_2_LO, RBBM_PERFCTR_LRZ_2_HI),
|
||||
COUNTER(GRAS_PERFCTR_LRZ_SEL_3, RBBM_PERFCTR_LRZ_3_LO, RBBM_PERFCTR_LRZ_3_HI),
|
||||
COUNTER(GRAS_PERFCTR_LRZ_SEL(0), RBBM_PERFCTR_LRZ(0), RBBM_PERFCTR_LRZ(0)+1),
|
||||
COUNTER(GRAS_PERFCTR_LRZ_SEL(1), RBBM_PERFCTR_LRZ(1), RBBM_PERFCTR_LRZ(1)+1),
|
||||
COUNTER(GRAS_PERFCTR_LRZ_SEL(2), RBBM_PERFCTR_LRZ(2), RBBM_PERFCTR_LRZ(2)+1),
|
||||
COUNTER(GRAS_PERFCTR_LRZ_SEL(3), RBBM_PERFCTR_LRZ(3), RBBM_PERFCTR_LRZ(3)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable lrz_countables[] = {
|
||||
|
|
@ -239,15 +239,15 @@ static const struct fd_perfcntr_countable lrz_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter hlsq_counters[] = {
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL_0, RBBM_PERFCTR_HLSQ_0_LO, RBBM_PERFCTR_HLSQ_0_HI),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL_1, RBBM_PERFCTR_HLSQ_1_LO, RBBM_PERFCTR_HLSQ_1_HI),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL_2, RBBM_PERFCTR_HLSQ_2_LO, RBBM_PERFCTR_HLSQ_2_HI),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL_3, RBBM_PERFCTR_HLSQ_3_LO, RBBM_PERFCTR_HLSQ_3_HI),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL_4, RBBM_PERFCTR_HLSQ_4_LO, RBBM_PERFCTR_HLSQ_4_HI),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL_5, RBBM_PERFCTR_HLSQ_5_LO, RBBM_PERFCTR_HLSQ_5_HI),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL(0), RBBM_PERFCTR_HLSQ(0), RBBM_PERFCTR_HLSQ(0)+1),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL(1), RBBM_PERFCTR_HLSQ(1), RBBM_PERFCTR_HLSQ(1)+1),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL(2), RBBM_PERFCTR_HLSQ(2), RBBM_PERFCTR_HLSQ(2)+1),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL(3), RBBM_PERFCTR_HLSQ(3), RBBM_PERFCTR_HLSQ(3)+1),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL(4), RBBM_PERFCTR_HLSQ(4), RBBM_PERFCTR_HLSQ(4)+1),
|
||||
COUNTER(HLSQ_PERFCTR_HLSQ_SEL(5), RBBM_PERFCTR_HLSQ(5), RBBM_PERFCTR_HLSQ(5)+1),
|
||||
// TODO did we loose some HLSQ counters or are they just missing from xml
|
||||
// COUNTER(HLSQ_PERFCTR_HLSQ_SEL_6, RBBM_PERFCTR_HLSQ_6_LO, RBBM_PERFCTR_HLSQ_6_HI),
|
||||
// COUNTER(HLSQ_PERFCTR_HLSQ_SEL_7, RBBM_PERFCTR_HLSQ_7_LO, RBBM_PERFCTR_HLSQ_7_HI),
|
||||
// COUNTER(HLSQ_PERFCTR_HLSQ_SEL(6), RBBM_PERFCTR_HLSQ(6), RBBM_PERFCTR_HLSQ(6)+1),
|
||||
// COUNTER(HLSQ_PERFCTR_HLSQ_SEL(7), RBBM_PERFCTR_HLSQ(7), RBBM_PERFCTR_HLSQ(7)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable hlsq_countables[] = {
|
||||
|
|
@ -275,14 +275,14 @@ static const struct fd_perfcntr_countable hlsq_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter pc_counters[] = {
|
||||
COUNTER(PC_PERFCTR_PC_SEL_0, RBBM_PERFCTR_PC_0_LO, RBBM_PERFCTR_PC_0_HI),
|
||||
COUNTER(PC_PERFCTR_PC_SEL_1, RBBM_PERFCTR_PC_1_LO, RBBM_PERFCTR_PC_1_HI),
|
||||
COUNTER(PC_PERFCTR_PC_SEL_2, RBBM_PERFCTR_PC_2_LO, RBBM_PERFCTR_PC_2_HI),
|
||||
COUNTER(PC_PERFCTR_PC_SEL_3, RBBM_PERFCTR_PC_3_LO, RBBM_PERFCTR_PC_3_HI),
|
||||
COUNTER(PC_PERFCTR_PC_SEL_4, RBBM_PERFCTR_PC_4_LO, RBBM_PERFCTR_PC_4_HI),
|
||||
COUNTER(PC_PERFCTR_PC_SEL_5, RBBM_PERFCTR_PC_5_LO, RBBM_PERFCTR_PC_5_HI),
|
||||
COUNTER(PC_PERFCTR_PC_SEL_6, RBBM_PERFCTR_PC_6_LO, RBBM_PERFCTR_PC_6_HI),
|
||||
COUNTER(PC_PERFCTR_PC_SEL_7, RBBM_PERFCTR_PC_7_LO, RBBM_PERFCTR_PC_7_HI),
|
||||
COUNTER(PC_PERFCTR_PC_SEL(0), RBBM_PERFCTR_PC(0), RBBM_PERFCTR_PC(0)+1),
|
||||
COUNTER(PC_PERFCTR_PC_SEL(1), RBBM_PERFCTR_PC(1), RBBM_PERFCTR_PC(1)+1),
|
||||
COUNTER(PC_PERFCTR_PC_SEL(2), RBBM_PERFCTR_PC(2), RBBM_PERFCTR_PC(2)+1),
|
||||
COUNTER(PC_PERFCTR_PC_SEL(3), RBBM_PERFCTR_PC(3), RBBM_PERFCTR_PC(3)+1),
|
||||
COUNTER(PC_PERFCTR_PC_SEL(4), RBBM_PERFCTR_PC(4), RBBM_PERFCTR_PC(4)+1),
|
||||
COUNTER(PC_PERFCTR_PC_SEL(5), RBBM_PERFCTR_PC(5), RBBM_PERFCTR_PC(5)+1),
|
||||
COUNTER(PC_PERFCTR_PC_SEL(6), RBBM_PERFCTR_PC(6), RBBM_PERFCTR_PC(6)+1),
|
||||
COUNTER(PC_PERFCTR_PC_SEL(7), RBBM_PERFCTR_PC(7), RBBM_PERFCTR_PC(7)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable pc_countables[] = {
|
||||
|
|
@ -331,14 +331,14 @@ static const struct fd_perfcntr_countable pc_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter rb_counters[] = {
|
||||
COUNTER(RB_PERFCTR_RB_SEL_0, RBBM_PERFCTR_RB_0_LO, RBBM_PERFCTR_RB_0_HI),
|
||||
COUNTER(RB_PERFCTR_RB_SEL_1, RBBM_PERFCTR_RB_1_LO, RBBM_PERFCTR_RB_1_HI),
|
||||
COUNTER(RB_PERFCTR_RB_SEL_2, RBBM_PERFCTR_RB_2_LO, RBBM_PERFCTR_RB_2_HI),
|
||||
COUNTER(RB_PERFCTR_RB_SEL_3, RBBM_PERFCTR_RB_3_LO, RBBM_PERFCTR_RB_3_HI),
|
||||
COUNTER(RB_PERFCTR_RB_SEL_4, RBBM_PERFCTR_RB_4_LO, RBBM_PERFCTR_RB_4_HI),
|
||||
COUNTER(RB_PERFCTR_RB_SEL_5, RBBM_PERFCTR_RB_5_LO, RBBM_PERFCTR_RB_5_HI),
|
||||
COUNTER(RB_PERFCTR_RB_SEL_6, RBBM_PERFCTR_RB_6_LO, RBBM_PERFCTR_RB_6_HI),
|
||||
COUNTER(RB_PERFCTR_RB_SEL_7, RBBM_PERFCTR_RB_7_LO, RBBM_PERFCTR_RB_7_HI),
|
||||
COUNTER(RB_PERFCTR_RB_SEL(0), RBBM_PERFCTR_RB(0), RBBM_PERFCTR_RB(0)+1),
|
||||
COUNTER(RB_PERFCTR_RB_SEL(1), RBBM_PERFCTR_RB(1), RBBM_PERFCTR_RB(1)+1),
|
||||
COUNTER(RB_PERFCTR_RB_SEL(2), RBBM_PERFCTR_RB(2), RBBM_PERFCTR_RB(2)+1),
|
||||
COUNTER(RB_PERFCTR_RB_SEL(3), RBBM_PERFCTR_RB(3), RBBM_PERFCTR_RB(3)+1),
|
||||
COUNTER(RB_PERFCTR_RB_SEL(4), RBBM_PERFCTR_RB(4), RBBM_PERFCTR_RB(4)+1),
|
||||
COUNTER(RB_PERFCTR_RB_SEL(5), RBBM_PERFCTR_RB(5), RBBM_PERFCTR_RB(5)+1),
|
||||
COUNTER(RB_PERFCTR_RB_SEL(6), RBBM_PERFCTR_RB(6), RBBM_PERFCTR_RB(6)+1),
|
||||
COUNTER(RB_PERFCTR_RB_SEL(7), RBBM_PERFCTR_RB(7), RBBM_PERFCTR_RB(7)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable rb_countables[] = {
|
||||
|
|
@ -394,10 +394,10 @@ static const struct fd_perfcntr_countable rb_countables[] = {
|
|||
|
||||
UNUSED static const struct fd_perfcntr_counter rbbm_counters[] = {
|
||||
//RESERVED: for kernel
|
||||
// COUNTER(RBBM_PERFCTR_RBBM_SEL_0, RBBM_PERFCTR_RBBM_0_LO, RBBM_PERFCTR_RBBM_0_HI),
|
||||
COUNTER(RBBM_PERFCTR_RBBM_SEL_1, RBBM_PERFCTR_RBBM_1_LO, RBBM_PERFCTR_RBBM_1_HI),
|
||||
COUNTER(RBBM_PERFCTR_RBBM_SEL_2, RBBM_PERFCTR_RBBM_2_LO, RBBM_PERFCTR_RBBM_2_HI),
|
||||
COUNTER(RBBM_PERFCTR_RBBM_SEL_3, RBBM_PERFCTR_RBBM_3_LO, RBBM_PERFCTR_RBBM_3_HI),
|
||||
// COUNTER(RBBM_PERFCTR_RBBM_SEL(0), RBBM_PERFCTR_RBBM(0), RBBM_PERFCTR_RBBM(0)+1),
|
||||
COUNTER(RBBM_PERFCTR_RBBM_SEL(1), RBBM_PERFCTR_RBBM(1), RBBM_PERFCTR_RBBM(1)+1),
|
||||
COUNTER(RBBM_PERFCTR_RBBM_SEL(2), RBBM_PERFCTR_RBBM(2), RBBM_PERFCTR_RBBM(2)+1),
|
||||
COUNTER(RBBM_PERFCTR_RBBM_SEL(3), RBBM_PERFCTR_RBBM(3), RBBM_PERFCTR_RBBM(3)+1),
|
||||
};
|
||||
|
||||
UNUSED static const struct fd_perfcntr_countable rbbm_countables[] = {
|
||||
|
|
@ -419,30 +419,30 @@ UNUSED static const struct fd_perfcntr_countable rbbm_countables[] = {
|
|||
|
||||
static const struct fd_perfcntr_counter sp_counters[] = {
|
||||
//RESERVED: for kernel
|
||||
// COUNTER(SP_PERFCTR_SP_SEL_0, RBBM_PERFCTR_SP_0_LO, RBBM_PERFCTR_SP_0_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_1, RBBM_PERFCTR_SP_1_LO, RBBM_PERFCTR_SP_1_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_2, RBBM_PERFCTR_SP_2_LO, RBBM_PERFCTR_SP_2_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_3, RBBM_PERFCTR_SP_3_LO, RBBM_PERFCTR_SP_3_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_4, RBBM_PERFCTR_SP_4_LO, RBBM_PERFCTR_SP_4_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_5, RBBM_PERFCTR_SP_5_LO, RBBM_PERFCTR_SP_5_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_6, RBBM_PERFCTR_SP_6_LO, RBBM_PERFCTR_SP_6_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_7, RBBM_PERFCTR_SP_7_LO, RBBM_PERFCTR_SP_7_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_8, RBBM_PERFCTR_SP_8_LO, RBBM_PERFCTR_SP_8_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_9, RBBM_PERFCTR_SP_9_LO, RBBM_PERFCTR_SP_9_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_10, RBBM_PERFCTR_SP_10_LO, RBBM_PERFCTR_SP_10_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_11, RBBM_PERFCTR_SP_11_LO, RBBM_PERFCTR_SP_11_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_12, RBBM_PERFCTR_SP_12_LO, RBBM_PERFCTR_SP_12_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_13, RBBM_PERFCTR_SP_13_LO, RBBM_PERFCTR_SP_13_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_14, RBBM_PERFCTR_SP_14_LO, RBBM_PERFCTR_SP_14_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_15, RBBM_PERFCTR_SP_15_LO, RBBM_PERFCTR_SP_15_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_16, RBBM_PERFCTR_SP_16_LO, RBBM_PERFCTR_SP_16_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_17, RBBM_PERFCTR_SP_17_LO, RBBM_PERFCTR_SP_17_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_18, RBBM_PERFCTR_SP_18_LO, RBBM_PERFCTR_SP_18_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_19, RBBM_PERFCTR_SP_19_LO, RBBM_PERFCTR_SP_19_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_20, RBBM_PERFCTR_SP_20_LO, RBBM_PERFCTR_SP_20_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_21, RBBM_PERFCTR_SP_21_LO, RBBM_PERFCTR_SP_21_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_22, RBBM_PERFCTR_SP_22_LO, RBBM_PERFCTR_SP_22_HI),
|
||||
COUNTER(SP_PERFCTR_SP_SEL_23, RBBM_PERFCTR_SP_23_LO, RBBM_PERFCTR_SP_23_HI),
|
||||
// COUNTER(SP_PERFCTR_SP_SEL(0), RBBM_PERFCTR_SP(0), RBBM_PERFCTR_SP(0)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(1), RBBM_PERFCTR_SP(1), RBBM_PERFCTR_SP(1)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(2), RBBM_PERFCTR_SP(2), RBBM_PERFCTR_SP(2)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(3), RBBM_PERFCTR_SP(3), RBBM_PERFCTR_SP(3)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(4), RBBM_PERFCTR_SP(4), RBBM_PERFCTR_SP(4)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(5), RBBM_PERFCTR_SP(5), RBBM_PERFCTR_SP(5)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(6), RBBM_PERFCTR_SP(6), RBBM_PERFCTR_SP(6)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(7), RBBM_PERFCTR_SP(7), RBBM_PERFCTR_SP(7)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(8), RBBM_PERFCTR_SP(8), RBBM_PERFCTR_SP(8)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(9), RBBM_PERFCTR_SP(9), RBBM_PERFCTR_SP(9)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(10), RBBM_PERFCTR_SP(10), RBBM_PERFCTR_SP(10)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(11), RBBM_PERFCTR_SP(11), RBBM_PERFCTR_SP(11)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(12), RBBM_PERFCTR_SP(12), RBBM_PERFCTR_SP(12)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(13), RBBM_PERFCTR_SP(13), RBBM_PERFCTR_SP(13)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(14), RBBM_PERFCTR_SP(14), RBBM_PERFCTR_SP(14)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(15), RBBM_PERFCTR_SP(15), RBBM_PERFCTR_SP(15)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(16), RBBM_PERFCTR_SP(16), RBBM_PERFCTR_SP(16)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(17), RBBM_PERFCTR_SP(17), RBBM_PERFCTR_SP(17)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(18), RBBM_PERFCTR_SP(18), RBBM_PERFCTR_SP(18)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(19), RBBM_PERFCTR_SP(19), RBBM_PERFCTR_SP(19)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(20), RBBM_PERFCTR_SP(20), RBBM_PERFCTR_SP(20)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(21), RBBM_PERFCTR_SP(21), RBBM_PERFCTR_SP(21)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(22), RBBM_PERFCTR_SP(22), RBBM_PERFCTR_SP(22)+1),
|
||||
COUNTER(SP_PERFCTR_SP_SEL(23), RBBM_PERFCTR_SP(23), RBBM_PERFCTR_SP(23)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable sp_countables[] = {
|
||||
|
|
@ -534,18 +534,18 @@ static const struct fd_perfcntr_countable sp_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter tp_counters[] = {
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_0, RBBM_PERFCTR_TP_0_LO, RBBM_PERFCTR_TP_0_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_1, RBBM_PERFCTR_TP_1_LO, RBBM_PERFCTR_TP_1_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_2, RBBM_PERFCTR_TP_2_LO, RBBM_PERFCTR_TP_2_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_3, RBBM_PERFCTR_TP_3_LO, RBBM_PERFCTR_TP_3_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_4, RBBM_PERFCTR_TP_4_LO, RBBM_PERFCTR_TP_4_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_5, RBBM_PERFCTR_TP_5_LO, RBBM_PERFCTR_TP_5_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_6, RBBM_PERFCTR_TP_6_LO, RBBM_PERFCTR_TP_6_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_7, RBBM_PERFCTR_TP_7_LO, RBBM_PERFCTR_TP_7_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_8, RBBM_PERFCTR_TP_8_LO, RBBM_PERFCTR_TP_8_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_9, RBBM_PERFCTR_TP_9_LO, RBBM_PERFCTR_TP_9_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_10, RBBM_PERFCTR_TP_10_LO, RBBM_PERFCTR_TP_10_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL_11, RBBM_PERFCTR_TP_11_LO, RBBM_PERFCTR_TP_11_HI),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(0), RBBM_PERFCTR_TP(0), RBBM_PERFCTR_TP(0)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(1), RBBM_PERFCTR_TP(1), RBBM_PERFCTR_TP(1)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(2), RBBM_PERFCTR_TP(2), RBBM_PERFCTR_TP(2)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(3), RBBM_PERFCTR_TP(3), RBBM_PERFCTR_TP(3)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(4), RBBM_PERFCTR_TP(4), RBBM_PERFCTR_TP(4)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(5), RBBM_PERFCTR_TP(5), RBBM_PERFCTR_TP(5)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(6), RBBM_PERFCTR_TP(6), RBBM_PERFCTR_TP(6)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(7), RBBM_PERFCTR_TP(7), RBBM_PERFCTR_TP(7)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(8), RBBM_PERFCTR_TP(8), RBBM_PERFCTR_TP(8)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(9), RBBM_PERFCTR_TP(9), RBBM_PERFCTR_TP(9)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(10), RBBM_PERFCTR_TP(10), RBBM_PERFCTR_TP(10)+1),
|
||||
COUNTER(TPL1_PERFCTR_TP_SEL(11), RBBM_PERFCTR_TP(11), RBBM_PERFCTR_TP(11)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable tp_countables[] = {
|
||||
|
|
@ -609,18 +609,18 @@ static const struct fd_perfcntr_countable tp_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter uche_counters[] = {
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_0, RBBM_PERFCTR_UCHE_0_LO, RBBM_PERFCTR_UCHE_0_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_1, RBBM_PERFCTR_UCHE_1_LO, RBBM_PERFCTR_UCHE_1_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_2, RBBM_PERFCTR_UCHE_2_LO, RBBM_PERFCTR_UCHE_2_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_3, RBBM_PERFCTR_UCHE_3_LO, RBBM_PERFCTR_UCHE_3_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_4, RBBM_PERFCTR_UCHE_4_LO, RBBM_PERFCTR_UCHE_4_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_5, RBBM_PERFCTR_UCHE_5_LO, RBBM_PERFCTR_UCHE_5_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_6, RBBM_PERFCTR_UCHE_6_LO, RBBM_PERFCTR_UCHE_6_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_7, RBBM_PERFCTR_UCHE_7_LO, RBBM_PERFCTR_UCHE_7_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_8, RBBM_PERFCTR_UCHE_8_LO, RBBM_PERFCTR_UCHE_8_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_9, RBBM_PERFCTR_UCHE_9_LO, RBBM_PERFCTR_UCHE_9_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_10, RBBM_PERFCTR_UCHE_10_LO, RBBM_PERFCTR_UCHE_10_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL_11, RBBM_PERFCTR_UCHE_11_LO, RBBM_PERFCTR_UCHE_11_HI),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(0), RBBM_PERFCTR_UCHE(0), RBBM_PERFCTR_UCHE(0)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(1), RBBM_PERFCTR_UCHE(1), RBBM_PERFCTR_UCHE(1)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(2), RBBM_PERFCTR_UCHE(2), RBBM_PERFCTR_UCHE(2)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(3), RBBM_PERFCTR_UCHE(3), RBBM_PERFCTR_UCHE(3)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(4), RBBM_PERFCTR_UCHE(4), RBBM_PERFCTR_UCHE(4)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(5), RBBM_PERFCTR_UCHE(5), RBBM_PERFCTR_UCHE(5)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(6), RBBM_PERFCTR_UCHE(6), RBBM_PERFCTR_UCHE(6)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(7), RBBM_PERFCTR_UCHE(7), RBBM_PERFCTR_UCHE(7)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(8), RBBM_PERFCTR_UCHE(8), RBBM_PERFCTR_UCHE(8)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(9), RBBM_PERFCTR_UCHE(9), RBBM_PERFCTR_UCHE(9)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(10), RBBM_PERFCTR_UCHE(10), RBBM_PERFCTR_UCHE(10)+1),
|
||||
COUNTER(UCHE_PERFCTR_UCHE_SEL(11), RBBM_PERFCTR_UCHE(11), RBBM_PERFCTR_UCHE(11)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable uche_countables[] = {
|
||||
|
|
@ -667,14 +667,14 @@ static const struct fd_perfcntr_countable uche_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter vfd_counters[] = {
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL_0, RBBM_PERFCTR_VFD_0_LO, RBBM_PERFCTR_VFD_0_HI),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL_1, RBBM_PERFCTR_VFD_1_LO, RBBM_PERFCTR_VFD_1_HI),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL_2, RBBM_PERFCTR_VFD_2_LO, RBBM_PERFCTR_VFD_2_HI),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL_3, RBBM_PERFCTR_VFD_3_LO, RBBM_PERFCTR_VFD_3_HI),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL_4, RBBM_PERFCTR_VFD_4_LO, RBBM_PERFCTR_VFD_4_HI),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL_5, RBBM_PERFCTR_VFD_5_LO, RBBM_PERFCTR_VFD_5_HI),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL_6, RBBM_PERFCTR_VFD_6_LO, RBBM_PERFCTR_VFD_6_HI),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL_7, RBBM_PERFCTR_VFD_7_LO, RBBM_PERFCTR_VFD_7_HI),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL(0), RBBM_PERFCTR_VFD(0), RBBM_PERFCTR_VFD(0)+1),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL(1), RBBM_PERFCTR_VFD(1), RBBM_PERFCTR_VFD(1)+1),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL(2), RBBM_PERFCTR_VFD(2), RBBM_PERFCTR_VFD(2)+1),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL(3), RBBM_PERFCTR_VFD(3), RBBM_PERFCTR_VFD(3)+1),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL(4), RBBM_PERFCTR_VFD(4), RBBM_PERFCTR_VFD(4)+1),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL(5), RBBM_PERFCTR_VFD(5), RBBM_PERFCTR_VFD(5)+1),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL(6), RBBM_PERFCTR_VFD(6), RBBM_PERFCTR_VFD(6)+1),
|
||||
COUNTER(VFD_PERFCTR_VFD_SEL(7), RBBM_PERFCTR_VFD(7), RBBM_PERFCTR_VFD(7)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable vfd_countables[] = {
|
||||
|
|
@ -704,12 +704,12 @@ static const struct fd_perfcntr_countable vfd_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter vpc_counters[] = {
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL_0, RBBM_PERFCTR_VPC_0_LO, RBBM_PERFCTR_VPC_0_HI),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL_1, RBBM_PERFCTR_VPC_1_LO, RBBM_PERFCTR_VPC_1_HI),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL_2, RBBM_PERFCTR_VPC_2_LO, RBBM_PERFCTR_VPC_2_HI),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL_3, RBBM_PERFCTR_VPC_3_LO, RBBM_PERFCTR_VPC_3_HI),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL_4, RBBM_PERFCTR_VPC_4_LO, RBBM_PERFCTR_VPC_4_HI),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL_5, RBBM_PERFCTR_VPC_5_LO, RBBM_PERFCTR_VPC_5_HI),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL(0), RBBM_PERFCTR_VPC(0), RBBM_PERFCTR_VPC(0)+1),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL(1), RBBM_PERFCTR_VPC(1), RBBM_PERFCTR_VPC(1)+1),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL(2), RBBM_PERFCTR_VPC(2), RBBM_PERFCTR_VPC(2)+1),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL(3), RBBM_PERFCTR_VPC(3), RBBM_PERFCTR_VPC(3)+1),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL(4), RBBM_PERFCTR_VPC(4), RBBM_PERFCTR_VPC(4)+1),
|
||||
COUNTER(VPC_PERFCTR_VPC_SEL(5), RBBM_PERFCTR_VPC(5), RBBM_PERFCTR_VPC(5)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable vpc_countables[] = {
|
||||
|
|
@ -744,8 +744,8 @@ static const struct fd_perfcntr_countable vpc_countables[] = {
|
|||
};
|
||||
|
||||
static const struct fd_perfcntr_counter vsc_counters[] = {
|
||||
COUNTER(VSC_PERFCTR_VSC_SEL_0, RBBM_PERFCTR_VSC_0_LO, RBBM_PERFCTR_VSC_0_HI),
|
||||
COUNTER(VSC_PERFCTR_VSC_SEL_1, RBBM_PERFCTR_VSC_1_LO, RBBM_PERFCTR_VSC_1_HI),
|
||||
COUNTER(VSC_PERFCTR_VSC_SEL(0), RBBM_PERFCTR_VSC(0), RBBM_PERFCTR_VSC(0)+1),
|
||||
COUNTER(VSC_PERFCTR_VSC_SEL(1), RBBM_PERFCTR_VSC(1), RBBM_PERFCTR_VSC(1)+1),
|
||||
};
|
||||
|
||||
static const struct fd_perfcntr_countable vsc_countables[] = {
|
||||
|
|
@ -777,4 +777,5 @@ const struct fd_perfcntr_group a6xx_perfcntr_groups[] = {
|
|||
|
||||
const unsigned a6xx_num_perfcntr_groups = ARRAY_SIZE(a6xx_perfcntr_groups);
|
||||
|
||||
#endif /* FD5_PERFCNTR_H_ */
|
||||
#endif /* FD6_PERFCNTR_H_ */
|
||||
|
||||
|
|
|
|||
|
|
@ -1036,20 +1036,7 @@ to upconvert to 32b float internally?
|
|||
<reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
|
||||
<reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
|
||||
<reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
|
||||
<reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
|
||||
<reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
|
||||
<reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
|
||||
<reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
|
||||
<reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
|
||||
<reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
|
||||
<reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
|
||||
<reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
|
||||
<reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
|
||||
<reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
|
||||
<reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
|
||||
<reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
|
||||
<reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
|
||||
<reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
|
||||
<array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
|
||||
<reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
|
||||
<reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
|
||||
<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
|
||||
|
|
@ -1139,256 +1126,22 @@ to upconvert to 32b float internally?
|
|||
<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
|
||||
<reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
|
||||
<reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
|
||||
<reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
|
||||
<reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
|
||||
<reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
|
||||
<reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
|
||||
<reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
|
||||
<reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
|
||||
<reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
|
||||
<reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
|
||||
<reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
|
||||
<reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
|
||||
<reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
|
||||
<reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
|
||||
<reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
|
||||
<reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
|
||||
<reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
|
||||
<reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
|
||||
<reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
|
||||
<reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
|
||||
<reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
|
||||
<reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
|
||||
<reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
|
||||
<reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
|
||||
<reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
|
||||
<reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
|
||||
<reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
|
||||
<reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
|
||||
<reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
|
||||
<reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
|
||||
<reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
|
||||
<reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
|
||||
<reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
|
||||
<reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
|
||||
<reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
|
||||
<reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
|
||||
<reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
|
||||
<reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
|
||||
<reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
|
||||
<reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
|
||||
<reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
|
||||
<reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
|
||||
<reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
|
||||
<reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
|
||||
<reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
|
||||
<reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
|
||||
<reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
|
||||
<reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
|
||||
<reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
|
||||
<reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
|
||||
<reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
|
||||
<reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
|
||||
<reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
|
||||
<reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
|
||||
<reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
|
||||
<reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
|
||||
<reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
|
||||
<reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
|
||||
<reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
|
||||
<reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
|
||||
<reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
|
||||
<reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
|
||||
<reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
|
||||
<reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
|
||||
<reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
|
||||
<reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
|
||||
<reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
|
||||
<reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
|
||||
<reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
|
||||
<reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
|
||||
<reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
|
||||
<reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
|
||||
<reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
|
||||
<reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
|
||||
<reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
|
||||
<reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
|
||||
<reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
|
||||
<reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
|
||||
<reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
|
||||
<reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
|
||||
<reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
|
||||
<reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
|
||||
<reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
|
||||
<reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
|
||||
<reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
|
||||
<reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
|
||||
<reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
|
||||
<reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
|
||||
<reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
|
||||
<reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
|
||||
<reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
|
||||
<reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
|
||||
<reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
|
||||
<reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
|
||||
<reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
|
||||
<reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
|
||||
<reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
|
||||
<reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
|
||||
<reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
|
||||
<reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
|
||||
<reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
|
||||
<reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
|
||||
<reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
|
||||
<reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
|
||||
<reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
|
||||
<reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
|
||||
<reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
|
||||
<reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
|
||||
<reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
|
||||
<reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
|
||||
<reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
|
||||
<reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
|
||||
<reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
|
||||
<reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
|
||||
<reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
|
||||
<reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
|
||||
<reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
|
||||
<reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
|
||||
<reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
|
||||
<reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
|
||||
<reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
|
||||
<reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
|
||||
<reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
|
||||
<reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
|
||||
<reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
|
||||
<reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
|
||||
<reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
|
||||
<reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
|
||||
<reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
|
||||
<reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
|
||||
<reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
|
||||
<reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
|
||||
<reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
|
||||
<reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
|
||||
<reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
|
||||
<reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
|
||||
<reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
|
||||
<reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
|
||||
<reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
|
||||
<reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
|
||||
<reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
|
||||
<reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
|
||||
<reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
|
||||
<reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
|
||||
<reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
|
||||
<reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
|
||||
<reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
|
||||
<reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
|
||||
<reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
|
||||
<reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
|
||||
<reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
|
||||
<reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
|
||||
<reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
|
||||
<reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
|
||||
<reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
|
||||
<reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
|
||||
<reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
|
||||
<reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
|
||||
<reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
|
||||
<reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
|
||||
<reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
|
||||
<reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
|
||||
<reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
|
||||
<reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
|
||||
<reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
|
||||
<reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
|
||||
<reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
|
||||
<reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
|
||||
<reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
|
||||
<reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
|
||||
<reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
|
||||
<reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
|
||||
<reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
|
||||
<reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
|
||||
<reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
|
||||
<reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
|
||||
<reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
|
||||
<reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
|
||||
<reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
|
||||
<reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
|
||||
<reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
|
||||
<reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
|
||||
<reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
|
||||
<reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
|
||||
<reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
|
||||
<reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
|
||||
<reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
|
||||
<reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
|
||||
<reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
|
||||
<reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
|
||||
<reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
|
||||
<reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
|
||||
<reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
|
||||
<reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
|
||||
<reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
|
||||
<reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
|
||||
<reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
|
||||
<reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
|
||||
<reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
|
||||
<reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
|
||||
<reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
|
||||
<reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
|
||||
<reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
|
||||
<reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
|
||||
<reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
|
||||
<reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
|
||||
<reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
|
||||
<reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
|
||||
<reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
|
||||
<reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
|
||||
<reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
|
||||
<reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
|
||||
<reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
|
||||
<reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
|
||||
<reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
|
||||
<reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
|
||||
<reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
|
||||
<reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
|
||||
<reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
|
||||
<reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
|
||||
<reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
|
||||
<reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
|
||||
<reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
|
||||
<reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
|
||||
<reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
|
||||
<reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
|
||||
<reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
|
||||
<reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
|
||||
<reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
|
||||
<reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
|
||||
<reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
|
||||
<reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
|
||||
<reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
|
||||
<reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
|
||||
<reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
|
||||
<reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
|
||||
<reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
|
||||
<reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
|
||||
<reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
|
||||
<reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
|
||||
<reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
|
||||
<reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
|
||||
<reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
|
||||
<reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
|
||||
<reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
|
||||
<reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
|
||||
<reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
|
||||
<reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
|
||||
<reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
|
||||
<reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
|
||||
<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14"/>
|
||||
<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4"/>
|
||||
<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8"/>
|
||||
<array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8"/>
|
||||
<array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6"/>
|
||||
<array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6"/>
|
||||
<array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5"/>
|
||||
<array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4"/>
|
||||
<array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4"/>
|
||||
<array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12"/>
|
||||
<array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12"/>
|
||||
<array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24"/>
|
||||
<array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8"/>
|
||||
<array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2"/>
|
||||
<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4"/>
|
||||
<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4"/>
|
||||
<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
|
||||
<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
|
||||
<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
|
||||
|
|
@ -1396,10 +1149,7 @@ to upconvert to 32b float internally?
|
|||
<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
|
||||
<reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
|
||||
<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
|
||||
<reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
|
||||
<reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
|
||||
<reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
|
||||
<reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
|
||||
<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
|
||||
<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
|
||||
<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
|
||||
|
||||
|
|
@ -1607,26 +1357,11 @@ to upconvert to 32b float internally?
|
|||
</reg32>
|
||||
<reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
|
||||
<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
|
||||
<reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
|
||||
<reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
|
||||
<array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
|
||||
<reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
|
||||
<reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
|
||||
<reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
|
||||
<reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
|
||||
<reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
|
||||
<reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
|
||||
<reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
|
||||
<reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
|
||||
<reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
|
||||
<reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
|
||||
<reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
|
||||
<reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
|
||||
<reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
|
||||
<reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
|
||||
<reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
|
||||
<reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
|
||||
<reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
|
||||
<reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
|
||||
<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
|
||||
<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
|
||||
<reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
|
||||
|
|
@ -1644,44 +1379,9 @@ to upconvert to 32b float internally?
|
|||
<reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
|
||||
<bitfield high="7" low="0" name="PERFSEL"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
|
||||
<reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
|
||||
<reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
|
||||
<reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
|
||||
<reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
|
||||
<reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
|
||||
<reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
|
||||
<reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
|
||||
<reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
|
||||
<reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
|
||||
<reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
|
||||
<reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
|
||||
<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
|
||||
<reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
|
||||
<reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
|
||||
<reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
|
||||
<reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
|
||||
<reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
|
||||
<reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
|
||||
<reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
|
||||
<reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
|
||||
<reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
|
||||
<reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
|
||||
<reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
|
||||
<reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
|
||||
<reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
|
||||
<reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
|
||||
<reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
|
||||
<reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
|
||||
<reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
|
||||
<reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
|
||||
<reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
|
||||
<reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
|
||||
<reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
|
||||
<reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
|
||||
<reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
|
||||
<reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
|
||||
<reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
|
||||
<reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
|
||||
<reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
|
||||
<reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
|
||||
<reg32 offset="0xB608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0"/>
|
||||
|
|
@ -1689,18 +1389,6 @@ to upconvert to 32b float internally?
|
|||
<reg32 offset="0xB60A" name="TPL1_BICUBIC_WEIGHTS_TABLE_2"/>
|
||||
<reg32 offset="0xB60B" name="TPL1_BICUBIC_WEIGHTS_TABLE_3"/>
|
||||
<reg32 offset="0xB60C" name="TPL1_BICUBIC_WEIGHTS_TABLE_4"/>
|
||||
<reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
|
||||
<reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
|
||||
<reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
|
||||
<reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
|
||||
<reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
|
||||
<reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
|
||||
<reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
|
||||
<reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
|
||||
<reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
|
||||
<reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
|
||||
<reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
|
||||
<reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
|
||||
<reg32 offset="0x3000" name="VBIF_VERSION"/>
|
||||
<reg32 offset="0x3001" name="VBIF_CLKON">
|
||||
<bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
|
||||
|
|
@ -2141,18 +1829,9 @@ to upconvert to 32b float internally?
|
|||
<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
|
||||
<reg32 offset="0x8600" name="GRAS_UNKNOWN_8600" low="0" high="12" />
|
||||
<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
|
||||
<reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
|
||||
<reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
|
||||
<reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
|
||||
<reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
|
||||
<reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
|
||||
<reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
|
||||
<reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
|
||||
<reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
|
||||
<reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
|
||||
<reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
|
||||
<reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
|
||||
<reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
|
||||
<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
|
||||
<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
|
||||
<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
|
||||
|
||||
<!-- note 0x8620-0x87ff are not all invalid
|
||||
(in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
|
||||
|
|
@ -2610,28 +2289,14 @@ to upconvert to 32b float internally?
|
|||
<bitfield name="UNK12" low="12" high="13"/>
|
||||
</reg32>
|
||||
<!-- 0x8e09-0x8e0f invalid -->
|
||||
<reg32 offset="0x8e10" name="RB_PERFCTR_RB_SEL_0"/>
|
||||
<reg32 offset="0x8e11" name="RB_PERFCTR_RB_SEL_1"/>
|
||||
<reg32 offset="0x8e12" name="RB_PERFCTR_RB_SEL_2"/>
|
||||
<reg32 offset="0x8e13" name="RB_PERFCTR_RB_SEL_3"/>
|
||||
<reg32 offset="0x8e14" name="RB_PERFCTR_RB_SEL_4"/>
|
||||
<reg32 offset="0x8e15" name="RB_PERFCTR_RB_SEL_5"/>
|
||||
<reg32 offset="0x8e16" name="RB_PERFCTR_RB_SEL_6"/>
|
||||
<reg32 offset="0x8e17" name="RB_PERFCTR_RB_SEL_7"/>
|
||||
<reg32 offset="0x8e18" name="RB_PERFCTR_CCU_SEL_0"/>
|
||||
<reg32 offset="0x8e19" name="RB_PERFCTR_CCU_SEL_1"/>
|
||||
<reg32 offset="0x8e1a" name="RB_PERFCTR_CCU_SEL_2"/>
|
||||
<reg32 offset="0x8e1b" name="RB_PERFCTR_CCU_SEL_3"/>
|
||||
<reg32 offset="0x8e1c" name="RB_PERFCTR_CCU_SEL_4"/>
|
||||
<array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
|
||||
<array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
|
||||
<!-- 0x8e1d-0x8e1f invalid -->
|
||||
<!-- 0x8e20-0x8e25 more perfcntr sel? -->
|
||||
<!-- 0x8e26-0x8e27 invalid -->
|
||||
<reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
|
||||
<!-- 0x8e29-0x8e2b invalid -->
|
||||
<reg32 offset="0x8e2c" name="RB_PERFCTR_CMP_SEL_0"/>
|
||||
<reg32 offset="0x8e2d" name="RB_PERFCTR_CMP_SEL_1"/>
|
||||
<reg32 offset="0x8e2e" name="RB_PERFCTR_CMP_SEL_2"/>
|
||||
<reg32 offset="0x8e2f" name="RB_PERFCTR_CMP_SEL_3"/>
|
||||
<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
|
||||
<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
|
||||
<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
|
||||
<!-- 0x8e3e-0x8e4f invalid -->
|
||||
|
|
@ -2816,12 +2481,7 @@ to upconvert to 32b float internally?
|
|||
<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
|
||||
<reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
|
||||
<reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
|
||||
<reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
|
||||
<reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
|
||||
<reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
|
||||
<reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
|
||||
<reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
|
||||
<reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
|
||||
<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6"/>
|
||||
<!-- 0x960a-0x9623 invalid -->
|
||||
<!-- TODO: regs from 0x9624-0x963a -->
|
||||
<!-- 0x963b-0x97ff invalid -->
|
||||
|
|
@ -2976,14 +2636,7 @@ to upconvert to 32b float internally?
|
|||
<reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
|
||||
<reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
|
||||
|
||||
<reg32 offset="0x9e34" name="PC_PERFCTR_PC_SEL_0"/>
|
||||
<reg32 offset="0x9e35" name="PC_PERFCTR_PC_SEL_1"/>
|
||||
<reg32 offset="0x9e36" name="PC_PERFCTR_PC_SEL_2"/>
|
||||
<reg32 offset="0x9e37" name="PC_PERFCTR_PC_SEL_3"/>
|
||||
<reg32 offset="0x9e38" name="PC_PERFCTR_PC_SEL_4"/>
|
||||
<reg32 offset="0x9e39" name="PC_PERFCTR_PC_SEL_5"/>
|
||||
<reg32 offset="0x9e3a" name="PC_PERFCTR_PC_SEL_6"/>
|
||||
<reg32 offset="0x9e3b" name="PC_PERFCTR_PC_SEL_7"/>
|
||||
<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8"/>
|
||||
|
||||
<!-- always 0x0 -->
|
||||
<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
|
||||
|
|
@ -3074,6 +2727,7 @@ to upconvert to 32b float internally?
|
|||
<value value="0" name="THREAD64"/>
|
||||
<value value="1" name="THREAD128"/>
|
||||
</enum>
|
||||
<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8"/>
|
||||
|
||||
<bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
|
||||
<!--
|
||||
|
|
@ -3552,9 +3206,18 @@ to upconvert to 32b float internally?
|
|||
|
||||
<reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
|
||||
<reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
|
||||
|
||||
<!-- always 0x3f ? -->
|
||||
<reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
|
||||
<reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE">
|
||||
<!-- some perfcntrs are affected by a per-stage enable bit
|
||||
(PERF_SP_ALU_WORKING_CYCLES for example)
|
||||
TODO: verify position of HS/DS/GS bits -->
|
||||
<bitfield name="VS" pos="0" type="boolean"/>
|
||||
<bitfield name="HS" pos="1" type="boolean"/>
|
||||
<bitfield name="DS" pos="2" type="boolean"/>
|
||||
<bitfield name="GS" pos="3" type="boolean"/>
|
||||
<bitfield name="FS" pos="4" type="boolean"/>
|
||||
<bitfield name="CS" pos="5" type="boolean"/>
|
||||
</reg32>
|
||||
<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
|
||||
|
||||
<!--
|
||||
The downstream kernel calls the debug cluster of registers
|
||||
|
|
@ -3616,6 +3279,7 @@ to upconvert to 32b float internally?
|
|||
|
||||
<!-- always 0x44 ? -->
|
||||
<reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
|
||||
<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12"/>
|
||||
|
||||
<bitset name="a6xx_hlsq_xs_cntl" inline="yes">
|
||||
<bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
|
||||
|
|
@ -3800,6 +3464,7 @@ to upconvert to 32b float internally?
|
|||
<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
|
||||
<!-- always 0x0 ? -->
|
||||
<reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
|
||||
<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
|
||||
|
||||
<!--
|
||||
These special registers signal the beginning/end of an event
|
||||
|
|
|
|||
|
|
@ -746,7 +746,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
|
|||
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
|
||||
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
|
||||
|
|
|
|||
|
|
@ -1221,7 +1221,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
|
|||
WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
|
||||
WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
|
||||
WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
|
||||
WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
|
||||
WRITE(REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
|
||||
WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
|
||||
WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
|
||||
WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
|
||||
|
|
|
|||
Loading…
Reference in New Issue