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r600g: fixup r700 CB_SHADER_CONTROL register. 

r600c emits this with a mask of each written output.
This commit is contained in:
Dave Airlie 2010-09-20 15:36:52 +10:00
parent d172ef3138
commit b110ddd9a9
3 changed files with 36 additions and 35 deletions
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9
src/gallium/drivers/r600/r600_hw_states.c
View File

@ -618,15 +618,17 @@ static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
struct r600_screen *rscreen = rctx->screen;
const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
uint32_t color_control, target_mask, shader_mask;
uint32_t color_control, target_mask, shader_mask, shader_control;
int i;
target_mask = 0;
shader_mask = 0;
shader_control = 0;
color_control = S_028808_PER_MRT_BLEND(1);
for (i = 0; i < nr_cbufs; i++) {
shader_mask |= 0xf << (i * 4);
shader_control |= (1 << i);
}
if (pbs->logicop_enable) {
@ -654,6 +656,8 @@ static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
if (rscreen->chip_class == R700)
rstate->states[R600_CB_CNTL__CB_SHADER_CONTROL] = shader_control;
rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
@ -884,9 +888,6 @@ static void r600_init_config(struct r600_context *rctx)
S_028A4C_WALK_ORDER_ENABLE(1) |
S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
}
rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] =
S_0287A0_RT0_ENABLE(1) |
S_0287A0_RT1_ENABLE(1);
rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;

60
src/gallium/drivers/r600/r600_states_inc.h
View File

@ -15,35 +15,34 @@
#define R600_CONFIG__DB_WATERMARKS 10
#define R600_CONFIG__SX_MISC 11
#define R600_CONFIG__SPI_THREAD_GROUPING 12
#define R600_CONFIG__CB_SHADER_CONTROL 13
#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14
#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15
#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16
#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17
#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18
#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19
#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20
#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21
#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22
#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23
#define R600_CONFIG__VGT_HOS_CNTL 24
#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25
#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26
#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27
#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28
#define R600_CONFIG__VGT_GROUP_FIRST_DECR 29
#define R600_CONFIG__VGT_GROUP_DECR 30
#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31
#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32
#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33
#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34
#define R600_CONFIG__VGT_GS_MODE 35
#define R600_CONFIG__PA_SC_MODE_CNTL 36
#define R600_CONFIG__VGT_STRMOUT_EN 37
#define R600_CONFIG__VGT_REUSE_OFF 38
#define R600_CONFIG__VGT_VTX_CNT_EN 39
#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40
#define R600_CONFIG_SIZE 41
#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 13
#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 14
#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 15
#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 16
#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 17
#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 18
#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 19
#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 20
#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 21
#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 22
#define R600_CONFIG__VGT_HOS_CNTL 23
#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 24
#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 25
#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 26
#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 27
#define R600_CONFIG__VGT_GROUP_FIRST_DECR 28
#define R600_CONFIG__VGT_GROUP_DECR 29
#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 30
#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 31
#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 32
#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 33
#define R600_CONFIG__VGT_GS_MODE 34
#define R600_CONFIG__PA_SC_MODE_CNTL 35
#define R600_CONFIG__VGT_STRMOUT_EN 36
#define R600_CONFIG__VGT_REUSE_OFF 37
#define R600_CONFIG__VGT_VTX_CNT_EN 38
#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 39
#define R600_CONFIG_SIZE 40
#define R600_CONFIG_PM4 128
/* R600_CB_CNTL */
@ -65,7 +64,8 @@
#define R600_CB_CNTL__CB_CLRCMP_DST 15
#define R600_CB_CNTL__CB_CLRCMP_MSK 16
#define R600_CB_CNTL__PA_SC_AA_MASK 17
#define R600_CB_CNTL_SIZE 18
#define R600_CB_CNTL__CB_SHADER_CONTROL 18
#define R600_CB_CNTL_SIZE 19
#define R600_CB_CNTL_PM4 128
/* R600_RASTERIZER */

2
src/gallium/winsys/r600/drm/r600_states.h
View File

@ -31,7 +31,6 @@ static const struct radeon_register R600_names_CONFIG[] = {
{0x00009838, 0, 0, "DB_WATERMARKS"},
{0x00028350, 0, 0, "SX_MISC"},
{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
{0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
{0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
{0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
{0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
@ -80,6 +79,7 @@ static const struct radeon_register R600_names_CB_CNTL[] = {
{0x00028C38, 0, 0, "CB_CLRCMP_DST"},
{0x00028C3C, 0, 0, "CB_CLRCMP_MSK"},
{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
{0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
};
static const struct radeon_register R600_names_RASTERIZER[] = {