pan/va: Use XML for special FAU page 0
Now all special FAU handling is unified, which makes both assembler and disassembler considerably nicer. This adds some more special FAU indices from page 0 that were previously missing, allowing them to be assembled and disasembled. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
31a171d92d
commit
b0faf422b7
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@ -94,6 +94,32 @@
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<value name="Return from shader">return</value>
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</enum>
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<enum name="FAU special page 0">
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<desc>
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Situated between the immediates hard-coded in the hardware and the
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uniforms defined purely in software, Valhall has a some special
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"constants" passing through data structures. These are encoded like the
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table of immediates, as if special constant $i$ were lookup table entry
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$32 + i$.
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</desc>
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<reserved/>
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<reserved/>
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<value desc="Warp ID and warps/core - 1">warp_id</value>
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<reserved/>
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<value desc="Bounding box maximum X/Y">framebuffer_size</value>
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<value desc="ATEST datum">atest_datum</value>
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<value desc="Sample positions">sample</value>
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<reserved/>
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<value desc="Blend descriptor 0">blend_descriptor_0</value>
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<value desc="Blend descriptor 1">blend_descriptor_1</value>
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<value desc="Blend descriptor 2">blend_descriptor_2</value>
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<value desc="Blend descriptor 3">blend_descriptor_3</value>
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<value desc="Blend descriptor 4">blend_descriptor_4</value>
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<value desc="Blend descriptor 5">blend_descriptor_5</value>
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<value desc="Blend descriptor 6">blend_descriptor_6</value>
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<value desc="Blend descriptor 7">blend_descriptor_7</value>
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</enum>
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<enum name="FAU special page 1">
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<desc>
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Situated between the immediates hard-coded in the hardware and the
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@ -91,21 +91,7 @@ def parse_int(s, minimum, maximum):
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return number
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def encode_source(op, fau):
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if op == 'atest_datum':
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fau.set_page(0)
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return 0x2A | 0xC0
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elif op.startswith('blend_descriptor_'):
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fau.set_page(0)
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fin = op[len('blend_descriptor_'):]
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die_if(len(fin) != 3, 'Bad syntax')
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die_if(fin[1] != '_', 'Bad syntax')
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die_if(fin[2] not in ['x', 'y'], 'Bad component')
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rt = parse_int(fin[0], 0, 7)
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hi = 1 if (fin[2] == 'y') else 0
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return (0x30 | (2*rt) + hi) | 0xC0
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elif op[0] == '`':
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if op[0] == '`':
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die_if(op[1] != 'r', f"Expected register after discard {op}")
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return parse_int(op[2:], 0, 63) | 0x40
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elif op[0] == 'r':
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@ -116,14 +102,6 @@ def encode_source(op, fau):
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return (val & 0x3F) | 0x80
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elif op[0] == 'i':
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return int(op[3:]) | 0xC0
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elif op in enums['fau_special_page_1'].bare_values:
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idx = 32 + (enums['fau_special_page_1'].bare_values.index(op) << 1)
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fau.set_page(1)
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return idx | 0xC0
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elif op in enums['fau_special_page_3'].bare_values:
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idx = 32 + (enums['fau_special_page_3'].bare_values.index(op) << 1)
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fau.set_page(3)
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return idx | 0xC0
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elif op.startswith('0x'):
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try:
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val = int(op, base=0)
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@ -133,8 +111,15 @@ def encode_source(op, fau):
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die_if(val not in immediates, 'Unexpected immediate value')
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return immediates.index(val) | 0xC0
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else:
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for i in [0, 1, 3]:
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if op in enums[f'fau_special_page_{i}'].bare_values:
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idx = 32 + (enums[f'fau_special_page_{i}'].bare_values.index(op) << 1)
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fau.set_page(i)
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return idx | 0xC0
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die('Invalid operand')
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def encode_dest(op):
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die_if(op[0] != 'r', f"Expected register destination {op}")
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@ -78,22 +78,16 @@ va_print_src(FILE *fp, uint8_t src, unsigned fau_page)
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if (type == VA_SRC_IMM_TYPE) {
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if (value >= 32) {
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if (fau_page == 0) {
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if (value >= 0x30)
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fprintf(fp, "blend_descriptor_%u_%c", (value - 0x30) >> 1, value & 1 ? 'y' : 'x');
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else if (value == 0x2A)
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fprintf(fp, "atest_datum");
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else
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fprintf(fp, "unk:%X", value);
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} else if (fau_page == 1) {
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if (fau_page == 0)
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fputs(valhall_fau_special_page_0[(value - 0x20) >> 1] + 1, fp);
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else if (fau_page == 1)
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fputs(valhall_fau_special_page_1[(value - 0x20) >> 1] + 1, fp);
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fprintf(fp, ".w%u", value & 1);
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} else if (fau_page == 3) {
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else if (fau_page == 3)
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fputs(valhall_fau_special_page_3[(value - 0x20) >> 1] + 1, fp);
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fprintf(fp, ".w%u", value & 1);
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} else {
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fprintf(fp, "unk:%X", value);
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}
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else
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fprintf(fp, "reserved_page2");
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fprintf(fp, ".w%u", value & 1);
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} else {
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fprintf(fp, "0x%X", va_immediates[value]);
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}
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@ -48,9 +48,9 @@ e6 00 00 00 00 c1 91 06 MOV.i32 r1, core_id.w0
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42 43 04 00 00 c0 a5 00 V2F32_TO_V2F16 r0, `r2, `r3
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40 c0 00 28 90 c0 a5 48 FADD.v2f16.barrier r0, `r0.abs, 0x0.neg
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c0 00 00 00 00 f6 10 01 IADD_IMM.i32 r54, 0x0, #0x0
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3c d0 ea 00 02 bc 7d 68 ATEST.td @r60, r60, 0x3F800000, atest_datum
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3c d0 ea 00 02 bc 7d 68 ATEST.td @r60, r60, 0x3F800000, atest_datum.w0
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40 db 05 04 00 c1 a1 00 MKVEC.v2i16 r1, `r0.h00, 0x3C000000.h10
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f0 00 3c 33 04 40 7f 78 BLEND.slot0.v4.f16.return @r0:r1, blend_descriptor_0_x, r60, target:0x0
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f0 00 3c 33 04 40 7f 78 BLEND.slot0.v4.f16.return @r0:r1, blend_descriptor_0.w0, r60, target:0x0
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7b 0d 00 40 04 84 5e 08 LEA_BUF_IMM.slot1.wait0 @r4:r5, `r59, table:0xD, index:0x0
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00 dd c0 08 14 c2 b2 00 FMA.f32 r2, r0, 0x44000000.neg.h1, 0x0.neg
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41 88 c0 00 04 c1 b2 00 FMA.f32 r1, `r1, u8, 0x0.neg
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@ -202,7 +202,7 @@ c0 00 00 00 00 c9 10 01 IADD_IMM.i32 r9, 0x0, #0x0
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49 3e c0 22 04 c9 b3 30 FMA.v2f16.wait12 r9, `r9, r62.h00, 0x0.neg
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47 43 00 00 00 c3 a4 00 FADD.f32 r3, `r7, `r3
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43 09 00 08 00 c3 a4 40 FADD.f32.wait0126 r3, `r3, r9.h1
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3c 03 ea 00 02 bc 7d 68 ATEST.td @r60, r60, r3, atest_datum
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3c 03 ea 00 02 bc 7d 68 ATEST.td @r60, r60, r3, atest_datum.w0
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46 42 00 00 00 c2 a4 00 FADD.f32 r2, `r6, `r2
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44 40 00 00 00 c0 a4 00 FADD.f32 r0, `r4, `r0
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48 7e c0 22 04 ff b3 00 FMA.v2f16 r63, `r8, `r62.h00, 0x0.neg
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@ -210,9 +210,9 @@ c0 00 00 00 00 c9 10 01 IADD_IMM.i32 r9, 0x0, #0x0
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41 3f 00 08 00 c1 a4 00 FADD.f32 r1, `r1, r63.h1
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40 7f 00 04 00 c0 a4 00 FADD.f32 r0, `r0, `r63.h0
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42 49 00 04 00 c2 a4 48 FADD.f32.barrier r2, `r2, `r9.h0
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f0 00 3c 32 08 40 7f 78 BLEND.slot0.v4.f32.return @r0:r1:r2:r3, blend_descriptor_0_x, r60, target:0x0
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f0 00 3c 32 08 40 7f 78 BLEND.slot0.v4.f32.return @r0:r1:r2:r3, blend_descriptor_0.w0, r60, target:0x0
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c0 00 00 00 00 f6 10 01 IADD_IMM.i32 r54, 0x0, #0x0
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c0 f1 00 00 10 c1 2f 08 BRANCHZI.eq.absolute.wait0 0x0, blend_descriptor_0_y
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c0 f1 00 00 10 c1 2f 08 BRANCHZI.eq.absolute.wait0 0x0, blend_descriptor_0.w1
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80 00 c0 17 34 7c 25 01 TEX_FETCH.slot0.f.32.2d @r0:r1:r2:r3, @r60:r61, u0
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80 00 00 00 00 c1 91 02 MOV.i32 r1, u64
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81 00 00 00 00 c1 91 02 MOV.i32 r1, u65
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