intel/fs: Add a couple of simple helper opcodes
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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@ -460,6 +460,19 @@ enum opcode {
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*/
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SHADER_OPCODE_SHUFFLE,
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/* Select between src0 and src1 based on channel enables.
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*
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* This instruction copies src0 into the enabled channels of the
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* destination and copies src1 into the disabled channels.
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*/
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SHADER_OPCODE_SEL_EXEC,
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/* Take every Nth element in src0 and broadcast it to the group of N
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* channels in which it lives in the destination. The offset within the
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* cluster is given by src1 and the cluster size is given by src2.
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*/
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SHADER_OPCODE_CLUSTER_BROADCAST,
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SHADER_OPCODE_GET_BUFFER_SIZE,
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VEC4_OPCODE_MOV_BYTES,
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@ -316,6 +316,15 @@ fs_inst::has_source_and_destination_hazard() const
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* that one of the instructions will read from a channel corresponding
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* to an earlier instruction.
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*/
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case SHADER_OPCODE_SEL_EXEC:
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/* This is implemented as
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*
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* mov(16) g4<1>D 0D { align1 WE_all 1H };
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* mov(16) g4<1>D g5<8,8,1>D { align1 1H }
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*
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* Because the source is only read in the second instruction, the first
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* may stomp all over it.
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*/
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return true;
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default:
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/* The SIMD16 compressed instruction
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@ -5038,6 +5047,8 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
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case BRW_OPCODE_MAD:
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case BRW_OPCODE_LRP:
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case FS_OPCODE_PACK:
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case SHADER_OPCODE_SEL_EXEC:
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case SHADER_OPCODE_CLUSTER_BROADCAST:
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return get_fpu_lowered_simd_width(devinfo, inst);
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case BRW_OPCODE_CMP: {
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@ -2293,6 +2293,53 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
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generate_shuffle(inst, dst, src[0], src[1]);
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break;
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case SHADER_OPCODE_SEL_EXEC:
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assert(inst->force_writemask_all);
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brw_set_default_mask_control(p, BRW_MASK_DISABLE);
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brw_MOV(p, dst, src[1]);
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brw_set_default_mask_control(p, BRW_MASK_ENABLE);
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brw_MOV(p, dst, src[0]);
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break;
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case SHADER_OPCODE_CLUSTER_BROADCAST: {
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assert(src[0].type == dst.type);
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assert(!src[0].negate && !src[0].abs);
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assert(src[1].file == BRW_IMMEDIATE_VALUE);
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assert(src[1].type == BRW_REGISTER_TYPE_UD);
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assert(src[2].file == BRW_IMMEDIATE_VALUE);
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assert(src[2].type == BRW_REGISTER_TYPE_UD);
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const unsigned component = src[1].ud;
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const unsigned cluster_size = src[2].ud;
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struct brw_reg strided = stride(suboffset(src[0], component),
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cluster_size, cluster_size, 0);
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if (type_sz(src[0].type) > 4 &&
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(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
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/* IVB has an issue (which we found empirically) where it reads
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* two address register components per channel for indirectly
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* addressed 64-bit sources.
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*
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* From the Cherryview PRM Vol 7. "Register Region Restrictions":
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*
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* "When source or destination datatype is 64b or operation is
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* integer DWord multiply, indirect addressing must not be
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* used."
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*
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* To work around both of these, we do two integer MOVs insead of
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* one 64-bit MOV. Because no double value should ever cross a
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* register boundary, it's safe to use the immediate offset in the
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* indirect here to handle adding 4 bytes to the offset and avoid
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* the extra ADD to the register file.
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*/
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
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subscript(strided, BRW_REGISTER_TYPE_D, 0));
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
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subscript(strided, BRW_REGISTER_TYPE_D, 1));
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} else {
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brw_MOV(p, dst, strided);
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}
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break;
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}
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case FS_OPCODE_SET_SAMPLE_ID:
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generate_set_sample_id(inst, dst, src[0], src[1]);
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break;
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@ -332,6 +332,10 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
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return "broadcast";
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case SHADER_OPCODE_SHUFFLE:
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return "shuffle";
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case SHADER_OPCODE_SEL_EXEC:
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return "sel_exec";
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case SHADER_OPCODE_CLUSTER_BROADCAST:
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return "cluster_broadcast";
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case SHADER_OPCODE_GET_BUFFER_SIZE:
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return "get_buffer_size";
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@ -847,6 +851,7 @@ backend_instruction::can_do_source_mods() const
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case BRW_OPCODE_FBL:
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case BRW_OPCODE_SUBB:
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case SHADER_OPCODE_BROADCAST:
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case SHADER_OPCODE_CLUSTER_BROADCAST:
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case SHADER_OPCODE_MOV_INDIRECT:
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return false;
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default:
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