radeonsi: add support for indirect samplers (v2)
This adds the frontend support, however the llvm backend produces the wrong pattern, however we can conditionalise enabling ARB_gpu_shader5 on whatever version of llvm we fix this in. v2: drop unneeded sampler_indirect checks (Marek) Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -98,7 +98,7 @@ GL 4.0, GLSL 4.00:
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GL_ARB_draw_indirect DONE (i965, nvc0, r600, radeonsi, llvmpipe, softpipe)
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GL_ARB_gpu_shader5 DONE (i965, nvc0)
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- 'precise' qualifier DONE
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- Dynamically uniform sampler array indices DONE (r600, softpipe)
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- Dynamically uniform sampler array indices DONE (r600, radeonsi, softpipe)
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- Dynamically uniform UBO array indices DONE (r600)
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- Implicit signed -> unsigned conversions DONE
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- Fused multiply-add DONE ()
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@ -2252,9 +2252,29 @@ static void tex_fetch_args(
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unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
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unsigned count = 0;
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unsigned chan;
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unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
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unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
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unsigned sampler_src;
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unsigned sampler_index;
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bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
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LLVMValueRef res_ptr, samp_ptr;
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sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
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sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
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if (emit_data->inst->Src[sampler_src].Register.Indirect) {
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const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
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LLVMValueRef ind_index;
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ind_index = get_indirect_index(si_shader_ctx, ®->Indirect, reg->Register.Index);
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res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
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res_ptr = build_indexed_load_const(si_shader_ctx, res_ptr, ind_index);
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samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
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samp_ptr = build_indexed_load_const(si_shader_ctx, samp_ptr, ind_index);
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} else {
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res_ptr = si_shader_ctx->resources[sampler_index];
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samp_ptr = si_shader_ctx->samplers[sampler_index];
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}
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if (target == TGSI_TEXTURE_BUFFER) {
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LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
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@ -2263,7 +2283,7 @@ static void tex_fetch_args(
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LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
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/* Bitcast and truncate v8i32 to v16i8. */
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LLVMValueRef res = si_shader_ctx->resources[sampler_index];
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LLVMValueRef res = res_ptr;
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res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
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res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
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res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
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@ -2489,7 +2509,7 @@ static void tex_fetch_args(
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}
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/* Resource */
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emit_data->args[1] = si_shader_ctx->resources[sampler_index];
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emit_data->args[1] = res_ptr;
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if (opcode == TGSI_OPCODE_TXF) {
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/* add tex offsets */
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@ -2572,7 +2592,7 @@ static void tex_fetch_args(
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dmask = 1 << gather_comp;
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}
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emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
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emit_data->args[2] = samp_ptr;
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emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
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emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
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emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
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@ -2588,7 +2608,7 @@ static void tex_fetch_args(
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LLVMFloatTypeInContext(gallivm->context),
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4);
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} else {
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emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
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emit_data->args[2] = samp_ptr;
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emit_data->args[3] = lp_build_const_int32(gallivm, target);
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emit_data->arg_count = 4;
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@ -2734,13 +2754,26 @@ static void txq_fetch_args(
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const struct tgsi_full_instruction *inst = emit_data->inst;
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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unsigned target = inst->Texture.Texture;
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LLVMValueRef res_ptr;
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if (inst->Src[1].Register.Indirect) {
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const struct tgsi_full_src_register *reg = &inst->Src[1];
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LLVMValueRef ind_index;
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ind_index = get_indirect_index(si_shader_ctx, ®->Indirect, reg->Register.Index);
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res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
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res_ptr = build_indexed_load_const(si_shader_ctx, res_ptr,
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ind_index);
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} else
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res_ptr = si_shader_ctx->resources[inst->Src[1].Register.Index];
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if (target == TGSI_TEXTURE_BUFFER) {
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LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
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LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
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/* Read the size from the buffer descriptor directly. */
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LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
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LLVMValueRef size = res_ptr;
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size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
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size = LLVMBuildExtractElement(gallivm->builder, size,
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lp_build_const_int32(gallivm, 6), "");
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@ -2752,7 +2785,7 @@ static void txq_fetch_args(
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emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
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/* Resource */
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emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
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emit_data->args[1] = res_ptr;
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/* Texture target */
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if (target == TGSI_TEXTURE_CUBE_ARRAY ||
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