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ac: add has_out_of_order_rast to ac_gpu_info 

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Samuel Pitoiset 2019-08-20 17:16:41 +02:00
parent ed720af46d
commit b027ad66d7
6 changed files with 7 additions and 8 deletions
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3
src/amd/common/ac_gpu_info.c
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@ -457,6 +457,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->has_rbplus = info->family == CHIP_STONEY ||
info->chip_class >= GFX9;
info->has_out_of_order_rast = info->chip_class >= GFX8 &&
info->max_se >= 2;
/* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
(info->chip_class >= GFX8 &&

1
src/amd/common/ac_gpu_info.h
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@ -63,6 +63,7 @@ struct radeon_info {
bool has_dcc_constant_encode;
bool has_rbplus; /* if RB+ registers exist */
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */

5
src/amd/vulkan/radv_device.c
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@ -371,10 +371,7 @@ radv_physical_device_init(struct radv_physical_device *device,
device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
/* Out-of-order primitive rasterization. */
device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
device->rad_info.max_se >= 2;
device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
!(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
device->dcc_msaa_allowed =

2
src/amd/vulkan/radv_extensions.py
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@ -140,7 +140,7 @@ EXTENSIONS = [
Extension('VK_AMD_gcn_shader', 1, True),
Extension('VK_AMD_gpu_shader_half_float', 1, 'device->rad_info.chip_class >= GFX9'),
Extension('VK_AMD_gpu_shader_int16', 1, 'device->rad_info.chip_class >= GFX9'),
Extension('VK_AMD_rasterization_order', 1, 'device->has_out_of_order_rast'),
Extension('VK_AMD_rasterization_order', 1, 'device->rad_info.has_out_of_order_rast'),
Extension('VK_AMD_shader_ballot', 1, 'device->use_shader_ballot'),
Extension('VK_AMD_shader_core_properties', 1, True),
Extension('VK_AMD_shader_core_properties2', 1, True),

1
src/amd/vulkan/radv_private.h
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@ -285,7 +285,6 @@ struct radv_physical_device {
bool has_scissor_bug;
bool has_tc_compat_zrange_bug;
bool has_out_of_order_rast;
bool out_of_order_rast_allowed;
/* Whether DCC should be enabled for MSAA textures. */

3
src/gallium/drivers/radeonsi/si_pipe.c
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@ -1121,8 +1121,7 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
sscreen->info.pfp_fw_version >= 79 &&
sscreen->info.me_fw_version >= 142);
sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 &&
sscreen->info.max_se >= 2 &&
sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast &&
!(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
sscreen->assume_no_z_fights =
driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");