i965: new state dump for sandybridge
Dump new state object on sandybridge for cc viewport, clip viewport, depth stencil, cc and blend state.
This commit is contained in:
Zhenyu Wang
parent
bf60f35934
commit
b016a78b98
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@ -161,6 +161,123 @@ static void dump_sf_viewport_state(struct brw_context *brw)
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drm_intel_bo_unmap(brw->sf.vp_bo);
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}
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static void dump_clip_viewport_state(struct brw_context *brw)
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{
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const char *name = "CLIP VP";
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struct brw_clipper_viewport *vp;
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uint32_t vp_off;
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if (brw->clip.vp_bo == NULL)
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return;
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drm_intel_bo_map(brw->clip.vp_bo, GL_FALSE);
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vp = brw->clip.vp_bo->virtual;
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vp_off = brw->clip.vp_bo->offset;
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state_out(name, vp, vp_off, 0, "xmin = %f\n", vp->xmin);
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state_out(name, vp, vp_off, 1, "xmax = %f\n", vp->xmax);
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state_out(name, vp, vp_off, 2, "ymin = %f\n", vp->ymin);
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state_out(name, vp, vp_off, 3, "ymax = %f\n", vp->ymax);
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drm_intel_bo_unmap(brw->clip.vp_bo);
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}
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static void dump_cc_viewport_state(struct brw_context *brw)
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{
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const char *name = "CC VP";
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struct brw_cc_viewport *vp;
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uint32_t vp_off;
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if (brw->cc.vp_bo == NULL)
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return;
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drm_intel_bo_map(brw->cc.vp_bo, GL_FALSE);
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vp = brw->cc.vp_bo->virtual;
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vp_off = brw->cc.vp_bo->offset;
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state_out(name, vp, vp_off, 0, "min_depth = %f\n", vp->min_depth);
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state_out(name, vp, vp_off, 1, "max_depth = %f\n", vp->max_depth);
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drm_intel_bo_unmap(brw->cc.vp_bo);
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}
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static void dump_depth_stencil_state(struct brw_context *brw)
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{
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const char *name = "DEPTH STENCIL";
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struct gen6_depth_stencil_state *ds;
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uint32_t ds_off;
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if (brw->cc.depth_stencil_state_bo == NULL)
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return;
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drm_intel_bo_map(brw->cc.depth_stencil_state_bo, GL_FALSE);
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ds = brw->cc.depth_stencil_state_bo->virtual;
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ds_off = brw->cc.depth_stencil_state_bo->offset;
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state_out(name, ds, ds_off, 0, "stencil %sable, func %d, write %sable\n",
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ds->ds0.stencil_enable ? "en" : "dis",
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ds->ds0.stencil_func,
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ds->ds0.stencil_write_enable ? "en" : "dis");
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state_out(name, ds, ds_off, 1, "stencil test mask 0x%x, write mask 0x%x\n",
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ds->ds1.stencil_test_mask, ds->ds1.stencil_write_mask);
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state_out(name, ds, ds_off, 2, "depth test %sable, func %d, write %sable\n",
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ds->ds2.depth_test_enable ? "en" : "dis",
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ds->ds2.depth_test_func,
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ds->ds2.depth_write_enable ? "en" : "dis");
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drm_intel_bo_unmap(brw->cc.depth_stencil_state_bo);
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}
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static void dump_cc_state(struct brw_context *brw)
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{
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const char *name = "CC";
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struct gen6_color_calc_state *cc;
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uint32_t cc_off;
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if (brw->cc.state_bo == NULL)
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return;
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drm_intel_bo_map(brw->cc.state_bo, GL_FALSE);
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cc = brw->cc.state_bo->virtual;
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cc_off = brw->cc.state_bo->offset;
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state_out(name, cc, cc_off, 0, "alpha test format %s, round disable %d, stencil ref %d,"
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"bf stencil ref %d\n",
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cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
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cc->cc0.round_disable,
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cc->cc0.stencil_ref,
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cc->cc0.bf_stencil_ref);
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state_out(name, cc, cc_off, 1, "\n");
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state_out(name, cc, cc_off, 2, "constant red %f\n", cc->constant_r);
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state_out(name, cc, cc_off, 3, "constant green %f\n", cc->constant_g);
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state_out(name, cc, cc_off, 4, "constant blue %f\n", cc->constant_b);
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state_out(name, cc, cc_off, 5, "constant alpha %f\n", cc->constant_a);
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drm_intel_bo_unmap(brw->cc.state_bo);
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}
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static void dump_blend_state(struct brw_context *brw)
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{
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const char *name = "BLEND";
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struct gen6_blend_state *blend;
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uint32_t blend_off;
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if (brw->cc.blend_state_bo == NULL)
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return;
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drm_intel_bo_map(brw->cc.blend_state_bo, GL_FALSE);
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blend = brw->cc.blend_state_bo->virtual;
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blend_off = brw->cc.blend_state_bo->offset;
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state_out(name, blend, blend_off, 0, "\n");
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state_out(name, blend, blend_off, 1, "\n");
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drm_intel_bo_unmap(brw->cc.blend_state_bo);
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}
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static void brw_debug_prog(const char *name, drm_intel_bo *prog)
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{
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unsigned int i;
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@ -208,16 +325,29 @@ void brw_debug_batch(struct intel_context *intel)
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state_struct_out("WM bind", brw->wm.bind_bo, 4 * brw->wm.nr_surfaces);
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dump_wm_surface_state(brw);
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state_struct_out("VS", brw->vs.state_bo, sizeof(struct brw_vs_unit_state));
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if (intel->gen < 6)
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state_struct_out("VS", brw->vs.state_bo, sizeof(struct brw_vs_unit_state));
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brw_debug_prog("VS prog", brw->vs.prog_bo);
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state_struct_out("GS", brw->gs.state_bo, sizeof(struct brw_gs_unit_state));
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if (intel->gen < 6)
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state_struct_out("GS", brw->gs.state_bo, sizeof(struct brw_gs_unit_state));
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brw_debug_prog("GS prog", brw->gs.prog_bo);
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state_struct_out("SF", brw->sf.state_bo, sizeof(struct brw_sf_unit_state));
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if (intel->gen < 6) {
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state_struct_out("SF", brw->sf.state_bo, sizeof(struct brw_sf_unit_state));
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brw_debug_prog("SF prog", brw->sf.prog_bo);
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}
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dump_sf_viewport_state(brw);
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brw_debug_prog("SF prog", brw->sf.prog_bo);
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state_struct_out("WM", brw->wm.state_bo, sizeof(struct brw_wm_unit_state));
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if (intel->gen < 6)
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state_struct_out("WM", brw->wm.state_bo, sizeof(struct brw_wm_unit_state));
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brw_debug_prog("WM prog", brw->wm.prog_bo);
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if (intel->gen >= 6) {
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dump_cc_viewport_state(brw);
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dump_clip_viewport_state(brw);
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dump_depth_stencil_state(brw);
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dump_cc_state(brw);
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dump_blend_state(brw);
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}
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}
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