freedreno/ir3: fix bogus register footprint with tess/gs
When we have a tess or gs stage, VS outputs aren't normal varyings, so regid is r63.x.. we shouldn't extend our registerfootprint to 64! Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
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@ -96,6 +96,9 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
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}
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for (i = 0; i < v->outputs_count; i++) {
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/* for ex, VS shaders with tess don't have normal varying outs: */
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if (!VALIDREG(v->outputs[i].regid))
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continue;
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int32_t regid = v->outputs[i].regid + 3;
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if (v->outputs[i].half) {
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if (gpu_id < 500) {
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