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freedreno/ir3: fix bogus register footprint with tess/gs 

When we have a tess or gs stage, VS outputs aren't normal varyings, so
regid is r63.x.. we shouldn't extend our registerfootprint to 64!

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
This commit is contained in:
Rob Clark 2020-03-21 13:13:34 -07:00 committed by Marge Bot
parent 1b4b455739
commit afdb8e3907
1 changed files with 3 additions and 0 deletions
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3
src/freedreno/ir3/ir3_shader.c
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@ -96,6 +96,9 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
}
for (i = 0; i < v->outputs_count; i++) {
/* for ex, VS shaders with tess don't have normal varying outs: */
if (!VALIDREG(v->outputs[i].regid))
continue;
int32_t regid = v->outputs[i].regid + 3;
if (v->outputs[i].half) {
if (gpu_id < 500) {