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isl: Implement isl_surf_init() for gen4-gen9 

This is a big code push. The patch is about 3000 lines.

Function isl_surf_init() calculates the physical layout of a surface.

The implementation is "complete" (but untested) for all 1D, 2D, 3D, and
cube surfaces for gen4 through gen9, except:
    * gen9 1D surfaces
    * gen9 Ys multisampled surfaces
    * auxiliary surfaces (such as hiz, mcs, ccs)
This commit is contained in:
Chad Versace 2015-11-13 16:01:35 -08:00
parent bda43a0f59
commit afdadec77f
14 changed files with 2967 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/vulkan/Makefile.am
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@ -92,7 +92,18 @@ VULKAN_SOURCES = \
anv_wsi.c \
anv_wsi_x11.c \
isl.c \
isl_format_layout.c
isl_format_layout.c \
isl_gen4.c \
isl_gen4.h \
isl_gen6.c \
isl_gen6.h \
isl_gen7.c \
isl_gen7.h \
isl_gen8.c \
isl_gen8.h \
isl_gen9.c \
isl_gen9.h \
$(NULL)
BUILT_SOURCES = \
anv_entrypoints.h \

1032
src/vulkan/isl.c
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File diff suppressed because it is too large Load Diff

568
src/vulkan/isl.h
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@ -24,34 +24,70 @@
/**
* @file
* @brief Intel Surface Layout
*
* Header Layout
* =============
*
* The header is ordered as:
* - forward declarations
* - macros that may be overridden at compile-time for specific gens
* - enums and constants
* - structs and unions
* - functions
*
*
* Surface Units
* =============
*
* Some symbol names have a unit suffix.
*
* - px: logical pixels
* - sa: physical surface samples
* - el: physical surface elements
* - sa_rows: rows of physical surface samples
* - el_rows: rows of physical surface elements
*
* The Broadwell PRM [1] defines a surface element as follows:
*
* An element is defined as a pixel in uncompresed surface formats, and as
* a compression block in compressed surface formats. For
* MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample.
*
* [1]: Broadwell PRM >> Volume 2d: Command Reference: Structures >>
* RENDER_SURFACE_STATE Surface Vertical Alignment (p325)
*/
#pragma once
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include "util/macros.h"
#ifdef __cplusplus
extern "C" {
#endif
struct brw_device_info;
#ifndef ISL_DEV_GEN
/**
* WARNING: These values differ from the hardware enum values, which are
* unstable across hardware generations.
* @brief Get the hardware generation of isl_device.
*
* Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
* clearly distinguish it from Yf and Ys.
* You can define this as a compile-time constant in the CFLAGS. For example,
* `gcc -DISL_DEV_GEN(dev)=9 ...`.
*/
enum isl_tiling {
ISL_TILING_LINEAR,
ISL_TILING_W,
ISL_TILING_X,
ISL_TILING_Y0, /**< Legacy Y tiling */
ISL_TILING_Yf,
ISL_TILING_Ys,
};
#define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
#endif
#ifndef ISL_DEV_USE_SEPARATE_STENCIL
/**
* You can define this as a compile-time constant in the CFLAGS. For example,
* `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
*/
#define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
#endif
/**
* Hardware enumeration SURFACE_FORMAT.
@ -286,6 +322,9 @@ enum isl_format {
ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
};
/**
* Numerical base type for channels of isl_format.
*/
enum isl_base_type {
ISL_VOID,
ISL_RAW,
@ -301,6 +340,9 @@ enum isl_base_type {
ISL_SSCALED,
};
/**
* Colorspace of isl_format.
*/
enum isl_colorspace {
ISL_COLORSPACE_NONE = 0,
ISL_COLORSPACE_LINEAR,
@ -309,7 +351,7 @@ enum isl_colorspace {
};
/**
* Texture compression mode
* Texture compression mode of isl_format.
*/
enum isl_txc {
ISL_TXC_NONE = 0,
@ -324,19 +366,203 @@ enum isl_txc {
ISL_TXC_ETC2,
};
/**
* @brief Hardware tile mode
*
* WARNING: These values differ from the hardware enum values, which are
* unstable across hardware generations.
*
* Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
* clearly distinguish it from Yf and Ys.
*/
enum isl_tiling {
ISL_TILING_LINEAR = 0,
ISL_TILING_W,
ISL_TILING_X,
ISL_TILING_Y0, /**< Legacy Y tiling */
ISL_TILING_Yf,
ISL_TILING_Ys,
};
/**
* @defgroup Tiling Flags
* @{
*/
typedef uint32_t isl_tiling_flags_t;
#define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
#define ISL_TILING_W_BIT (1u << ISL_TILING_W)
#define ISL_TILING_X_BIT (1u << ISL_TILING_X)
#define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
#define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
#define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
#define ISL_TILING_ANY_MASK (~0u)
#define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
/** Any Y tiling, including legacy Y tiling. */
#define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
ISL_TILING_Yf_BIT | \
ISL_TILING_Ys_BIT)
/** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
#define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
ISL_TILING_Ys_BIT)
/** @} */
/**
* @brief Logical dimension of surface.
*
* Note: There is no dimension for cube map surfaces. ISL interprets cube maps
* as 2D array surfaces.
*/
enum isl_surf_dim {
ISL_SURF_DIM_1D,
ISL_SURF_DIM_2D,
ISL_SURF_DIM_3D,
};
/**
* @brief Physical layout of the surface's dimensions.
*/
enum isl_dim_layout {
/**
* For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
* 6.17.3: 2D Surfaces.
*
* On many gens, 1D surfaces share the same layout as 2D surfaces. From
* the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
*
* One-dimensional surfaces are identical to 2D surfaces with height of
* one.
*/
ISL_DIM_LAYOUT_GEN4_2D,
/**
* For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
* 6.17.5: 3D Surfaces.
*/
ISL_DIM_LAYOUT_GEN4_3D,
/**
* For details, see the Skylake BSpec >> Memory Views >> Common Surface
* Formats >> Surface Layout and Tiling >> » 1D Surfaces.
*/
ISL_DIM_LAYOUT_GEN9_1D,
};
/* TODO(chadv): Explain */
enum isl_array_pitch_span {
ISL_ARRAY_PITCH_SPAN_FULL,
ISL_ARRAY_PITCH_SPAN_COMPACT,
};
/**
* @defgroup Surface Usage
* @{
*/
typedef uint64_t isl_surf_usage_flags_t;
#define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
#define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
#define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
#define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
#define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
#define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
#define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
#define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
#define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
#define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
#define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
#define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
/** @} */
/**
* @brief Multisample Format
*/
enum isl_msaa_layout {
/**
* @brief Suface is single-sampled.
*/
ISL_MSAA_LAYOUT_NONE,
/**
* @brief [SNB+] Interleaved Multisample Format
*
* In this format, multiple samples are interleaved into each cacheline.
* In other words, the sample index is swizzled into the low 6 bits of the
* surface's virtual address space.
*
* For example, suppose the surface is legacy Y tiled, is 4x multisampled,
* and its pixel format is 32bpp. Then the first cacheline is arranged
* thus:
*
* (0,0,0) (0,1,0) (0,0,1) (1,0,1)
* (1,0,0) (1,1,0) (0,1,1) (1,1,1)
*
* (0,0,2) (1,0,2) (0,0,3) (1,0,3)
* (0,1,2) (1,1,2) (0,1,3) (1,1,3)
*
* The hardware docs refer to this format with multiple terms. In
* Sandybridge, this is the only multisample format; so no term is used.
* The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
* Multisample Surface). Later hardware docs additionally refer to this
* format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
* color surfaces).
*
* See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
* Surface Behavior".
*
* See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
* Multisampled Surfaces".
*/
ISL_MSAA_LAYOUT_INTERLEAVED,
/**
* @brief [IVB+] Array Multisample Format
*
* In this format, the surface's physical layout resembles that of a
* 2D array surface.
*
* Suppose the multisample surface's logical extent is (w, h) and its
* sample count is N. Then surface's physical extent is the same as
* a singlesample 2D surface whose logical extent is (w, h) and array
* length is N. Array slice `i` contains the pixel values for sample
* index `i`.
*
* The Ivybridge docs refer to surfaces in this format as UMS
* (Uncompressed Multsample Layout) and CMS (Compressed Multisample
* Surface). The Broadwell docs additionally refer to this format as
* MSFMT_MSS (MSS=Multisample Surface Storage).
*
* See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
* Multisample Surfaces".
*
* See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
* Multisample Surfaces".
*/
ISL_MSAA_LAYOUT_ARRAY,
};
struct isl_device {
const struct brw_device_info *info;
bool use_separate_stencil;
};
struct isl_extent2d {
uint32_t width;
uint32_t height;
union { uint32_t w, width; };
union { uint32_t h, height; };
};
struct isl_extent3d {
uint32_t width;
uint32_t height;
uint32_t depth;
union { uint32_t w, width; };
union { uint32_t h, height; };
union { uint32_t d, depth; };
};
struct isl_extent4d {
union { uint32_t w, width; };
union { uint32_t h, height; };
union { uint32_t d, depth; };
union { uint32_t a, array_len; };
};
struct isl_channel_layout {
@ -367,17 +593,319 @@ struct isl_format_layout {
enum isl_txc txc;
};
struct isl_tile_info {
enum isl_tiling tiling;
uint32_t width; /**< in bytes */
uint32_t height; /**< in rows of memory */
uint32_t size; /**< in bytes */
};
/**
* @brief Input to surface initialization
*
* @invariant width >= 1
* @invariant height >= 1
* @invariant depth >= 1
* @invariant levels >= 1
* @invariant samples >= 1
* @invariant array_len >= 1
*
* @invariant if 1D then height == 1 and depth == 1 and samples == 1
* @invariant if 2D then depth == 1
* @invariant if 3D then array_len == 1 and samples == 1
*/
struct isl_surf_init_info {
enum isl_surf_dim dim;
enum isl_format format;
uint32_t width;
uint32_t height;
uint32_t depth;
uint32_t levels;
uint32_t array_len;
uint32_t samples;
/** Lower bound for isl_surf::alignment, in bytes. */
uint32_t min_alignment;
/** Lower bound for isl_surf::pitch, in bytes. */
uint32_t min_pitch;
isl_surf_usage_flags_t usage;
/** Flags that alter how ISL selects isl_surf::tiling. */
isl_tiling_flags_t tiling_flags;
};
struct isl_surf {
enum isl_surf_dim dim;
enum isl_dim_layout dim_layout;
enum isl_msaa_layout msaa_layout;
enum isl_tiling tiling;
enum isl_format format;
/**
* Alignment of the upper-left sample of each LOD, in units of surface
* elements.
*/
struct isl_extent3d lod_alignment_el;
/**
* Logical extent of the surface's base level, in units of pixels. This is
* identical to the extent defined in isl_surf_init_info.
*/
struct isl_extent4d logical_level0_px;
/**
* Physical extent of the surface's base level, in units of pixels.
*
* Consider isl_dim_layout as an operator that transforms a logical surface
* layout to a physical surface layout. Then
*
* logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
* isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
*/
struct isl_extent4d phys_level0_sa;
uint32_t levels;
uint32_t samples;
/** Total size of the surface, in bytes. */
uint32_t size;
/** Required alignment for the surface's base address. */
uint32_t alignment;
/**
* Pitch between vertically adjacent samples, in bytes.
*/
uint32_t row_pitch;
/**
* Pitch between physical array slices, in rows of surface elements.
*/
uint32_t array_pitch_el_rows;
enum isl_array_pitch_span array_pitch_span;
/** Copy of isl_surf_init_info::usage. */
isl_surf_usage_flags_t usage;
};
extern const struct isl_format_layout isl_format_layouts[];
void
isl_device_init(struct isl_device *dev,
const struct brw_device_info *info);
static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)
{
return &isl_format_layouts[fmt];
}
bool
isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
static inline bool
isl_format_is_compressed(enum isl_format fmt)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
return fmtl->txc != ISL_TXC_NONE;
}
static inline bool
isl_format_has_bc_compression(enum isl_format fmt)
{
switch (isl_format_get_layout(fmt)->txc) {
case ISL_TXC_DXT1:
case ISL_TXC_DXT3:
case ISL_TXC_DXT5:
return true;
case ISL_TXC_NONE:
case ISL_TXC_FXT1:
case ISL_TXC_RGTC1:
case ISL_TXC_RGTC2:
case ISL_TXC_BPTC:
case ISL_TXC_ETC1:
case ISL_TXC_ETC2:
return false;
}
unreachable("bad texture compression mode");
return false;
}
static inline bool
isl_format_is_yuv(enum isl_format fmt)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
return fmtl->colorspace == ISL_COLORSPACE_YUV;
}
static inline bool
isl_format_block_is_1x1x1(enum isl_format fmt)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
}
static inline bool
isl_tiling_is_std_y(enum isl_tiling tiling)
{
return (1u << tiling) & ISL_TILING_STD_Y_MASK;
}
bool
isl_tiling_get_info(const struct isl_device *dev,
enum isl_tiling tiling,
uint32_t format_block_size,
struct isl_tile_info *info);
void
isl_tiling_get_extent(const struct isl_device *dev,
enum isl_tiling tiling,
uint32_t cpp,
uint32_t format_block_size,
struct isl_extent2d *e);
bool
isl_surf_choose_tiling(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling *tiling);
extern const struct isl_format_layout isl_format_layouts[];
static inline bool
isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
{
return usage & ISL_SURF_USAGE_DISPLAY_BIT;
}
static inline bool
isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
{
return usage & ISL_SURF_USAGE_DEPTH_BIT;
}
static inline bool
isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
{
return usage & ISL_SURF_USAGE_STENCIL_BIT;
}
static inline bool
isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
{
return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
(usage & ISL_SURF_USAGE_STENCIL_BIT);
}
static inline bool
isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
{
return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
}
static inline bool
isl_surf_info_is_z16(const struct isl_surf_init_info *info)
{
return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
(info->format == ISL_FORMAT_R16_UNORM);
}
static inline bool
isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
{
return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
(info->format == ISL_FORMAT_R32_FLOAT);
}
static inline struct isl_extent2d
isl_extent2d(uint32_t width, uint32_t height)
{
return (struct isl_extent2d) { .w = width, .h = height };
}
static inline struct isl_extent3d
isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
{
return (struct isl_extent3d) { .w = width, .h = height, .d = depth };
}
static inline struct isl_extent4d
isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
uint32_t array_len)
{
return (struct isl_extent4d) {
.w = width,
.h = height,
.d = depth,
.a = array_len,
};
}
#define isl_surf_init(dev, surf, ...) \
isl_surf_init_s((dev), (surf), \
&(struct isl_surf_init_info) { __VA_ARGS__ });
bool
isl_surf_init_s(const struct isl_device *dev,
struct isl_surf *surf,
const struct isl_surf_init_info *restrict info);
/**
* Alignment of the upper-left sample of each LOD, in units of surface
* elements.
*/
static inline struct isl_extent3d
isl_surf_get_lod_alignment_el(const struct isl_surf *surf)
{
return surf->lod_alignment_el;
}
/**
* Alignment of the upper-left sample of each LOD, in units of surface
* samples.
*/
static inline struct isl_extent3d
isl_surf_get_lod_alignment_sa(const struct isl_surf *surf)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
return (struct isl_extent3d) {
.w = fmtl->bw * surf->lod_alignment_el.w,
.h = fmtl->bh * surf->lod_alignment_el.h,
.d = fmtl->bd * surf->lod_alignment_el.d,
};
}
/**
* Pitch between physical array slices, in rows of surface elements.
*/
static inline uint32_t
isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
{
return surf->array_pitch_el_rows;
}
/**
* Pitch between physical array slices, in rows of surface samples.
*/
static inline uint32_t
isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
}
/**
* Pitch between physical array slices, in bytes.
*/
static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf *surf)
{
return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
}
#ifdef __cplusplus
}

74
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@ -0,0 +1,74 @@
/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "isl_gen4.h"
#include "isl_priv.h"
bool
gen4_choose_msaa_layout(const struct isl_device *dev,
const struct isl_surf_init_info *info,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout)
{
/* Gen4 and Gen5 do not support MSAA */
assert(info->samples >= 1);
*msaa_layout = ISL_MSAA_LAYOUT_NONE;
return true;
}
void
gen4_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el)
{
assert(info->samples == 1);
assert(msaa_layout == ISL_MSAA_LAYOUT_NONE);
assert(!isl_tiling_is_std_y(tiling));
/* Note that neither the surface's horizontal nor vertical image alignment
* is programmable on gen4 nor gen5.
*
* From the G35 PRM (2008-01), Volume 1 Graphics Core, Section 6.17.3.4
* Alignment Unit Size:
*
* Note that the compressed formats are padded to a full compression
* cell.
*
* +------------------------+--------+--------+
* | format | halign | valign |
* +------------------------+--------+--------+
* | YUV 4:2:2 formats | 4 | 2 |
* | uncompressed formats | 4 | 2 |
* +------------------------+--------+--------+
*/
if (isl_format_is_compressed(info->format)) {
*lod_align_el = isl_extent3d(1, 1, 1);
return;
}
*lod_align_el = isl_extent3d(4, 2, 1);
}

47
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@ -0,0 +1,47 @@
/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#pragma once
#include "isl_priv.h"
#ifdef __cplusplus
extern "C" {
#endif
bool
gen4_choose_msaa_layout(const struct isl_device *dev,
const struct isl_surf_init_info *info,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout);
void
gen4_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el);
#ifdef __cplusplus
}
#endif

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "isl_gen6.h"
#include "isl_priv.h"
bool
gen6_choose_msaa_layout(const struct isl_device *dev,
const struct isl_surf_init_info *info,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
assert(ISL_DEV_GEN(dev) == 6);
assert(info->samples >= 1);
if (info->samples == 1) {
*msaa_layout = ISL_MSAA_LAYOUT_NONE;
return false;
}
/* From the Sandybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Surface
* Format:
*
* If Number of Multisamples is set to a value other than
* MULTISAMPLECOUNT_1, this field cannot be set to the following
* formats:
*
* - any format with greater than 64 bits per element
* - any compressed texture format (BC*)
* - any YCRCB* format
*/
if (fmtl->bs > 8)
return false;
if (isl_format_is_compressed(info->format))
return false;
if (isl_format_is_yuv(info->format))
return false;
/* From the Sandybridge PRM, Volume 4 Part 1 p85, SURFACE_STATE, Number of
* Multisamples:
*
* If this field is any value other than MULTISAMPLECOUNT_1 the
* following restrictions apply:
*
* - the Surface Type must be SURFTYPE_2D
* - [...]
*/
if (info->dim != ISL_SURF_DIM_2D)
return false;
/* More obvious restrictions */
if (isl_surf_usage_is_display(info->usage))
return false;
if (tiling == ISL_TILING_LINEAR)
return false;
if (info->levels > 1)
return false;
*msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
return true;
}
void
gen6_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el)
{
/* Note that the surface's horizontal image alignment is not programmable
* on Sandybridge.
*
* From the Sandybridge PRM (2011-05), Volume 1, Part 1, Section 7.18.3.4
* Alignment Unit Size:
*
* Note that the compressed formats are padded to a full compression cell.
*
* +------------------------+--------+--------+
* | format | halign | valign |
* +------------------------+--------+--------+
* | YUV 4:2:2 formats | 4 | * |
* | uncompressed formats | 4 | * |
* +------------------------+--------+--------+
*
* * For these formats, the vertical alignment factor “j” is determined
* as follows:
* - j = 4 for any depth buffer
* - j = 2 for separate stencil buffer
* - j = 4 for any render target surface is multisampled (4x)
* - j = 2 for all other render target surface
*
* From the Sandrybridge PRM (2011-05), Volume 4, Part 1, Section 2.11.2
* SURFACE_STATE, Surface Vertical Alignment:
*
* - This field must be set to VALIGN_2 if the Surface Format is 96 bits
* per element (BPE).
*
* - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
* (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
* (0x190)
*/
if (isl_format_is_compressed(info->format)) {
*lod_align_el = isl_extent3d(1, 1, 1);
return;
}
if (isl_format_is_yuv(info->format)) {
*lod_align_el = isl_extent3d(4, 2, 1);
return;
}
if (info->samples > 1) {
*lod_align_el = isl_extent3d(4, 4, 1);
return;
}
if (isl_surf_usage_is_depth_or_stencil(info->usage) &&
!ISL_DEV_USE_SEPARATE_STENCIL(dev)) {
/* interleaved depthstencil buffer */
*lod_align_el = isl_extent3d(4, 4, 1);
return;
}
if (isl_surf_usage_is_depth(info->usage)) {
/* separate depth buffer */
*lod_align_el = isl_extent3d(4, 4, 1);
return;
}
if (isl_surf_usage_is_stencil(info->usage)) {
/* separate stencil buffer */
*lod_align_el = isl_extent3d(4, 2, 1);
return;
}
*lod_align_el = isl_extent3d(4, 2, 1);
}

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#pragma once
#include "isl_priv.h"
#ifdef __cplusplus
extern "C" {
#endif
bool
gen6_choose_msaa_layout(const struct isl_device *dev,
const struct isl_surf_init_info *info,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout);
void
gen6_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el);
#ifdef __cplusplus
}
#endif

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "isl_gen7.h"
#include "isl_priv.h"
bool
gen7_choose_msaa_layout(const struct isl_device *dev,
const struct isl_surf_init_info *info,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
bool require_array = false;
bool require_interleaved = false;
assert(ISL_DEV_GEN(dev) == 7);
assert(info->samples >= 1);
if (info->samples == 1) {
*msaa_layout = ISL_MSAA_LAYOUT_NONE;
return true;
}
/* From the Ivybridge PRM, Volume 4 Part 1 p63, SURFACE_STATE, Surface
* Format:
*
* If Number of Multisamples is set to a value other than
* MULTISAMPLECOUNT_1, this field cannot be set to the following
* formats: any format with greater than 64 bits per element, any
* compressed texture format (BC*), and any YCRCB* format.
*/
if (fmtl->bs > 8)
return false;
if (isl_format_is_compressed(info->format))
return false;
if (isl_format_is_yuv(info->format))
return false;
/* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
* Multisamples:
*
* - If this field is any value other than MULTISAMPLECOUNT_1, the
* Surface Type must be SURFTYPE_2D.
*
* - If this field is any value other than MULTISAMPLECOUNT_1, Surface
* Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero
*/
if (info->dim != ISL_SURF_DIM_2D)
return false;
if (info->levels > 1)
return false;
/* The Ivyrbridge PRM insists twice that signed integer formats cannot be
* multisampled.
*
* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
* Multisamples:
*
* - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when
* all RT channels are not written.
*
* And errata from the Ivybridge PRM, Volume 4 Part 1 p77,
* RENDER_SURFACE_STATE, MCS Enable:
*
* This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs
* when all RT channels are not written.
*
* Note that the above SINT restrictions apply only to *MSRTs* (that is,
* *multisampled* render targets). The restrictions seem to permit an MCS
* if the render target is singlesampled.
*/
if (isl_format_has_sint_channel(info->format))
return false;
/* More obvious restrictions */
if (isl_surf_usage_is_display(info->usage))
return false;
if (tiling == ISL_TILING_LINEAR)
return false;
/* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
* Suface Storage Format:
*
* +---------------------+----------------------------------------------------------------+
* | MSFMT_MSS | Multsampled surface was/is rendered as a render target |
* | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer |
* +---------------------+----------------------------------------------------------------+
*
* In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and
* MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED.
*/
if (isl_surf_usage_is_depth_or_stencil(info->usage))
require_interleaved = true;
/* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
* Suface Storage Format:
*
* If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
* is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
* field must be set to MSFMT_MSS.
*/
if (info->samples == 8 && info->width == 8192)
require_array = true;
/* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
* Suface Storage Format:
*
* If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
* ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number
* of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is
* > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.
*/
if ((info->samples == 8 && info->height > 4194304u) ||
(info->samples == 4 && info->height > 8388608u))
require_interleaved = true;
/* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
* Suface Storage Format:
*
* This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is
* one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
* R24_UNORM_X8_TYPELESS.
*/
if (info->format == ISL_FORMAT_I24X8_UNORM ||
info->format == ISL_FORMAT_L24X8_UNORM ||
info->format == ISL_FORMAT_A24X8_UNORM ||
info->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS)
require_interleaved = true;
if (require_array && require_interleaved)
return false;
if (require_interleaved) {
*msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
return true;
}
/* Default to the array layout because it permits multisample
* compression.
*/
*msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
return true;
}
static bool
gen7_format_needs_valign2(const struct isl_device *dev,
enum isl_format format)
{
/* This workaround applies only to gen7 */
if (ISL_DEV_GEN(dev) > 7)
return false;
/* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
* RENDER_SURFACE_STATE Surface Vertical Alignment:
*
* - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
* (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
* (0x190)
*
* - VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
*/
return isl_format_is_yuv(format) ||
format == ISL_FORMAT_R32G32B32_FLOAT;
}
void
gen7_filter_tiling(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
isl_tiling_flags_t *flags)
{
/* IVB+ requires separate stencil */
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
/* Clear flags unsupported on this hardware */
if (ISL_DEV_GEN(dev) < 9) {
*flags &= ~ISL_TILING_Yf_BIT;
*flags &= ~ISL_TILING_Ys_BIT;
}
/* And... clear the Yf and Ys bits anyway because Anvil doesn't support
* them yet.
*/
*flags &= ~ISL_TILING_Yf_BIT; /* FINISHME[SKL]: Support Yf */
*flags &= ~ISL_TILING_Ys_BIT; /* FINISHME[SKL]: Support Ys */
if (isl_surf_usage_is_depth(info->usage)) {
/* Depth requires Y. */
*flags &= ISL_TILING_ANY_Y_MASK;
}
/* Separate stencil requires W tiling, and W tiling requires separate
* stencil.
*/
if (isl_surf_usage_is_stencil(info->usage)) {
*flags &= ISL_TILING_W_BIT;
} else {
*flags &= ~ISL_TILING_W_BIT;
}
if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
isl_finishme("%s:%s: handle rotated display surfaces",
__FILE__, __func__);
}
if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
isl_finishme("%s:%s: handle flipped display surfaces",
__FILE__, __func__);
}
if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
/* Before Skylake, the display engine does not accept Y */
/* FINISHME[SKL]: Y tiling for display surfaces */
*flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
}
if (info->samples > 1) {
/* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled
* Surface:
*
* For multisample render targets, this field must be 1 (true). MSRTs
* can only be tiled.
*
* Multisample surfaces never require X tiling, and Y tiling generally
* performs better than X. So choose Y. (Unless it's stencil, then it
* must be W).
*/
*flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT);
}
/* For 1D surfaces, use linear when possible. 1D surfaces (array and
* non-array) do not benefit from tiling. In fact, it leads to less
* efficient use of memory due to tile alignment.
*/
if (info->dim == ISL_SURF_DIM_1D && (*flags & ISL_TILING_LINEAR_BIT)) {
*flags = ISL_TILING_LINEAR_BIT;
}
/* workaround */
if (ISL_DEV_GEN(dev) == 7 &&
gen7_format_needs_valign2(dev, info->format) &&
(info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
info->samples == 1) {
/* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1,
* SURFACE_STATE Surface Vertical Alignment:
*
* This field must be set to VALIGN_4 for all tiled Y Render Target
* surfaces.
*/
*flags &= ~ISL_TILING_Y0_BIT;
}
}
/**
* Choose horizontal LOD alignment, in units of surface elements.
*/
static uint32_t
gen7_choose_halign_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info)
{
if (isl_format_is_compressed(info->format))
return 1;
/* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
* RENDER_SURFACE_STATE Surface Hoizontal Alignment:
*
* - This field is intended to be set to HALIGN_8 only if the surface
* was rendered as a depth buffer with Z16 format or a stencil buffer,
* since these surfaces support only alignment of 8. Use of HALIGN_8
* for other surfaces is supported, but uses more memory.
*/
if (isl_surf_info_is_z16(info) ||
isl_surf_usage_is_stencil(info->usage))
return 8;
return 4;
}
/**
* Choose vertical LOD alignment, in units of surface elements.
*/
static uint32_t
gen7_choose_valign_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling)
{
bool require_valign2 = false;
bool require_valign4 = false;
if (isl_format_is_compressed(info->format))
return 1;
if (gen7_format_needs_valign2(dev, info->format))
require_valign2 = true;
/* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1:
* RENDER_SURFACE_STATE Surface Vertical Alignment:
*
* - This field is intended to be set to VALIGN_4 if the surface was
* rendered as a depth buffer, for a multisampled (4x) render target,
* or for a multisampled (8x) render target, since these surfaces
* support only alignment of 4. Use of VALIGN_4 for other surfaces is
* supported, but uses more memory. This field must be set to
* VALIGN_4 for all tiled Y Render Target surfaces.
*
*/
if (isl_surf_usage_is_depth(info->usage) ||
info->samples > 1 ||
tiling == ISL_TILING_Y0) {
require_valign4 = true;
}
if (isl_surf_usage_is_stencil(info->usage)) {
/* The Ivybridge PRM states that the stencil buffer's vertical alignment
* is 8 [Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.4 Alignment
* Unit Size]. However, valign=8 is outside the set of valid values of
* RENDER_SURFACE_STATE.SurfaceVerticalAlignment, which is VALIGN_2
* (0x0) and VALIGN_4 (0x1).
*
* The PRM is generally confused about the width, height, and alignment
* of the stencil buffer; and this confusion appears elsewhere. For
* example, the following PRM text effectively converts the stencil
* buffer's 8-pixel alignment to a 4-pixel alignment [Ivybridge PRM,
* Volume 1, Part 1, Section
* 6.18.4.2 Base Address and LOD Calculation]:
*
* For separate stencil buffer, the width must be mutiplied by 2 and
* height divided by 2 as follows:
*
* w_L = 2*i*ceil(W_L/i)
* h_L = 1/2*j*ceil(H_L/j)
*
* The root of the confusion is that, in W tiling, each pair of rows is
* interleaved into one.
*
* FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's API
* is more polished.
*/
require_valign4 = true;
}
assert(!require_valign2 || !require_valign4);
if (require_valign4)
return 4;
/* Prefer VALIGN_2 because it conserves memory. */
return 2;
}
void
gen7_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el)
{
/* IVB+ does not support combined depthstencil. */
assert(!isl_surf_usage_is_depth_and_stencil(info->usage));
*lod_align_el = (struct isl_extent3d) {
.w = gen7_choose_halign_el(dev, info),
.h = gen7_choose_valign_el(dev, info, tiling),
.d = 1,
};
}

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#pragma once
#include "isl_priv.h"
#ifdef __cplusplus
extern "C" {
#endif
void
gen7_filter_tiling(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
isl_tiling_flags_t *flags);
bool
gen7_choose_msaa_layout(const struct isl_device *dev,
const struct isl_surf_init_info *info,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout);
void
gen7_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el);
#ifdef __cplusplus
}
#endif

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "isl_gen8.h"
#include "isl_priv.h"
bool
gen8_choose_msaa_layout(const struct isl_device *dev,
const struct isl_surf_init_info *info,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout)
{
bool require_array = false;
bool require_interleaved = false;
assert(info->samples >= 1);
if (info->samples == 1) {
*msaa_layout = ISL_MSAA_LAYOUT_NONE;
return true;
}
/* From the Broadwell PRM >> Volume2d: Command Structures >>
* RENDER_SURFACE_STATE Tile Mode:
*
* - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
* must be YMAJOR.
*
* As usual, though, stencil is special.
*/
if (!isl_tiling_is_std_y(tiling) && !isl_surf_usage_is_stencil(info->usage))
return false;
/* From the Broadwell PRM >> Volume2d: Command Structures >>
* RENDER_SURFACE_STATE Multisampled Surface Storage Format:
*
* All multisampled render target surfaces must have this field set to
* MSFMT_MSS
*/
if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
require_array = true;
/* From the Broadwell PRM >> Volume2d: Command Structures >>
* RENDER_SURFACE_STATE Number of Multisamples:
*
* - If this field is any value other than MULTISAMPLECOUNT_1, the
* Surface Type must be SURFTYPE_2D This field must be set to
* MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface
* or Render Target surface.
*
* - If this field is any value other than MULTISAMPLECOUNT_1, Surface
* Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero.
*/
if (info->dim != ISL_SURF_DIM_2D)
return false;
if (info->levels > 1)
return false;
/* More obvious restrictions */
if (isl_surf_usage_is_display(info->usage))
return false;
if (isl_format_is_compressed(info->format))
return false;
if (isl_format_is_yuv(info->format))
return false;
if (isl_surf_usage_is_depth_or_stencil(info->usage))
require_interleaved = true;
if (require_array && require_interleaved)
return false;
if (require_interleaved) {
*msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
return true;
}
*msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
return true;
}
/**
* Choose horizontal LOD alignment, in units of surface elements.
*/
static uint32_t
gen8_choose_halign_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info)
{
if (isl_format_is_compressed(info->format))
return 1;
/* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
* RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
*
* - This field is intended to be set to HALIGN_8 only if the surface
* was rendered as a depth buffer with Z16 format or a stencil buffer.
* In this case it must be set to HALIGN_8 since these surfaces
* support only alignment of 8. [...]
*/
if (isl_surf_info_is_z16(info))
return 8;
if (isl_surf_usage_is_stencil(info->usage))
return 8;
/* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
* RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
*
* [...] For Z32 formats it must be set to HALIGN_4.
*/
if (isl_surf_usage_is_depth(info->usage))
return 4;
if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
/* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
* RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
*
* - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
* HALIGN 16 must be used.
*
* This case handles color surfaces that may own an auxiliary MCS, CCS_D,
* or CCS_E. Depth buffers, including those that own an auxiliary HiZ
* surface, are handled above and do not require HALIGN_16.
*/
assert(!isl_surf_usage_is_depth(info->usage));
return 16;
}
/* XXX(chadv): I believe the hardware requires each image to be
* cache-aligned. If that's true, then defaulting to halign=4 is wrong for
* many formats. Depending on the format's block size, we may need to
* increase halign to 8.
*/
return 4;
}
/**
* Choose vertical LOD alignment, in units of surface elements.
*/
static uint32_t
gen8_choose_valign_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info)
{
/* From the Broadwell PRM > Volume 2d: Command Reference: Structures
* > RENDER_SURFACE_STATE Surface Vertical Alignment (p325):
*
* - For Sampling Engine and Render Target Surfaces: This field
* specifies the vertical alignment requirement in elements for the
* surface. [...] An element is defined as a pixel in uncompresed
* surface formats, and as a compression block in compressed surface
* formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
* element is a sample.
*
* - This field is intended to be set to VALIGN_4 if the surface was
* rendered as a depth buffer, for a multisampled (4x) render target,
* or for a multisampled (8x) render target, since these surfaces
* support only alignment of 4. Use of VALIGN_4 for other surfaces is
* supported, but increases memory usage.
*
* - This field is intended to be set to VALIGN_8 only if the surface
* was rendered as a stencil buffer, since stencil buffer surfaces
* support only alignment of 8. If set to VALIGN_8, Surface Format
* must be R8_UINT.
*/
if (isl_format_is_compressed(info->format))
return 1;
if (isl_surf_usage_is_stencil(info->usage))
return 8;
return 4;
}
void
gen8_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el)
{
assert(!isl_tiling_is_std_y(tiling));
/* The below text from the Broadwell PRM provides some insight into the
* hardware's requirements for LOD alignment. From the Broadwell PRM >>
* Volume 5: Memory Views >> Surface Layout >> 2D Surfaces:
*
* These [2D surfaces] must adhere to the following memory organization
* rules:
*
* - For non-compressed texture formats, each mipmap must start on an
* even row within the monolithic rectangular area. For
* 1-texel-high mipmaps, this may require a row of padding below
* the previous mipmap. This restriction does not apply to any
* compressed texture formats; each subsequent (lower-res)
* compressed mipmap is positioned directly below the previous
* mipmap.
*
* - Vertical alignment restrictions vary with memory tiling type:
* 1 DWord for linear, 16-byte (DQWord) for tiled. (Note that tiled
* mipmaps are not required to start at the left edge of a tile
* row.)
*/
*lod_align_el = (struct isl_extent3d) {
.w = gen8_choose_halign_el(dev, info),
.h = gen8_choose_valign_el(dev, info),
.d = 1,
};
}

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#pragma once
#include "isl_priv.h"
#ifdef __cplusplus
extern "C" {
#endif
bool
gen8_choose_msaa_layout(const struct isl_device *dev,
const struct isl_surf_init_info *info,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout);
void
gen8_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el);
#ifdef __cplusplus
}
#endif

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "isl_gen8.h"
#include "isl_gen9.h"
#include "isl_priv.h"
/**
* Calculate the LOD alignment, in units of surface samples, for the standard
* tiling formats Yf and Ys.
*/
static void
gen9_calc_std_lod_alignment_sa(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *align_sa)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
assert(isl_tiling_is_std_y(tiling));
const uint32_t bs = fmtl->bs;
const uint32_t is_Ys = tiling == ISL_TILING_Ys;
switch (info->dim) {
case ISL_SURF_DIM_1D:
/* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
* Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
*/
*align_sa = (struct isl_extent3d) {
.w = 1 << (12 - (ffs(bs) - 1) + (4 * is_Ys)),
.h = 1,
.d = 1,
};
return;
case ISL_SURF_DIM_2D:
/* See the Skylake BSpec > Memory Views > Common Surface Formats >
* Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment
* Requirements.
*/
*align_sa = (struct isl_extent3d) {
.w = 1 << (6 - ((ffs(bs) - 1) / 2) + (4 * is_Ys)),
.h = 1 << (6 - ((ffs(bs) - 0) / 2) + (4 * is_Ys)),
.d = 1,
};
if (is_Ys) {
/* FINISHME(chadv): I don't trust this code. Untested. */
isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__, __func__);
switch (msaa_layout) {
case ISL_MSAA_LAYOUT_NONE:
case ISL_MSAA_LAYOUT_INTERLEAVED:
break;
case ISL_MSAA_LAYOUT_ARRAY:
align_sa->w >>= (ffs(info->samples) - 0) / 2;
align_sa->h >>= (ffs(info->samples) - 1) / 2;
break;
}
}
return;
case ISL_SURF_DIM_3D:
/* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
* Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
*/
*align_sa = (struct isl_extent3d) {
.w = 1 << (4 - ((ffs(bs) + 1) / 3) + (4 * is_Ys)),
.h = 1 << (4 - ((ffs(bs) - 1) / 3) + (2 * is_Ys)),
.d = 1 << (4 - ((ffs(bs) - 0) / 3) + (2 * is_Ys)),
};
return;
}
unreachable("bad isl_surface_type");
}
void
gen9_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el)
{
/* This BSpec text provides some insight into the hardware's alignment
* requirements [Skylake BSpec > Memory Views > Common Surface Formats >
* Surface Layout and Tiling > 2D Surfaces]:
*
* An LOD must be aligned to a cache-line except for some special cases
* related to Planar YUV surfaces. In general, the cache-alignment
* restriction implies there is a minimum height for an LOD of 4 texels.
* So, LODs which are smaller than 4 high are padded.
*
* From the Skylake BSpec, RENDER_SURFACE_STATE Surface Vertical Alignment:
*
* - For Sampling Engine and Render Target Surfaces: This field
* specifies the vertical alignment requirement in elements for the
* surface. [...] An element is defined as a pixel in uncompresed
* surface formats, and as a compression block in compressed surface
* formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
* element is a sample.
*
* - This field is used for 2D, CUBE, and 3D surface alignment when Tiled
* Resource Mode is TRMODE_NONE (Tiled Resource Mode is disabled).
* This field is ignored for 1D surfaces and also when Tiled Resource
* Mode is not TRMODE_NONE (e.g. Tiled Resource Mode is enabled).
*
* See the appropriate Alignment table in the "Surface Layout and
* Tiling" section under Common Surface Formats for the table of
* alignment values for Tiled Resrouces.
*
* - For uncompressed surfaces, the units of "j" are rows of pixels on
* the physical surface. For compressed texture formats, the units of
* "j" are in compression blocks, thus each increment in "j" is equal
* to h pixels, where h is the height of the compression block in
* pixels.
*
* - Valid Values: VALIGN_4, VALIGN_8, VALIGN_16
*
* From the Skylake BSpec, RENDER_SURFACE_STATE Surface Horizontal
* Alignment:
*
* - For uncompressed surfaces, the units of "i" are pixels on the
* physical surface. For compressed texture formats, the units of "i"
* are in compression blocks, thus each increment in "i" is equal to
* w pixels, where w is the width of the compression block in pixels.
*
* - Valid Values: HALIGN_4, HALIGN_8, HALIGN_16
*/
if (isl_tiling_is_std_y(tiling)) {
struct isl_extent3d lod_align_sa;
gen9_calc_std_lod_alignment_sa(dev, info, tiling, msaa_layout,
&lod_align_sa);
*lod_align_el = isl_extent3d_sa_to_el(info->format, lod_align_sa);
return;
}
if (info->dim == ISL_SURF_DIM_1D) {
/* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
* Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
*/
*lod_align_el = isl_extent3d(64, 1, 1);
return;
}
if (isl_format_is_compressed(info->format)) {
/* On Gen9, the meaning of RENDER_SURFACE_STATE's
* SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for
* compressed formats. They now indicate a multiple of the compression
* block. For example, if the compression mode is ETC2 then HALIGN_4
* indicates a horizontal alignment of 16 pixels.
*
* To avoid wasting memory, choose the smallest alignment possible:
* HALIGN_4 and VALIGN_4.
*/
*lod_align_el = isl_extent3d(4, 4, 1);
return;
}
gen8_choose_lod_alignment_el(dev, info, tiling, msaa_layout, lod_align_el);
}

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#pragma once
#include "isl_priv.h"
#ifdef __cplusplus
extern "C" {
#endif
void
gen9_choose_lod_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *lod_align_el);
#ifdef __cplusplus
}
#endif

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/*
* Copyright 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#pragma once
#include <assert.h>
#include "brw_device_info.h"
#include "mesa/main/imports.h"
#include "util/macros.h"
#include "isl.h"
#define isl_finishme(format, ...) \
__isl_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__)
void PRINTFLIKE(3, 4) UNUSED
__isl_finishme(const char *file, int line, const char *fmt, ...);
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
static inline uint32_t
ffs(uint32_t n) {
return __builtin_ffs(n);
}
static inline bool
isl_is_pow2(uintmax_t n)
{
return !(n & (n - 1));
}
/**
* Alignment must be a power of 2.
*/
static inline bool
isl_is_aligned(uintmax_t n, uintmax_t a)
{
assert(isl_is_pow2(a));
return (n & (a - 1)) == 0;
}
/**
* Alignment must be a power of 2.
*/
static inline uintmax_t
isl_align(uintmax_t n, uintmax_t a)
{
assert(isl_is_pow2(a));
return (n + a - 1) & ~(a - 1);
}
static inline uintmax_t
isl_align_npot(uintmax_t n, uintmax_t a)
{
assert(a > 0);
return ((n + a - 1) / a) * a;
}
/**
* Alignment must be a power of 2.
*/
static inline uintmax_t
isl_align_div(uintmax_t n, uintmax_t a)
{
return isl_align(n, a) / a;
}
static inline uintmax_t
isl_align_div_npot(uintmax_t n, uintmax_t a)
{
return isl_align_npot(n, a) / a;
}
/**
* Log base 2, rounding towards zero.
*/
static inline uint32_t
isl_log2u(uint32_t n)
{
assert(n != 0);
return 31 - __builtin_clz(n);
}
static inline uint32_t
isl_minify(uint32_t n, uint32_t levels)
{
if (unlikely(n == 0))
return 0;
else
return MAX(n >> levels, 1);
}
static inline struct isl_extent3d
isl_extent3d_sa_to_el(enum isl_format fmt, struct isl_extent3d extent_sa)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
assert(extent_sa.w % fmtl->bw == 0);
assert(extent_sa.h % fmtl->bh == 0);
assert(extent_sa.d % fmtl->bd == 0);
return (struct isl_extent3d) {
.w = extent_sa.w / fmtl->bw,
.h = extent_sa.h / fmtl->bh,
.d = extent_sa.d / fmtl->bd,
};
}
static inline struct isl_extent3d
isl_extent3d_el_to_sa(enum isl_format fmt, struct isl_extent3d extent_el)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
return (struct isl_extent3d) {
.w = extent_el.w * fmtl->bw,
.h = extent_el.h * fmtl->bh,
.d = extent_el.d * fmtl->bd,
};
}