radv: port polaris vgt vertex reuse workaround.
This ports the VGT_VERTEX_REUSE register settings for Polaris GPUs from radeonsi. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -716,6 +716,21 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
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}
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}
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}
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}
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static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
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struct radv_pipeline *pipeline)
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{
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uint32_t vtx_reuse_depth = 30;
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if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
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return;
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if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
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if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
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vtx_reuse_depth = 14;
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}
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radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
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vtx_reuse_depth);
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}
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static void
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static void
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radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
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radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
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struct radv_pipeline *pipeline)
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struct radv_pipeline *pipeline)
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@ -730,6 +745,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
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radv_emit_vertex_shader(cmd_buffer, pipeline);
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radv_emit_vertex_shader(cmd_buffer, pipeline);
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radv_emit_geometry_shader(cmd_buffer, pipeline);
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radv_emit_geometry_shader(cmd_buffer, pipeline);
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radv_emit_fragment_shader(cmd_buffer, pipeline);
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radv_emit_fragment_shader(cmd_buffer, pipeline);
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polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
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radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
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radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
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pipeline->graphics.prim_restart_enable);
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pipeline->graphics.prim_restart_enable);
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@ -414,7 +414,8 @@ si_emit_config(struct radv_physical_device *physical_device,
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radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
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radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
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S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
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S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
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S_028424_OVERWRITE_COMBINER_WATERMARK(4));
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S_028424_OVERWRITE_COMBINER_WATERMARK(4));
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radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
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if (physical_device->rad_info.family < CHIP_POLARIS10)
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radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
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radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
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radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
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vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
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vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
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