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pan/bi: Rework Valhall register alignment 

Because we lower SPLIT and COLLECT before RA, we need to consider offsets when
determining the dimensions of vectors, in order to align properly. Lowering
COLLECT post-RA would avoid this special case.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>
This commit is contained in:
Alyssa Rosenzweig 2022-05-09 10:18:13 -04:00 committed by Marge Bot
parent 0770e7a90c
commit ad5c84999b
1 changed files with 3 additions and 4 deletions
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7
src/panfrost/bifrost/bi_ra.c
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@ -267,13 +267,12 @@ bi_mark_interference(bi_block *block, struct lcra_state *l, uint8_t *live, uint6
* offset, so we shift right. */
unsigned count = bi_count_write_registers(ins, d);
unsigned offset = ins->dest[d].offset;
uint64_t affinity = bi_make_affinity(preload_live, count, split_file);
uint64_t affinity = bi_make_affinity(preload_live, count, split_file) >> offset;
/* Valhall needs >= 64-bit staging writes to be pair-aligned */
if (aligned_sr && count >= 2)
if (aligned_sr && (count >= 2 || offset))
affinity &= EVEN_BITS_MASK;
l->affinity[node] &= (affinity >> offset);
l->affinity[node] &= affinity;
for (unsigned i = 0; i < node_count; ++i) {
uint8_t r = live[i];