diff --git a/include/pci_ids/iris_pci_ids.h b/include/pci_ids/iris_pci_ids.h index b3bb52c1897..9f460deb350 100644 --- a/include/pci_ids/iris_pci_ids.h +++ b/include/pci_ids/iris_pci_ids.h @@ -221,15 +221,14 @@ CHIPSET(0x4907, sg1, "SG1", "Intel(R) Graphics") CHIPSET(0x4908, dg1, "DG1", "Intel(R) Graphics") CHIPSET(0x4909, dg1, "DG1", "Intel(R) Graphics") -/* Waiting on i915 upstream support */ -#if 0 -CHIPSET(0x4f80, dg2_g10, "DG2", "Intel(R) Graphics") -CHIPSET(0x4f81, dg2_g10, "DG2", "Intel(R) Graphics") -CHIPSET(0x4f82, dg2_g10, "DG2", "Intel(R) Graphics") -CHIPSET(0x4f83, dg2_g10, "DG2", "Intel(R) Graphics") -CHIPSET(0x4f84, dg2_g10, "DG2", "Intel(R) Graphics") -CHIPSET(0x4f87, dg2_g11, "DG2", "Intel(R) Graphics") -CHIPSET(0x4f88, dg2_g11, "DG2", "Intel(R) Graphics") +/* Commented devices are waiting on i915 upstream support */ +/* CHIPSET(0x4f80, dg2_g10, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x4f81, dg2_g10, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x4f82, dg2_g10, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x4f83, dg2_g10, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x4f84, dg2_g10, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x4f87, dg2_g11, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x4f88, dg2_g11, "DG2", "Intel(R) Graphics") */ CHIPSET(0x5690, dg2_g10, "DG2", "Intel(R) Graphics") CHIPSET(0x5691, dg2_g10, "DG2", "Intel(R) Graphics") CHIPSET(0x5692, dg2_g10, "DG2", "Intel(R) Graphics") @@ -238,17 +237,16 @@ CHIPSET(0x5694, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x5695, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x5696, dg2_g12, "DG2", "Intel(R) Graphics") CHIPSET(0x5697, dg2_g12, "DG2", "Intel(R) Graphics") -CHIPSET(0x56a0, dg2_g10, "DG2", "Intel(R) Graphics") -CHIPSET(0x56a1, dg2_g10, "DG2", "Intel(R) Graphics") -CHIPSET(0x56a2, dg2_g10, "DG2", "Intel(R) Graphics") -CHIPSET(0x56a3, dg2_g12, "DG2", "Intel(R) Graphics") -CHIPSET(0x56a4, dg2_g12, "DG2", "Intel(R) Graphics") -CHIPSET(0x56a5, dg2_g11, "DG2", "Intel(R) Graphics") -CHIPSET(0x56a6, dg2_g11, "DG2", "Intel(R) Graphics") +/* CHIPSET(0x56a0, dg2_g10, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x56a1, dg2_g10, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x56a2, dg2_g10, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x56a3, dg2_g12, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x56a4, dg2_g12, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x56a5, dg2_g11, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x56a6, dg2_g11, "DG2", "Intel(R) Graphics") */ CHIPSET(0x56b0, dg2_g11, "DG2", "Intel(R) Graphics") -CHIPSET(0x56b1, dg2_g11, "DG2", "Intel(R) Graphics") +/* CHIPSET(0x56b1, dg2_g11, "DG2", "Intel(R) Graphics") */ CHIPSET(0x56b2, dg2_g12, "DG2", "Intel(R) Graphics") -CHIPSET(0x56b3, dg2_g12, "DG2", "Intel(R) Graphics") -CHIPSET(0x56c0, dg2_g10, "ATS-M", "Intel(R) Graphics") -CHIPSET(0x56c1, dg2_g11, "ATS-M", "Intel(R) Graphics") -#endif +/* CHIPSET(0x56b3, dg2_g12, "DG2", "Intel(R) Graphics") */ +/* CHIPSET(0x56c0, dg2_g10, "ATS-M", "Intel(R) Graphics") */ +/* CHIPSET(0x56c1, dg2_g11, "ATS-M", "Intel(R) Graphics") */ diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c index b69831f9cbf..45381a43596 100644 --- a/src/intel/dev/intel_device_info.c +++ b/src/intel/dev/intel_device_info.c @@ -71,6 +71,7 @@ static const struct { { "adl", 0x4680 }, { "sg1", 0x4907 }, { "rpl", 0xa780 }, + { "dg2", 0x5690 }, }; /** @@ -1072,17 +1073,17 @@ static const struct intel_device_info intel_device_info_sg1 = { .has_coarse_pixel_primitive_and_cb = true, \ .has_mesh_shading = true -UNUSED static const struct intel_device_info intel_device_info_dg2_g10 = { +static const struct intel_device_info intel_device_info_dg2_g10 = { DG2_FEATURES, .platform = INTEL_PLATFORM_DG2_G10, }; -UNUSED static const struct intel_device_info intel_device_info_dg2_g11 = { +static const struct intel_device_info intel_device_info_dg2_g11 = { DG2_FEATURES, .platform = INTEL_PLATFORM_DG2_G11, }; -UNUSED static const struct intel_device_info intel_device_info_dg2_g12 = { +static const struct intel_device_info intel_device_info_dg2_g12 = { DG2_FEATURES, .platform = INTEL_PLATFORM_DG2_G12, };