intel: Get information about pixel pipes subslices.
v2: Use 1 instead of 1UL (Ken).
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32344dc581
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@ -1073,6 +1073,7 @@ reset_masks(struct gen_device_info *devinfo)
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memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
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memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
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memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
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memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
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memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
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memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
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memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
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}
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}
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static void
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static void
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@ -1098,7 +1099,7 @@ update_from_topology(struct gen_device_info *devinfo,
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uint32_t n_subslices = 0;
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uint32_t n_subslices = 0;
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for (int s = 0; s < topology->max_slices; s++) {
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for (int s = 0; s < topology->max_slices; s++) {
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if ((devinfo->slice_masks & (1UL << s)) == 0)
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if ((devinfo->slice_masks & (1 << s)) == 0)
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continue;
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continue;
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for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
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for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
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@ -1109,6 +1110,23 @@ update_from_topology(struct gen_device_info *devinfo,
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}
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}
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assert(n_subslices > 0);
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assert(n_subslices > 0);
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if (devinfo->gen == 11) {
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/* On ICL we only have one slice */
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assert(devinfo->slice_masks == 1);
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/* Count the number of subslices on each pixel pipe. Assume that
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* subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
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*/
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unsigned subslices = devinfo->subslice_masks[0];
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unsigned ss = 0;
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while (subslices > 0) {
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if (subslices & 1)
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devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
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subslices >>= 1;
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ss++;
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}
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}
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uint32_t eu_mask_len =
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uint32_t eu_mask_len =
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topology->eu_stride * topology->max_subslices * topology->max_slices;
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topology->eu_stride * topology->max_subslices * topology->max_slices;
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assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
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assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
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@ -39,6 +39,7 @@ struct drm_i915_query_topology_info;
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#define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gen10 */
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#define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gen10 */
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#define GEN_DEVICE_MAX_SUBSLICES (8) /* Maximum on gen11 */
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#define GEN_DEVICE_MAX_SUBSLICES (8) /* Maximum on gen11 */
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#define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
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#define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
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#define GEN_DEVICE_MAX_PIXEL_PIPES (2) /* Maximum on gen11 */
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/**
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/**
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* Intel hardware information and quirks
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* Intel hardware information and quirks
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@ -124,6 +125,11 @@ struct gen_device_info
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*/
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*/
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unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
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unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
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/**
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* Number of subslices on each pixel pipe (ICL).
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*/
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unsigned ppipe_subslices[GEN_DEVICE_MAX_PIXEL_PIPES];
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/**
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/**
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* Upper bound of number of EU per subslice (some SKUs might have just 1 EU
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* Upper bound of number of EU per subslice (some SKUs might have just 1 EU
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* fused across all subslices, like 47 EUs, in which case this number won't
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* fused across all subslices, like 47 EUs, in which case this number won't
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