nvir: don't use designated initialisers in C++ code
This feature only available since C++20.
Fixes: fa0a241b33 ("nvir/nir: move nir options to codegen")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3114
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5430>
This commit is contained in:
Yevhenii Kolesnikov
parent
013d096d15
commit
ad00159070
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@ -3355,106 +3355,106 @@ Program::makeFromNIR(struct nv50_ir_prog_info *info)
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static nir_shader_compiler_options
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nvir_nir_shader_compiler_options(int chipset)
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{
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return {
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.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET),
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.lower_ffma = false,
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.fuse_ffma = false, /* nir doesn't track mad vs fma */
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.lower_flrp16 = (chipset >= NVISA_GV100_CHIPSET),
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.lower_flrp32 = true,
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.lower_flrp64 = true,
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.lower_fpow = false, // TODO: nir's lowering is broken, or we could use it
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.lower_fsat = false,
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.lower_fsqrt = false, // TODO: only before gm200
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.lower_sincos = false,
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.lower_fmod = true,
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.lower_bitfield_extract = false,
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.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET),
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.lower_bitfield_insert = false,
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.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET),
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.lower_bitfield_insert_to_bitfield_select = false,
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.lower_bitfield_reverse = false,
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.lower_bit_count = false,
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.lower_ifind_msb = false,
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.lower_find_lsb = false,
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.lower_uadd_carry = true, // TODO
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.lower_usub_borrow = true, // TODO
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.lower_mul_high = false,
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.lower_negate = false,
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.lower_sub = true,
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.lower_scmp = true, // TODO: not implemented yet
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.lower_vector_cmp = false,
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.lower_idiv = true,
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.lower_bitops = false,
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.lower_isign = (chipset >= NVISA_GV100_CHIPSET),
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.lower_fsign = (chipset >= NVISA_GV100_CHIPSET),
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.lower_fdph = false,
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.lower_fdot = false,
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.fdot_replicates = false, // TODO
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.lower_ffloor = false, // TODO
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.lower_ffract = true,
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.lower_fceil = false, // TODO
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.lower_ftrunc = false,
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.lower_ldexp = true,
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.lower_pack_half_2x16 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_unpack_half_2x16 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_unorm_4x8 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_pack_split = false,
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.lower_extract_byte = (chipset < NVISA_GM107_CHIPSET),
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.lower_extract_word = (chipset < NVISA_GM107_CHIPSET),
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.lower_all_io_to_temps = false,
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.lower_all_io_to_elements = false,
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.vertex_id_zero_based = false,
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.lower_base_vertex = false,
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.lower_helper_invocation = false,
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.optimize_sample_mask_in = false,
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.lower_cs_local_index_from_id = true,
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.lower_cs_local_id_from_index = false,
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.lower_device_index_to_zero = false, // TODO
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.lower_wpos_pntc = false, // TODO
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.lower_hadd = true, // TODO
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.lower_add_sat = true, // TODO
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.vectorize_io = false,
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.lower_to_scalar = true,
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.unify_interfaces = false,
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.use_interpolated_input_intrinsics = true,
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.lower_mul_2x32_64 = true, // TODO
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.lower_rotate = (chipset < NVISA_GV100_CHIPSET),
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.has_imul24 = false,
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.intel_vec4 = false,
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.max_unroll_iterations = 32,
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.lower_int64_options = (nir_lower_int64_options) (
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_isign64 : 0) |
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nir_lower_divmod64 |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_high64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_mov64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_icmp64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_iabs64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ineg64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_logic64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_minmax64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_shift64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_2x32_64 : 0) |
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((chipset >= NVISA_GM107_CHIPSET) ? nir_lower_extract64 : 0) |
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nir_lower_ufind_msb64
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),
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.lower_doubles_options = (nir_lower_doubles_options) (
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_drcp : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dsqrt : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_drsq : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dfract : 0) |
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nir_lower_dmod |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dsub : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ddiv : 0)
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)
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};
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nir_shader_compiler_options op = {};
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op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_ffma = false;
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op.fuse_ffma = false; /* nir doesn't track mad vs fma */
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op.lower_flrp16 = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_flrp32 = true;
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op.lower_flrp64 = true;
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op.lower_fpow = false; // TODO: nir's lowering is broken, or we could use it
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op.lower_fsat = false;
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op.lower_fsqrt = false; // TODO: only before gm200
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op.lower_sincos = false;
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op.lower_fmod = true;
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op.lower_bitfield_extract = false;
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op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_bitfield_insert = false;
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op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_bitfield_insert_to_bitfield_select = false;
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op.lower_bitfield_reverse = false;
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op.lower_bit_count = false;
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op.lower_ifind_msb = false;
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op.lower_find_lsb = false;
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op.lower_uadd_carry = true; // TODO
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op.lower_usub_borrow = true; // TODO
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op.lower_mul_high = false;
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op.lower_negate = false;
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op.lower_sub = true;
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op.lower_scmp = true; // TODO: not implemented yet
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op.lower_vector_cmp = false;
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op.lower_idiv = true;
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op.lower_bitops = false;
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op.lower_isign = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_fsign = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_fdph = false;
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op.lower_fdot = false;
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op.fdot_replicates = false; // TODO
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op.lower_ffloor = false; // TODO
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op.lower_ffract = true;
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op.lower_fceil = false; // TODO
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op.lower_ftrunc = false;
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op.lower_ldexp = true;
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op.lower_pack_half_2x16 = true;
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op.lower_pack_unorm_2x16 = true;
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op.lower_pack_snorm_2x16 = true;
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op.lower_pack_unorm_4x8 = true;
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op.lower_pack_snorm_4x8 = true;
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op.lower_unpack_half_2x16 = true;
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op.lower_unpack_unorm_2x16 = true;
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op.lower_unpack_snorm_2x16 = true;
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op.lower_unpack_unorm_4x8 = true;
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op.lower_unpack_snorm_4x8 = true;
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op.lower_pack_split = false;
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op.lower_extract_byte = (chipset < NVISA_GM107_CHIPSET);
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op.lower_extract_word = (chipset < NVISA_GM107_CHIPSET);
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op.lower_all_io_to_temps = false;
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op.lower_all_io_to_elements = false;
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op.vertex_id_zero_based = false;
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op.lower_base_vertex = false;
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op.lower_helper_invocation = false;
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op.optimize_sample_mask_in = false;
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op.lower_cs_local_index_from_id = true;
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op.lower_cs_local_id_from_index = false;
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op.lower_device_index_to_zero = false; // TODO
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op.lower_wpos_pntc = false; // TODO
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op.lower_hadd = true; // TODO
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op.lower_add_sat = true; // TODO
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op.vectorize_io = false;
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op.lower_to_scalar = true;
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op.unify_interfaces = false;
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op.use_interpolated_input_intrinsics = true;
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op.lower_mul_2x32_64 = true; // TODO
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op.lower_rotate = (chipset < NVISA_GV100_CHIPSET);
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op.has_imul24 = false;
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op.intel_vec4 = false;
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op.max_unroll_iterations = 32;
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op.lower_int64_options = (nir_lower_int64_options) (
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_isign64 : 0) |
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nir_lower_divmod64 |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_high64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_mov64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_icmp64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_iabs64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ineg64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_logic64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_minmax64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_shift64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_2x32_64 : 0) |
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((chipset >= NVISA_GM107_CHIPSET) ? nir_lower_extract64 : 0) |
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nir_lower_ufind_msb64
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);
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op.lower_doubles_options = (nir_lower_doubles_options) (
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_drcp : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dsqrt : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_drsq : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dfract : 0) |
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nir_lower_dmod |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dsub : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ddiv : 0)
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);
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return op;
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}
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static const nir_shader_compiler_options gf100_nir_shader_compiler_options =
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