include/uapi: Update drm_fourcc.h from kernel
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
v2. Pull in the header from drm-next at commit
9035039e1ed691cd893777a42e048003a2f349d6
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
This commit is contained in:
Anuj Phogat
Marge Bot
parent
2bc8c61fd0
commit
acba3efe69
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@ -104,6 +104,12 @@ extern "C" {
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/* 8 bpp Red */
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#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
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/* 10 bpp Red */
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#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
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/* 12 bpp Red */
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#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
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/* 16 bpp Red */
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#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
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@ -308,6 +314,13 @@ extern "C" {
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*/
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#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
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/* 2 plane YCbCr420.
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* 3 10 bit components and 2 padding bits packed into 4 bytes.
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* index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
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* index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
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*/
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#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
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/* 3 plane non-subsampled (444) YCbCr
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* 16 bits per component, but only 10 bits are used and 6 bits are padded
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* index 0: Y plane, [15:0] Y:x [10:6] little endian
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@ -373,6 +386,12 @@ extern "C" {
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#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
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#define fourcc_mod_get_vendor(modifier) \
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(((modifier) >> 56) & 0xff)
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#define fourcc_mod_is_vendor(modifier, vendor) \
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(fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
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#define fourcc_mod_code(vendor, val) \
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((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
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@ -553,6 +572,53 @@ extern "C" {
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
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/*
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* Intel Tile 4 layout
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*
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* This is a tiled layout using 4KB tiles in a row-major layout. It has the same
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* shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
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* only differs from Tile Y at the 256B granularity in between. At this
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* granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
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* of 64B x 8 rows.
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*/
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#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
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/*
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* Intel color control surfaces (CCS) for DG2 render compression.
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*
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* The main surface is Tile 4 and at plane index 0. The CCS data is stored
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* outside of the GEM object in a reserved memory area dedicated for the
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* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
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* main surface pitch is required to be a multiple of four Tile 4 widths.
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*/
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#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
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/*
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* Intel color control surfaces (CCS) for DG2 media compression.
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*
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* The main surface is Tile 4 and at plane index 0. For semi-planar formats
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* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
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* 0 and 1, respectively. The CCS for all planes are stored outside of the
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* GEM object in a reserved memory area dedicated for the storage of the
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* CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
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* pitch is required to be a multiple of four Tile 4 widths.
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*/
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#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
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/*
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* Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
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*
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* The main surface is Tile 4 and at plane index 0. The CCS data is stored
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* outside of the GEM object in a reserved memory area dedicated for the
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* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
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* main surface pitch is required to be a multiple of four Tile 4 widths. The
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* clear color is stored at plane index 1 and the pitch should be ignored. The
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* format of the 256 bits of clear color data matches the one used for the
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* I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
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* for details.
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*/
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#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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@ -736,7 +802,7 @@ extern "C" {
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* which corresponds to the "generic" kind used for simple single-sample
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* uncompressed color formats on Fermi - Volta GPUs.
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*/
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static __inline__ __u64
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static inline __u64
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drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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{
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if (!(modifier & 0x10) || (modifier & (0xff << 12)))
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@ -842,6 +908,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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* and UV. Some SAND-using hardware stores UV in a separate tiled
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* image from Y to reduce the column height, which is not supported
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* with these modifiers.
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*
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* The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
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* supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
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* wide, but as this is a 10 bpp format that translates to 96 pixels.
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*/
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#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
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