radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.c
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
parent
0ca8294ece
commit
ac72a6bd0b
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@ -35,6 +35,7 @@ C_SOURCES := \
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si_shader_tgsi_alu.c \
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si_shader_tgsi_mem.c \
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si_shader_tgsi_setup.c \
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si_shaderlib_tgsi.c \
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si_state.c \
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si_state_binning.c \
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si_state_draw.c \
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@ -51,6 +51,7 @@ files_libradeonsi = files(
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'si_shader_tgsi_alu.c',
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'si_shader_tgsi_mem.c',
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'si_shader_tgsi_setup.c',
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'si_shaderlib_tgsi.c',
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'si_state.c',
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'si_state.h',
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'si_state_binning.c',
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@ -1205,6 +1205,12 @@ void si_init_query_functions(struct si_context *sctx);
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void si_suspend_queries(struct si_context *sctx);
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void si_resume_queries(struct si_context *sctx);
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/* si_shaderlib_tgsi.c */
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void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
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unsigned num_layers);
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void *si_create_fixed_func_tcs(struct si_context *sctx);
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void *si_create_query_result_cs(struct si_context *sctx);
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/* si_test_dma.c */
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void si_test_dma(struct si_screen *sscreen);
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@ -30,7 +30,6 @@
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#include "util/u_upload_mgr.h"
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#include "util/os_time.h"
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#include "util/u_suballoc.h"
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#include "tgsi/tgsi_text.h"
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#include "amd/common/sid.h"
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#define SI_MAX_STREAMS 4
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@ -1389,222 +1388,6 @@ bool si_query_hw_get_result(struct si_context *sctx,
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return true;
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}
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/* Create the compute shader that is used to collect the results.
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*
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* One compute grid with a single thread is launched for every query result
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* buffer. The thread (optionally) reads a previous summary buffer, then
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* accumulates data from the query result buffer, and writes the result either
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* to a summary buffer to be consumed by the next grid invocation or to the
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* user-supplied buffer.
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*
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* Data layout:
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*
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* CONST
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* 0.x = end_offset
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* 0.y = result_stride
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* 0.z = result_count
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* 0.w = bit field:
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* 1: read previously accumulated values
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* 2: write accumulated values for chaining
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* 4: write result available
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* 8: convert result to boolean (0/1)
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* 16: only read one dword and use that as result
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* 32: apply timestamp conversion
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* 64: store full 64 bits result
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* 128: store signed 32 bits result
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* 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
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* 1.x = fence_offset
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* 1.y = pair_stride
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* 1.z = pair_count
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*
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* BUFFER[0] = query result buffer
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* BUFFER[1] = previous summary buffer
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* BUFFER[2] = next summary buffer or user-supplied buffer
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*/
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static void si_create_query_result_shader(struct si_context *sctx)
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{
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/* TEMP[0].xy = accumulated result so far
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* TEMP[0].z = result not available
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*
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* TEMP[1].x = current result index
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* TEMP[1].y = current pair index
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*/
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static const char text_tmpl[] =
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"COMP\n"
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"PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
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"PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
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"PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
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"DCL BUFFER[0]\n"
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"DCL BUFFER[1]\n"
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"DCL BUFFER[2]\n"
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"DCL CONST[0][0..1]\n"
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"DCL TEMP[0..5]\n"
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"IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
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"IMM[1] UINT32 {1, 2, 4, 8}\n"
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"IMM[2] UINT32 {16, 32, 64, 128}\n"
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"IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
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"IMM[4] UINT32 {256, 0, 0, 0}\n"
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"AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
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"UIF TEMP[5]\n"
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/* Check result availability. */
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"LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
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"ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
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"MOV TEMP[1], TEMP[0].zzzz\n"
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"NOT TEMP[0].z, TEMP[0].zzzz\n"
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/* Load result if available. */
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"UIF TEMP[1]\n"
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"LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
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"ENDIF\n"
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"ELSE\n"
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/* Load previously accumulated result if requested. */
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"MOV TEMP[0], IMM[0].xxxx\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
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"UIF TEMP[4]\n"
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"LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
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"ENDIF\n"
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"MOV TEMP[1].x, IMM[0].xxxx\n"
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"BGNLOOP\n"
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/* Break if accumulated result so far is not available. */
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"UIF TEMP[0].zzzz\n"
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"BRK\n"
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"ENDIF\n"
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/* Break if result_index >= result_count. */
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"USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
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"UIF TEMP[5]\n"
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"BRK\n"
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"ENDIF\n"
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/* Load fence and check result availability */
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"UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
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"LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
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"ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
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"NOT TEMP[0].z, TEMP[0].zzzz\n"
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"UIF TEMP[0].zzzz\n"
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"BRK\n"
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"ENDIF\n"
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"MOV TEMP[1].y, IMM[0].xxxx\n"
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"BGNLOOP\n"
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/* Load start and end. */
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"UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
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"UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
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"LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
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"UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
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"LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
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"U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
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"AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
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"UIF TEMP[5].zzzz\n"
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/* Load second start/end half-pair and
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* take the difference
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*/
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"UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
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"LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
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"LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
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"U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
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"U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
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"ENDIF\n"
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"U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
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/* Increment pair index */
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"UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
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"USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
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"UIF TEMP[5]\n"
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"BRK\n"
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"ENDIF\n"
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"ENDLOOP\n"
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/* Increment result index */
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"UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
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"ENDLOOP\n"
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"ENDIF\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
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"UIF TEMP[4]\n"
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/* Store accumulated data for chaining. */
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"STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
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"ELSE\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
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"UIF TEMP[4]\n"
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/* Store result availability. */
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"NOT TEMP[0].z, TEMP[0]\n"
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"AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
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"STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
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"UIF TEMP[4]\n"
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"STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
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"ENDIF\n"
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"ELSE\n"
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/* Store result if it is available. */
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"NOT TEMP[4], TEMP[0].zzzz\n"
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"UIF TEMP[4]\n"
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/* Apply timestamp conversion */
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"AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
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"UIF TEMP[4]\n"
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"U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
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"U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
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"ENDIF\n"
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/* Convert to boolean */
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"AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
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"UIF TEMP[4]\n"
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"U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
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"AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
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"MOV TEMP[0].y, IMM[0].xxxx\n"
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"ENDIF\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
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"UIF TEMP[4]\n"
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"STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
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"ELSE\n"
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/* Clamping */
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"UIF TEMP[0].yyyy\n"
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"MOV TEMP[0].x, IMM[0].wwww\n"
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"ENDIF\n"
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"AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
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"UIF TEMP[4]\n"
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"UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
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"ENDIF\n"
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"STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
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"ENDIF\n"
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"ENDIF\n"
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"ENDIF\n"
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"ENDIF\n"
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"END\n";
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char text[sizeof(text_tmpl) + 32];
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struct tgsi_token tokens[1024];
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struct pipe_compute_state state = {};
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/* Hard code the frequency into the shader so that the backend can
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* use the full range of optimizations for divide-by-constant.
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*/
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snprintf(text, sizeof(text), text_tmpl,
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sctx->screen->info.clock_crystal_freq);
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if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
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assert(false);
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return;
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}
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state.ir_type = PIPE_SHADER_IR_TGSI;
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state.prog = tokens;
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sctx->query_result_shader = sctx->b.create_compute_state(&sctx->b, &state);
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}
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static void si_restore_qbo_state(struct si_context *sctx,
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struct si_qbo_state *st)
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{
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@ -1647,7 +1430,7 @@ static void si_query_hw_get_result_resource(struct si_context *sctx,
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} consts;
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if (!sctx->query_result_shader) {
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si_create_query_result_shader(sctx);
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sctx->query_result_shader = si_create_query_result_cs(sctx);
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if (!sctx->query_result_shader)
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return;
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}
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@ -0,0 +1,336 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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#include "tgsi/tgsi_text.h"
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#include "tgsi/tgsi_ureg.h"
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void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
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unsigned num_layers)
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{
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unsigned vs_blit_property;
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void **vs;
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switch (type) {
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case UTIL_BLITTER_ATTRIB_NONE:
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vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
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&sctx->vs_blit_pos;
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vs_blit_property = SI_VS_BLIT_SGPRS_POS;
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break;
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case UTIL_BLITTER_ATTRIB_COLOR:
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vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
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&sctx->vs_blit_color;
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vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
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break;
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case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
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case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
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assert(num_layers == 1);
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vs = &sctx->vs_blit_texcoord;
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vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
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break;
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default:
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assert(0);
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return NULL;
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}
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if (*vs)
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return *vs;
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struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
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if (!ureg)
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return NULL;
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/* Tell the shader to load VS inputs from SGPRs: */
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ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
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ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
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/* This is just a pass-through shader with 1-3 MOV instructions. */
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ureg_MOV(ureg,
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ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
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ureg_DECL_vs_input(ureg, 0));
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if (type != UTIL_BLITTER_ATTRIB_NONE) {
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ureg_MOV(ureg,
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ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
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ureg_DECL_vs_input(ureg, 1));
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}
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if (num_layers > 1) {
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struct ureg_src instance_id =
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ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
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struct ureg_dst layer =
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ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
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ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
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ureg_scalar(instance_id, TGSI_SWIZZLE_X));
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}
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ureg_END(ureg);
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*vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
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return *vs;
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}
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/**
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* This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
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* VS passes its outputs to TES directly, so the fixed-function shader only
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* has to write TESSOUTER and TESSINNER.
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*/
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void *si_create_fixed_func_tcs(struct si_context *sctx)
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{
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struct ureg_src outer, inner;
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struct ureg_dst tessouter, tessinner;
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struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
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if (!ureg)
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return NULL;
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outer = ureg_DECL_system_value(ureg,
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TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
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inner = ureg_DECL_system_value(ureg,
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TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
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tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
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tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
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ureg_MOV(ureg, tessouter, outer);
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ureg_MOV(ureg, tessinner, inner);
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ureg_END(ureg);
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return ureg_create_shader_and_destroy(ureg, &sctx->b);
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}
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/* Create the compute shader that is used to collect the results.
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*
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* One compute grid with a single thread is launched for every query result
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* buffer. The thread (optionally) reads a previous summary buffer, then
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* accumulates data from the query result buffer, and writes the result either
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* to a summary buffer to be consumed by the next grid invocation or to the
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* user-supplied buffer.
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*
|
||||
* Data layout:
|
||||
*
|
||||
* CONST
|
||||
* 0.x = end_offset
|
||||
* 0.y = result_stride
|
||||
* 0.z = result_count
|
||||
* 0.w = bit field:
|
||||
* 1: read previously accumulated values
|
||||
* 2: write accumulated values for chaining
|
||||
* 4: write result available
|
||||
* 8: convert result to boolean (0/1)
|
||||
* 16: only read one dword and use that as result
|
||||
* 32: apply timestamp conversion
|
||||
* 64: store full 64 bits result
|
||||
* 128: store signed 32 bits result
|
||||
* 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
|
||||
* 1.x = fence_offset
|
||||
* 1.y = pair_stride
|
||||
* 1.z = pair_count
|
||||
*
|
||||
* BUFFER[0] = query result buffer
|
||||
* BUFFER[1] = previous summary buffer
|
||||
* BUFFER[2] = next summary buffer or user-supplied buffer
|
||||
*/
|
||||
void *si_create_query_result_cs(struct si_context *sctx)
|
||||
{
|
||||
/* TEMP[0].xy = accumulated result so far
|
||||
* TEMP[0].z = result not available
|
||||
*
|
||||
* TEMP[1].x = current result index
|
||||
* TEMP[1].y = current pair index
|
||||
*/
|
||||
static const char text_tmpl[] =
|
||||
"COMP\n"
|
||||
"PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
|
||||
"PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
|
||||
"PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
|
||||
"DCL BUFFER[0]\n"
|
||||
"DCL BUFFER[1]\n"
|
||||
"DCL BUFFER[2]\n"
|
||||
"DCL CONST[0][0..1]\n"
|
||||
"DCL TEMP[0..5]\n"
|
||||
"IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
|
||||
"IMM[1] UINT32 {1, 2, 4, 8}\n"
|
||||
"IMM[2] UINT32 {16, 32, 64, 128}\n"
|
||||
"IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
|
||||
"IMM[4] UINT32 {256, 0, 0, 0}\n"
|
||||
|
||||
"AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
|
||||
"UIF TEMP[5]\n"
|
||||
/* Check result availability. */
|
||||
"LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
|
||||
"ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
|
||||
"MOV TEMP[1], TEMP[0].zzzz\n"
|
||||
"NOT TEMP[0].z, TEMP[0].zzzz\n"
|
||||
|
||||
/* Load result if available. */
|
||||
"UIF TEMP[1]\n"
|
||||
"LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
|
||||
"ENDIF\n"
|
||||
"ELSE\n"
|
||||
/* Load previously accumulated result if requested. */
|
||||
"MOV TEMP[0], IMM[0].xxxx\n"
|
||||
"AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
|
||||
"UIF TEMP[4]\n"
|
||||
"LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
|
||||
"ENDIF\n"
|
||||
|
||||
"MOV TEMP[1].x, IMM[0].xxxx\n"
|
||||
"BGNLOOP\n"
|
||||
/* Break if accumulated result so far is not available. */
|
||||
"UIF TEMP[0].zzzz\n"
|
||||
"BRK\n"
|
||||
"ENDIF\n"
|
||||
|
||||
/* Break if result_index >= result_count. */
|
||||
"USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
|
||||
"UIF TEMP[5]\n"
|
||||
"BRK\n"
|
||||
"ENDIF\n"
|
||||
|
||||
/* Load fence and check result availability */
|
||||
"UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
|
||||
"LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
|
||||
"ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
|
||||
"NOT TEMP[0].z, TEMP[0].zzzz\n"
|
||||
"UIF TEMP[0].zzzz\n"
|
||||
"BRK\n"
|
||||
"ENDIF\n"
|
||||
|
||||
"MOV TEMP[1].y, IMM[0].xxxx\n"
|
||||
"BGNLOOP\n"
|
||||
/* Load start and end. */
|
||||
"UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
|
||||
"UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
|
||||
"LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
|
||||
|
||||
"UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
|
||||
"LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
|
||||
|
||||
"U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
|
||||
|
||||
"AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
|
||||
"UIF TEMP[5].zzzz\n"
|
||||
/* Load second start/end half-pair and
|
||||
* take the difference
|
||||
*/
|
||||
"UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
|
||||
"LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
|
||||
"LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
|
||||
|
||||
"U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
|
||||
"U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
|
||||
"ENDIF\n"
|
||||
|
||||
"U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
|
||||
|
||||
/* Increment pair index */
|
||||
"UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
|
||||
"USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
|
||||
"UIF TEMP[5]\n"
|
||||
"BRK\n"
|
||||
"ENDIF\n"
|
||||
"ENDLOOP\n"
|
||||
|
||||
/* Increment result index */
|
||||
"UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
|
||||
"ENDLOOP\n"
|
||||
"ENDIF\n"
|
||||
|
||||
"AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
|
||||
"UIF TEMP[4]\n"
|
||||
/* Store accumulated data for chaining. */
|
||||
"STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
|
||||
"ELSE\n"
|
||||
"AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
|
||||
"UIF TEMP[4]\n"
|
||||
/* Store result availability. */
|
||||
"NOT TEMP[0].z, TEMP[0]\n"
|
||||
"AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
|
||||
"STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
|
||||
|
||||
"AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
|
||||
"UIF TEMP[4]\n"
|
||||
"STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
|
||||
"ENDIF\n"
|
||||
"ELSE\n"
|
||||
/* Store result if it is available. */
|
||||
"NOT TEMP[4], TEMP[0].zzzz\n"
|
||||
"UIF TEMP[4]\n"
|
||||
/* Apply timestamp conversion */
|
||||
"AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
|
||||
"UIF TEMP[4]\n"
|
||||
"U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
|
||||
"U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
|
||||
"ENDIF\n"
|
||||
|
||||
/* Convert to boolean */
|
||||
"AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
|
||||
"UIF TEMP[4]\n"
|
||||
"U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
|
||||
"AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
|
||||
"MOV TEMP[0].y, IMM[0].xxxx\n"
|
||||
"ENDIF\n"
|
||||
|
||||
"AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
|
||||
"UIF TEMP[4]\n"
|
||||
"STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
|
||||
"ELSE\n"
|
||||
/* Clamping */
|
||||
"UIF TEMP[0].yyyy\n"
|
||||
"MOV TEMP[0].x, IMM[0].wwww\n"
|
||||
"ENDIF\n"
|
||||
|
||||
"AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
|
||||
"UIF TEMP[4]\n"
|
||||
"UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
|
||||
"ENDIF\n"
|
||||
|
||||
"STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
|
||||
"ENDIF\n"
|
||||
"ENDIF\n"
|
||||
"ENDIF\n"
|
||||
"ENDIF\n"
|
||||
|
||||
"END\n";
|
||||
|
||||
char text[sizeof(text_tmpl) + 32];
|
||||
struct tgsi_token tokens[1024];
|
||||
struct pipe_compute_state state = {};
|
||||
|
||||
/* Hard code the frequency into the shader so that the backend can
|
||||
* use the full range of optimizations for divide-by-constant.
|
||||
*/
|
||||
snprintf(text, sizeof(text), text_tmpl,
|
||||
sctx->screen->info.clock_crystal_freq);
|
||||
|
||||
if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
|
||||
assert(false);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
state.ir_type = PIPE_SHADER_IR_TGSI;
|
||||
state.prog = tokens;
|
||||
|
||||
return sctx->b.create_compute_state(&sctx->b, &state);
|
||||
}
|
|
@ -514,8 +514,6 @@ void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
|
|||
void si_get_active_slot_masks(const struct tgsi_shader_info *info,
|
||||
uint32_t *const_and_shader_buffers,
|
||||
uint64_t *samplers_and_images);
|
||||
void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
|
||||
unsigned num_layers);
|
||||
|
||||
/* si_state_draw.c */
|
||||
void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
|
||||
|
|
|
@ -1543,7 +1543,7 @@ void si_draw_rectangle(struct blitter_context *blitter,
|
|||
case UTIL_BLITTER_ATTRIB_NONE:;
|
||||
}
|
||||
|
||||
pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
|
||||
pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
|
||||
|
||||
struct pipe_draw_info info = {};
|
||||
info.mode = SI_PRIM_RECTANGLE_LIST;
|
||||
|
|
|
@ -27,7 +27,6 @@
|
|||
|
||||
#include "compiler/nir/nir_serialize.h"
|
||||
#include "tgsi/tgsi_parse.h"
|
||||
#include "tgsi/tgsi_ureg.h"
|
||||
#include "util/hash_table.h"
|
||||
#include "util/crc32.h"
|
||||
#include "util/u_async_debug.h"
|
||||
|
@ -3100,38 +3099,6 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
|
|||
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
|
||||
* VS passes its outputs to TES directly, so the fixed-function shader only
|
||||
* has to write TESSOUTER and TESSINNER.
|
||||
*/
|
||||
static void si_generate_fixed_func_tcs(struct si_context *sctx)
|
||||
{
|
||||
struct ureg_src outer, inner;
|
||||
struct ureg_dst tessouter, tessinner;
|
||||
struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
|
||||
|
||||
if (!ureg)
|
||||
return; /* if we get here, we're screwed */
|
||||
|
||||
assert(!sctx->fixed_func_tcs_shader.cso);
|
||||
|
||||
outer = ureg_DECL_system_value(ureg,
|
||||
TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
|
||||
inner = ureg_DECL_system_value(ureg,
|
||||
TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
|
||||
|
||||
tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
|
||||
tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
|
||||
|
||||
ureg_MOV(ureg, tessouter, outer);
|
||||
ureg_MOV(ureg, tessinner, inner);
|
||||
ureg_END(ureg);
|
||||
|
||||
sctx->fixed_func_tcs_shader.cso =
|
||||
ureg_create_shader_and_destroy(ureg, &sctx->b);
|
||||
}
|
||||
|
||||
static void si_update_vgt_shader_config(struct si_context *sctx)
|
||||
{
|
||||
/* Calculate the index of the config.
|
||||
|
@ -3209,7 +3176,8 @@ bool si_update_shaders(struct si_context *sctx)
|
|||
si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
|
||||
} else {
|
||||
if (!sctx->fixed_func_tcs_shader.cso) {
|
||||
si_generate_fixed_func_tcs(sctx);
|
||||
sctx->fixed_func_tcs_shader.cso =
|
||||
si_create_fixed_func_tcs(sctx);
|
||||
if (!sctx->fixed_func_tcs_shader.cso)
|
||||
return false;
|
||||
}
|
||||
|
@ -3388,70 +3356,6 @@ static void si_emit_scratch_state(struct si_context *sctx)
|
|||
}
|
||||
}
|
||||
|
||||
void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
|
||||
unsigned num_layers)
|
||||
{
|
||||
unsigned vs_blit_property;
|
||||
void **vs;
|
||||
|
||||
switch (type) {
|
||||
case UTIL_BLITTER_ATTRIB_NONE:
|
||||
vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
|
||||
&sctx->vs_blit_pos;
|
||||
vs_blit_property = SI_VS_BLIT_SGPRS_POS;
|
||||
break;
|
||||
case UTIL_BLITTER_ATTRIB_COLOR:
|
||||
vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
|
||||
&sctx->vs_blit_color;
|
||||
vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
|
||||
break;
|
||||
case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
|
||||
case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
|
||||
assert(num_layers == 1);
|
||||
vs = &sctx->vs_blit_texcoord;
|
||||
vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
return NULL;
|
||||
}
|
||||
if (*vs)
|
||||
return *vs;
|
||||
|
||||
struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
|
||||
if (!ureg)
|
||||
return NULL;
|
||||
|
||||
/* Tell the shader to load VS inputs from SGPRs: */
|
||||
ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
|
||||
ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
|
||||
|
||||
/* This is just a pass-through shader with 1-3 MOV instructions. */
|
||||
ureg_MOV(ureg,
|
||||
ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
|
||||
ureg_DECL_vs_input(ureg, 0));
|
||||
|
||||
if (type != UTIL_BLITTER_ATTRIB_NONE) {
|
||||
ureg_MOV(ureg,
|
||||
ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
|
||||
ureg_DECL_vs_input(ureg, 1));
|
||||
}
|
||||
|
||||
if (num_layers > 1) {
|
||||
struct ureg_src instance_id =
|
||||
ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
|
||||
struct ureg_dst layer =
|
||||
ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
|
||||
|
||||
ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
|
||||
ureg_scalar(instance_id, TGSI_SWIZZLE_X));
|
||||
}
|
||||
ureg_END(ureg);
|
||||
|
||||
*vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
|
||||
return *vs;
|
||||
}
|
||||
|
||||
void si_init_shader_functions(struct si_context *sctx)
|
||||
{
|
||||
sctx->atoms.s.spi_map.emit = si_emit_spi_map;
|
||||
|
|
Loading…
Reference in New Issue